Lines Matching refs:Is1H
2922 VIXL_ASSERT((vn.Is1H() && vd.Is1S()) || (vn.Is1S() && vd.Is1D()) ||
2993 V(sqdmlal, NEON_SQDMLAL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
2994 V(sqdmlal2, NEON_SQDMLAL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
2995 V(sqdmlsl, NEON_SQDMLSL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
2996 V(sqdmlsl2, NEON_SQDMLSL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
2997 V(sqdmull, NEON_SQDMULL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
2998 V(sqdmull2, NEON_SQDMULL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
3288 VIXL_ASSERT(vd.Is1H());
3303 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3304 VIXL_ASSERT((rd.GetSizeInBits() == vn.GetSizeInBits()) || vn.Is1H());
3324 VIXL_ASSERT(vd.Is1H() || vd.Is1S() || vd.Is1D());
3325 VIXL_ASSERT((vd.GetSizeInBits() == rn.GetSizeInBits()) || vd.Is1H());
3344 if (vd.Is1H()) {
3347 VIXL_ASSERT(vd.Is1H() || vd.Is1S() || vd.Is1D());
3375 if (vd.Is1H()) {
3394 if (vd.Is1H()) {
3413 if (vd.Is1H()) {
3432 if (vd.Is1H()) {
3451 if (vd.Is1H()) {
3472 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3481 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3490 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3497 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3504 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3511 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3521 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3532 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3542 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3552 if (vd.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3553 VIXL_ASSERT(vd.Is1H() || vd.Is1S() || vd.Is1D());
3564 VIXL_ASSERT(vn.Is1S() || vn.Is1H());
3567 VIXL_ASSERT(vn.Is1D() || vn.Is1H());
3570 VIXL_ASSERT(vd.Is1H());
3704 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3705 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3729 vd.Is1H() || vd.Is4H() || vd.Is8H());
3737 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3738 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3762 vd.Is1H() || vd.Is4H() || vd.Is8H());
3780 vd.Is1H() || vd.Is4H() || vd.Is8H());
3798 vd.Is1H() || vd.Is4H() || vd.Is8H());
3806 if (vd.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3807 VIXL_ASSERT(vd.Is1H() || vd.Is1S() || vd.Is1D());
3820 if (vd.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3821 VIXL_ASSERT(vd.Is1H() || vd.Is1S() || vd.Is1D());
3892 if (vd.Is1H()) { \
4076 VIXL_ASSERT(vd.Is1H());
4149 if (vd.Is1H()) {
4267 if ((SCA_OP_H != 0) && vd.Is1H()) { \
4272 VIXL_ASSERT(vd.Is1H() || vd.Is1S() || vd.Is1D()); \
4275 if (vd.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf)); \
4276 } else if (vd.Is1H()) { \
4406 (vd.Is1H() && vn.Is2H()));
4407 if (vd.Is1H()) {
4419 (vd.Is1H() && vn.Is2H()));
4420 if (vd.Is1H()) {
4432 (vd.Is1H() && vn.Is2H()));
4433 if (vd.Is1H()) {
4445 (vd.Is1H() && vn.Is2H()));
4446 if (vd.Is1H()) {
4458 (vd.Is1H() && vn.Is2H()));
4459 if (vd.Is1H()) {
4606 (vd.Is1D() && vm.Is1D()) || (vd.Is4H() && vm.Is1H()) ||
4607 (vd.Is8H() && vm.Is1H()) || (vd.Is1H() && vm.Is1H()));
4609 (vm.Is1H() && (vm.GetCode() < 16) && (vm_index < 8)));
4626 if (!vm.Is1H()) {
4642 VIXL_ASSERT((vd.Is4H() && vm.Is1H()) || (vd.Is8H() && vm.Is1H()) ||
4643 (vd.Is1H() && vm.Is1H()) || (vd.Is2S() && vm.Is1S()) ||
4645 VIXL_ASSERT((vm.Is1H() && (vm.GetCode() < 16) && (vm_index < 8)) ||
4649 int index_num_bits = vm.Is1H() ? 3 : 2;
4666 VIXL_ASSERT((vd.Is4S() && vn.Is4H() && vm.Is1H()) ||
4667 (vd.Is4S() && vn.Is8H() && vm.Is1H()) ||
4668 (vd.Is1S() && vn.Is1H() && vm.Is1H()) ||
4673 VIXL_ASSERT((vm.Is1H() && (vm.GetCode() < 16) && (vm_index < 8)) ||
4677 int index_num_bits = vm.Is1H() ? 3 : 2;
4913 VIXL_ASSERT((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) ||
5326 VIXL_ASSERT((vn.Is8B() && vd.Is1H()) || (vn.Is16B() && vd.Is1H()) ||
5350 (vn.Is4H() && vd.Is1H()) || (vn.Is8H() && vd.Is1H()) ||
5353 if (vd.Is1H()) {
5397 if (vd.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf)); \
5398 VIXL_ASSERT(vd.Is1S() || vd.Is1H()); \
5527 VIXL_ASSERT((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) ||
6125 VIXL_ASSERT(vd.Is1H() || vd.Is1S() || vd.Is1D());
6135 VIXL_ASSERT(vd.Is1H() || vd.Is1S() || vd.Is1D());