Lines Matching defs:vt4
2620 const VRegister& vt4,
2622 USE(vt2, vt3, vt4);
2624 VIXL_ASSERT(AreSameFormat(vt, vt2, vt3, vt4));
2625 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3, vt4));
2704 const VRegister& vt4,
2706 USE(vt2, vt3, vt4);
2708 VIXL_ASSERT(AreSameFormat(vt, vt2, vt3, vt4));
2709 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3, vt4));
2717 const VRegister& vt4,
2720 USE(vt2, vt3, vt4);
2722 VIXL_ASSERT(AreSameFormat(vt, vt2, vt3, vt4));
2723 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3, vt4));
2731 const VRegister& vt4,
2733 USE(vt2, vt3, vt4);
2735 VIXL_ASSERT(AreSameFormat(vt, vt2, vt3, vt4));
2736 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3, vt4));
2773 const VRegister& vt4,
2775 USE(vt2, vt3, vt4);
2777 VIXL_ASSERT(AreSameFormat(vt, vt2, vt3, vt4));
2778 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3, vt4));
2834 const VRegister& vt4,
2836 USE(vt2, vt3, vt4);
2838 VIXL_ASSERT(AreSameFormat(vt, vt2, vt3, vt4));
2839 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3, vt4));
2847 const VRegister& vt4,
2850 USE(vt2, vt3, vt4);
2852 VIXL_ASSERT(AreSameFormat(vt, vt2, vt3, vt4));
2853 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3, vt4));