Lines Matching defs:vn
316 const VRegister& vn,
321 VIXL_ASSERT(vn.Is16B());
323 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd));
328 const VRegister& vn,
331 NEONTable(vd, vn, vm, NEON_TBL_1v);
336 const VRegister& vn,
341 VIXL_ASSERT(AreSameFormat(vn, vn2));
342 VIXL_ASSERT(AreConsecutive(vn, vn2));
343 NEONTable(vd, vn, vm, NEON_TBL_2v);
348 const VRegister& vn,
354 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3));
355 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3));
356 NEONTable(vd, vn, vm, NEON_TBL_3v);
361 const VRegister& vn,
368 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3, vn4));
369 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3, vn4));
370 NEONTable(vd, vn, vm, NEON_TBL_4v);
375 const VRegister& vn,
378 NEONTable(vd, vn, vm, NEON_TBX_1v);
383 const VRegister& vn,
388 VIXL_ASSERT(AreSameFormat(vn, vn2));
389 VIXL_ASSERT(AreConsecutive(vn, vn2));
390 NEONTable(vd, vn, vm, NEON_TBX_2v);
395 const VRegister& vn,
401 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3));
402 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3));
403 NEONTable(vd, vn, vm, NEON_TBX_3v);
408 const VRegister& vn,
415 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3, vn4));
416 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3, vn4));
417 NEONTable(vd, vn, vm, NEON_TBX_4v);
2918 const VRegister& vn,
2921 VIXL_ASSERT(AreSameFormat(vn, vm));
2922 VIXL_ASSERT((vn.Is1H() && vd.Is1S()) || (vn.Is1S() && vd.Is1D()) ||
2923 (vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) ||
2924 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) ||
2925 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
2929 format = SFormat(vn);
2931 format = VFormat(vn);
2933 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
2938 const VRegister& vn,
2941 VIXL_ASSERT(AreSameFormat(vd, vn));
2945 Emit(VFormat(vm) | vop | Rm(vm) | Rn(vn) | Rd(vd));
2950 const VRegister& vn,
2953 VIXL_ASSERT(AreSameFormat(vm, vn));
2954 VIXL_ASSERT((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
2955 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
2956 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
2957 Emit(VFormat(vd) | vop | Rm(vm) | Rn(vn) | Rd(vd));
2963 V(pmull, NEON_PMULL, vn.IsVector() && vn.Is8B()) \
2964 V(pmull2, NEON_PMULL2, vn.IsVector() && vn.Is16B()) \
2965 V(saddl, NEON_SADDL, vn.IsVector() && vn.IsD()) \
2966 V(saddl2, NEON_SADDL2, vn.IsVector() && vn.IsQ()) \
2967 V(sabal, NEON_SABAL, vn.IsVector() && vn.IsD()) \
2968 V(sabal2, NEON_SABAL2, vn.IsVector() && vn.IsQ()) \
2969 V(uabal, NEON_UABAL, vn.IsVector() && vn.IsD()) \
2970 V(uabal2, NEON_UABAL2, vn.IsVector() && vn.IsQ()) \
2971 V(sabdl, NEON_SABDL, vn.IsVector() && vn.IsD()) \
2972 V(sabdl2, NEON_SABDL2, vn.IsVector() && vn.IsQ()) \
2973 V(uabdl, NEON_UABDL, vn.IsVector() && vn.IsD()) \
2974 V(uabdl2, NEON_UABDL2, vn.IsVector() && vn.IsQ()) \
2975 V(smlal, NEON_SMLAL, vn.IsVector() && vn.IsD()) \
2976 V(smlal2, NEON_SMLAL2, vn.IsVector() && vn.IsQ()) \
2977 V(umlal, NEON_UMLAL, vn.IsVector() && vn.IsD()) \
2978 V(umlal2, NEON_UMLAL2, vn.IsVector() && vn.IsQ()) \
2979 V(smlsl, NEON_SMLSL, vn.IsVector() && vn.IsD()) \
2980 V(smlsl2, NEON_SMLSL2, vn.IsVector() && vn.IsQ()) \
2981 V(umlsl, NEON_UMLSL, vn.IsVector() && vn.IsD()) \
2982 V(umlsl2, NEON_UMLSL2, vn.IsVector() && vn.IsQ()) \
2983 V(smull, NEON_SMULL, vn.IsVector() && vn.IsD()) \
2984 V(smull2, NEON_SMULL2, vn.IsVector() && vn.IsQ()) \
2985 V(umull, NEON_UMULL, vn.IsVector() && vn.IsD()) \
2986 V(umull2, NEON_UMULL2, vn.IsVector() && vn.IsQ()) \
2987 V(ssubl, NEON_SSUBL, vn.IsVector() && vn.IsD()) \
2988 V(ssubl2, NEON_SSUBL2, vn.IsVector() && vn.IsQ()) \
2989 V(uaddl, NEON_UADDL, vn.IsVector() && vn.IsD()) \
2990 V(uaddl2, NEON_UADDL2, vn.IsVector() && vn.IsQ()) \
2991 V(usubl, NEON_USUBL, vn.IsVector() && vn.IsD()) \
2992 V(usubl2, NEON_USUBL2, vn.IsVector() && vn.IsQ()) \
2993 V(sqdmlal, NEON_SQDMLAL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
2994 V(sqdmlal2, NEON_SQDMLAL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
2995 V(sqdmlsl, NEON_SQDMLSL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
2996 V(sqdmlsl2, NEON_SQDMLSL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
2997 V(sqdmull, NEON_SQDMULL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
2998 V(sqdmull2, NEON_SQDMULL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
3004 const VRegister& vn, \
3008 NEON3DifferentL(vd, vn, vm, OP); \
3027 const VRegister& vn, \
3031 NEON3DifferentHN(vd, vn, vm, OP); \
3037 const VRegister& vn,
3041 NEON3DifferentW(vd, vn, vm, NEON_UADDW);
3046 const VRegister& vn,
3050 NEON3DifferentW(vd, vn, vm, NEON_UADDW2);
3055 const VRegister& vn,
3059 NEON3DifferentW(vd, vn, vm, NEON_SADDW);
3064 const VRegister& vn,
3068 NEON3DifferentW(vd, vn, vm, NEON_SADDW2);
3073 const VRegister& vn,
3077 NEON3DifferentW(vd, vn, vm, NEON_USUBW);
3082 const VRegister& vn,
3086 NEON3DifferentW(vd, vn, vm, NEON_USUBW2);
3091 const VRegister& vn,
3095 NEON3DifferentW(vd, vn, vm, NEON_SSUBW);
3100 const VRegister& vn,
3104 NEON3DifferentW(vd, vn, vm, NEON_SSUBW2);
3301 void Assembler::fmov(const Register& rd, const VRegister& vn) {
3303 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3304 VIXL_ASSERT((rd.GetSizeInBits() == vn.GetSizeInBits()) || vn.Is1H());
3306 switch (vn.GetSizeInBits()) {
3317 Emit(op | Rd(rd) | Rn(vn));
3342 void Assembler::fmov(const VRegister& vd, const VRegister& vn) {
3348 VIXL_ASSERT(vd.IsSameFormat(vn));
3349 Emit(FPType(vd) | FMOV | Rd(vd) | Rn(vn));
3361 void Assembler::fmov(const Register& rd, const VRegister& vn, int index) {
3363 VIXL_ASSERT((index == 1) && vn.Is1D() && rd.IsX());
3365 Emit(FMOV_x_d1 | Rd(rd) | Rn(vn));
3370 const VRegister& vn,
3384 FPDataProcessing3Source(vd, vn, vm, va, op);
3389 const VRegister& vn,
3403 FPDataProcessing3Source(vd, vn, vm, va, op);
3408 const VRegister& vn,
3422 FPDataProcessing3Source(vd, vn, vm, va, op);
3427 const VRegister& vn,
3441 FPDataProcessing3Source(vd, vn, vm, va, op);
3446 const VRegister& vn,
3449 VIXL_ASSERT(AreSameSizeAndType(vd, vn, vm));
3460 Emit(FPType(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
3464 void Assembler::FPCompareMacro(const VRegister& vn,
3472 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3474 Emit(FPType(vn) | op | Rn(vn));
3478 void Assembler::FPCompareMacro(const VRegister& vn,
3481 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3482 VIXL_ASSERT(vn.IsSameSizeAndType(vm));
3484 Emit(FPType(vn) | op | Rm(vm) | Rn(vn));
3488 void Assembler::fcmp(const VRegister& vn, const VRegister& vm) {
3490 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3491 FPCompareMacro(vn, vm, DisableTrap);
3495 void Assembler::fcmpe(const VRegister& vn, const VRegister& vm) {
3497 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3498 FPCompareMacro(vn, vm, EnableTrap);
3502 void Assembler::fcmp(const VRegister& vn, double value) {
3504 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3505 FPCompareMacro(vn, value, DisableTrap);
3509 void Assembler::fcmpe(const VRegister& vn, double value) {
3511 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3512 FPCompareMacro(vn, value, EnableTrap);
3516 void Assembler::FPCCompareMacro(const VRegister& vn,
3521 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3522 VIXL_ASSERT(vn.IsSameSizeAndType(vm));
3524 Emit(FPType(vn) | op | Rm(vm) | Cond(cond) | Rn(vn) | Nzcv(nzcv));
3527 void Assembler::fccmp(const VRegister& vn,
3532 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3533 FPCCompareMacro(vn, vm, nzcv, cond, DisableTrap);
3537 void Assembler::fccmpe(const VRegister& vn,
3542 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3543 FPCCompareMacro(vn, vm, nzcv, cond, EnableTrap);
3548 const VRegister& vn,
3554 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
3555 Emit(FPType(vd) | FCSEL | Rm(vm) | Cond(cond) | Rn(vn) | Rd(vd));
3559 void Assembler::fcvt(const VRegister& vd, const VRegister& vn) {
3564 VIXL_ASSERT(vn.Is1S() || vn.Is1H());
3565 op = vn.Is1S() ? FCVT_ds : FCVT_dh;
3567 VIXL_ASSERT(vn.Is1D() || vn.Is1H());
3568 op = vn.Is1D() ? FCVT_sd : FCVT_sh;
3571 VIXL_ASSERT(vn.Is1D() || vn.Is1S());
3572 op = vn.Is1D() ? FCVT_hd : FCVT_hs;
3574 FPDataProcessing1Source(vd, vn, op);
3578 void Assembler::fcvtl(const VRegister& vd, const VRegister& vn) {
3580 VIXL_ASSERT((vd.Is4S() && vn.Is4H()) || (vd.Is2D() && vn.Is2S()));
3583 Emit(format | NEON_FCVTL | Rn(vn) | Rd(vd));
3587 void Assembler::fcvtl2(const VRegister& vd, const VRegister& vn) {
3589 VIXL_ASSERT((vd.Is4S() && vn.Is8H()) || (vd.Is2D() && vn.Is4S()));
3592 Emit(NEON_Q | format | NEON_FCVTL | Rn(vn) | Rd(vd));
3596 void Assembler::fcvtn(const VRegister& vd, const VRegister& vn) {
3598 VIXL_ASSERT((vn.Is4S() && vd.Is4H()) || (vn.Is2D() && vd.Is2S()));
3600 Instr format = vn.Is2D() ? (1 << NEONSize_offset) : 0;
3601 Emit(format | NEON_FCVTN | Rn(vn) | Rd(vd));
3605 void Assembler::fcvtn2(const VRegister& vd, const VRegister& vn) {
3607 VIXL_ASSERT((vn.Is4S() && vd.Is8H()) || (vn.Is2D() && vd.Is4S()));
3609 Instr format = vn.Is2D() ? (1 << NEONSize_offset) : 0;
3610 Emit(NEON_Q | format | NEON_FCVTN | Rn(vn) | Rd(vd));
3614 void Assembler::fcvtxn(const VRegister& vd, const VRegister& vn) {
3618 VIXL_ASSERT(vd.Is1S() && vn.Is1D());
3619 Emit(format | NEON_FCVTXN_scalar | Rn(vn) | Rd(vd));
3621 VIXL_ASSERT(vd.Is2S() && vn.Is2D());
3622 Emit(format | NEON_FCVTXN | Rn(vn) | Rd(vd));
3627 void Assembler::fcvtxn2(const VRegister& vd, const VRegister& vn) {
3629 VIXL_ASSERT(vd.Is4S() && vn.Is2D());
3631 Emit(NEON_Q | format | NEON_FCVTXN | Rn(vn) | Rd(vd));
3634 void Assembler::fjcvtzs(const Register& rd, const VRegister& vn) {
3636 VIXL_ASSERT(rd.IsW() && vn.Is1D());
3637 Emit(FJCVTZS | Rn(vn) | Rd(rd));
3642 const VRegister& vn,
3644 Emit(SF(rd) | FPType(vn) | op | Rn(vn) | Rd(rd));
3649 const VRegister& vn,
3651 if (vn.IsScalar()) {
3652 VIXL_ASSERT((vd.Is1S() && vn.Is1S()) || (vd.Is1D() && vn.Is1D()));
3655 Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd));
3660 const VRegister& vn,
3662 VIXL_ASSERT(AreSameFormat(vd, vn));
3663 VIXL_ASSERT(vn.IsLaneSizeH());
3664 if (vn.IsScalar()) {
3666 } else if (vn.Is8H()) {
3669 Emit(op | Rn(vn) | Rd(vd));
3684 void Assembler::FN(const Register& rd, const VRegister& vn) { \
3686 if (vn.IsH()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf)); \
3687 NEONFPConvertToInt(rd, vn, SCA_OP); \
3689 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
3693 NEONFP16ConvertToInt(vd, vn, VEC_OP##_H); \
3695 NEONFPConvertToInt(vd, vn, VEC_OP); \
3702 void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) {
3704 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3705 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3708 Emit(SF(rd) | FPType(vn) | FCVTZS | Rn(vn) | Rd(rd));
3710 Emit(SF(rd) | FPType(vn) | FCVTZS_fixed | FPScale(64 - fbits) | Rn(vn) |
3716 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) {
3719 if (vn.IsLaneSizeH()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf));
3723 NEONFP2RegMiscFP16(vd, vn, NEON_FCVTZS_H);
3725 NEONFP2RegMisc(vd, vn, NEON_FCVTZS);
3730 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZS_imm);
3735 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) {
3737 if (vn.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));
3738 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3741 Emit(SF(rd) | FPType(vn) | FCVTZU | Rn(vn) | Rd(rd));
3743 Emit(SF(rd) | FPType(vn) | FCVTZU_fixed | FPScale(64 - fbits) | Rn(vn) |
3749 void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) {
3752 if (vn.IsLaneSizeH()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf));
3756 NEONFP2RegMiscFP16(vd, vn, NEON_FCVTZU_H);
3758 NEONFP2RegMisc(vd, vn, NEON_FCVTZU);
3763 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZU_imm);
3767 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) {
3770 if (vn.IsLaneSizeH()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf));
3774 NEONFP2RegMiscFP16(vd, vn, NEON_UCVTF_H);
3776 NEONFP2RegMisc(vd, vn, NEON_UCVTF);
3781 NEONShiftRightImmediate(vd, vn, fbits, NEON_UCVTF_imm);
3785 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) {
3788 if (vn.IsLaneSizeH()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf));
3792 NEONFP2RegMiscFP16(vd, vn, NEON_SCVTF_H);
3794 NEONFP2RegMisc(vd, vn, NEON_SCVTF);
3799 NEONShiftRightImmediate(vd, vn, fbits, NEON_SCVTF_imm);
3833 const VRegister& vn,
3836 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
3847 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
3852 const VRegister& vn,
3855 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
3856 Emit(FPFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
3861 const VRegister& vn,
3864 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
3867 Emit(op | Rm(vm) | Rn(vn) | Rd(vd));
3888 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
3922 NEONFP2RegMiscFP16(vd, vn, op); \
3924 NEONFP2RegMisc(vd, vn, op); \
3939 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
3950 NEONFP2RegMisc(vd, vn, op); \
3956 const VRegister& vn,
3958 VIXL_ASSERT(AreSameFormat(vd, vn));
3959 Emit(op | Rn(vn) | Rd(vd));
3964 const VRegister& vn,
3966 VIXL_ASSERT(AreSameFormat(vd, vn));
3967 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd));
3972 const VRegister& vn,
3975 VIXL_ASSERT(AreSameFormat(vd, vn));
3987 Emit(format | op | Rn(vn) | Rd(vd));
3991 void Assembler::cmeq(const VRegister& vd, const VRegister& vn, int value) {
3994 NEON2RegMisc(vd, vn, NEON_CMEQ_zero, value);
3998 void Assembler::cmge(const VRegister& vd, const VRegister& vn, int value) {
4001 NEON2RegMisc(vd, vn, NEON_CMGE_zero, value);
4005 void Assembler::cmgt(const VRegister& vd, const VRegister& vn, int value) {
4008 NEON2RegMisc(vd, vn, NEON_CMGT_zero, value);
4012 void Assembler::cmle(const VRegister& vd, const VRegister& vn, int value) {
4015 NEON2RegMisc(vd, vn, NEON_CMLE_zero, value);
4019 void Assembler::cmlt(const VRegister& vd, const VRegister& vn, int value) {
4022 NEON2RegMisc(vd, vn, NEON_CMLT_zero, value);
4026 void Assembler::shll(const VRegister& vd, const VRegister& vn, int shift) {
4029 VIXL_ASSERT((vd.Is8H() && vn.Is8B() && shift == 8) ||
4030 (vd.Is4S() && vn.Is4H() && shift == 16) ||
4031 (vd.Is2D() && vn.Is2S() && shift == 32));
4032 Emit(VFormat(vn) | NEON_SHLL | Rn(vn) | Rd(vd));
4036 void Assembler::shll2(const VRegister& vd, const VRegister& vn, int shift) {
4039 VIXL_ASSERT((vd.Is8H() && vn.Is16B() && shift == 8) ||
4040 (vd.Is4S() && vn.Is8H() && shift == 16) ||
4041 (vd.Is2D() && vn.Is4S() && shift == 32));
4042 Emit(VFormat(vn) | NEON_SHLL | Rn(vn) | Rd(vd));
4047 const VRegister& vn,
4050 VIXL_ASSERT(AreSameFormat(vd, vn));
4062 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd));
4067 const VRegister& vn,
4070 VIXL_ASSERT(AreSameFormat(vd, vn));
4085 Emit(op | Rn(vn) | Rd(vd));
4089 void Assembler::fcmeq(const VRegister& vd, const VRegister& vn, double value) {
4093 NEONFP2RegMiscFP16(vd, vn, NEON_FCMEQ_H_zero, value);
4095 NEONFP2RegMisc(vd, vn, NEON_FCMEQ_zero, value);
4100 void Assembler::fcmge(const VRegister& vd, const VRegister& vn, double value) {
4104 NEONFP2RegMiscFP16(vd, vn, NEON_FCMGE_H_zero, value);
4106 NEONFP2RegMisc(vd, vn, NEON_FCMGE_zero, value);
4111 void Assembler::fcmgt(const VRegister& vd, const VRegister& vn, double value) {
4115 NEONFP2RegMiscFP16(vd, vn, NEON_FCMGT_H_zero, value);
4117 NEONFP2RegMisc(vd, vn, NEON_FCMGT_zero, value);
4122 void Assembler::fcmle(const VRegister& vd, const VRegister& vn, double value) {
4126 NEONFP2RegMiscFP16(vd, vn, NEON_FCMLE_H_zero, value);
4128 NEONFP2RegMisc(vd, vn, NEON_FCMLE_zero, value);
4133 void Assembler::fcmlt(const VRegister& vd, const VRegister& vn, double value) {
4137 NEONFP2RegMiscFP16(vd, vn, NEON_FCMLT_H_zero, value);
4139 NEONFP2RegMisc(vd, vn, NEON_FCMLT_zero, value);
4144 void Assembler::frecpx(const VRegister& vd, const VRegister& vn) {
4147 VIXL_ASSERT(AreSameFormat(vd, vn));
4156 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd));
4219 const VRegister& vn, \
4223 NEON3Same(vd, vn, vm, OP); \
4261 const VRegister& vn, \
4294 NEON3SameFP16(vd, vn, vm, op); \
4296 NEONFP3Same(vd, vn, vm, op); \
4313 const VRegister& vn, \
4319 VIXL_ASSERT((vd.Is2S() && vn.Is2H() && vm.Is2H()) || \
4320 (vd.Is4S() && vn.Is4H() && vm.Is4H())); \
4321 Emit(FPFormat(vd) | VEC_OP | Rm(vm) | Rn(vn) | Rd(vd)); \
4327 void Assembler::addp(const VRegister& vd, const VRegister& vn) {
4329 VIXL_ASSERT((vd.Is1D() && vn.Is2D()));
4330 Emit(SFormat(vd) | NEON_ADDP_scalar | Rn(vn) | Rd(vd));
4335 const VRegister& vn,
4338 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
4349 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
4354 const VRegister& vn,
4357 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
4368 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
4373 const VRegister& vn,
4376 VIXL_ASSERT(AreSameFormat(vn, vm));
4377 VIXL_ASSERT((vd.Is2S() && vn.Is8B()) || (vd.Is4S() && vn.Is16B()));
4379 Emit(VFormat(vd) | NEON_SDOT | Rm(vm) | Rn(vn) | Rd(vd));
4384 const VRegister& vn,
4387 VIXL_ASSERT(AreSameFormat(vn, vm));
4388 VIXL_ASSERT((vd.Is2S() && vn.Is8B()) || (vd.Is4S() && vn.Is16B()));
4390 Emit(VFormat(vd) | NEON_UDOT | Rm(vm) | Rn(vn) | Rd(vd));
4394 const VRegister& vn,
4397 VIXL_ASSERT(AreSameFormat(vn, vm));
4398 VIXL_ASSERT((vd.Is2S() && vn.Is8B()) || (vd.Is4S() && vn.Is16B()));
4400 Emit(VFormat(vd) | 0x0e809c00 | Rm(vm) | Rn(vn) | Rd(vd));
4403 void Assembler::faddp(const VRegister& vd, const VRegister& vn) {
4405 VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()) ||
4406 (vd.Is1H() && vn.Is2H()));
4409 Emit(NEON_FADDP_h_scalar | Rn(vn) | Rd(vd));
4411 Emit(FPFormat(vd) | NEON_FADDP_scalar | Rn(vn) | Rd(vd));
4416 void Assembler::fmaxp(const VRegister& vd, const VRegister& vn) {
4418 VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()) ||
4419 (vd.Is1H() && vn.Is2H()));
4422 Emit(NEON_FMAXP_h_scalar | Rn(vn) | Rd(vd));
4424 Emit(FPFormat(vd) | NEON_FMAXP_scalar | Rn(vn) | Rd(vd));
4429 void Assembler::fminp(const VRegister& vd, const VRegister& vn) {
4431 VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()) ||
4432 (vd.Is1H() && vn.Is2H()));
4435 Emit(NEON_FMINP_h_scalar | Rn(vn) | Rd(vd));
4437 Emit(FPFormat(vd) | NEON_FMINP_scalar | Rn(vn) | Rd(vd));
4442 void Assembler::fmaxnmp(const VRegister& vd, const VRegister& vn) {
4444 VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()) ||
4445 (vd.Is1H() && vn.Is2H()));
4448 Emit(NEON_FMAXNMP_h_scalar | Rn(vn) | Rd(vd));
4450 Emit(FPFormat(vd) | NEON_FMAXNMP_scalar | Rn(vn) | Rd(vd));
4455 void Assembler::fminnmp(const VRegister& vd, const VRegister& vn) {
4457 VIXL_ASSERT((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()) ||
4458 (vd.Is1H() && vn.Is2H()));
4461 Emit(NEON_FMINNMP_h_scalar | Rn(vn) | Rd(vd));
4463 Emit(FPFormat(vd) | NEON_FMINNMP_scalar | Rn(vn) | Rd(vd));
4470 const VRegister& vn,
4475 VIXL_ASSERT(vd.IsVector() && AreSameFormat(vd, vn));
4481 ImmNEONHLM(vm_index, index_num_bits) | ImmRotFcmlaSca(rot) | Rn(vn) |
4487 const VRegister& vn,
4491 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
4494 Emit(VFormat(vd) | Rm(vm) | NEON_FCMLA | ImmRotFcmlaVec(rot) | Rn(vn) |
4501 const VRegister& vn,
4505 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
4508 Emit(VFormat(vd) | Rm(vm) | NEON_FCADD | ImmRotFcadd(rot) | Rn(vn) | Rd(vd));
4518 void Assembler::mov(const VRegister& vd, const VRegister& vn) {
4520 VIXL_ASSERT(AreSameFormat(vd, vn));
4522 orr(vd.V8B(), vn.V8B(), vn.V8B());
4525 orr(vd.V16B(), vn.V16B(), vn.V16B());
4571 void Assembler::mvn(const VRegister& vd, const VRegister& vn) {
4573 VIXL_ASSERT(AreSameFormat(vd, vn));
4575 not_(vd.V8B(), vn.V8B());
4578 not_(vd.V16B(), vn.V16B());
4598 const VRegister& vn,
4603 VIXL_ASSERT(AreSameFormat(vd, vn));
4632 Emit(op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | Rd(vd));
4637 const VRegister& vn,
4641 VIXL_ASSERT(AreSameFormat(vd, vn));
4652 format = SFormat(vn);
4654 format = VFormat(vn);
4656 Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
4662 const VRegister& vn,
4666 VIXL_ASSERT((vd.Is4S() && vn.Is4H() && vm.Is1H()) ||
4667 (vd.Is4S() && vn.Is8H() && vm.Is1H()) ||
4668 (vd.Is1S() && vn.Is1H() && vm.Is1H()) ||
4669 (vd.Is2D() && vn.Is2S() && vm.Is1S()) ||
4670 (vd.Is2D() && vn.Is4S() && vm.Is1S()) ||
4671 (vd.Is1D() && vn.Is1S() && vm.Is1S()));
4680 format = SFormat(vn);
4682 format = VFormat(vn);
4684 Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
4690 const VRegister& vn,
4694 VIXL_ASSERT((vd.Is2S() && vn.Is8B() && vm.Is1S4B()) ||
4695 (vd.Is4S() && vn.Is16B() && vm.Is1S4B()));
4699 ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | Rd(vd));
4704 const VRegister& vn,
4708 VIXL_ASSERT((vd.Is2S() && vn.Is8B() && vm.Is1S4B()) ||
4709 (vd.Is4S() && vn.Is16B() && vm.Is1S4B()));
4713 ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) | Rd(vd));
4717 const VRegister& vn,
4721 VIXL_ASSERT((vd.Is2S() && vn.Is8B() && vm.Is1S4B()) ||
4722 (vd.Is4S() && vn.Is16B() && vm.Is1S4B()));
4725 Emit(q | 0x0f00f000 | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
4731 const VRegister& vn,
4735 VIXL_ASSERT((vd.Is2S() && vn.Is8B() && vm.Is1S4B()) ||
4736 (vd.Is4S() && vn.Is16B() && vm.Is1S4B()));
4739 Emit(q | 0x0f80f000 | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
4745 V(mul, NEON_MUL_byelement, vn.IsVector()) \
4746 V(mla, NEON_MLA_byelement, vn.IsVector()) \
4747 V(mls, NEON_MLS_byelement, vn.IsVector()) \
4754 const VRegister& vn, \
4759 NEONByElement(vd, vn, vm, vm_index, OP); \
4773 const VRegister& vn, \
4777 NEONByElement(vd, vn, vm, vm_index, OP); \
4793 const VRegister& vn, \
4798 NEONFPByElement(vd, vn, vm, vm_index, OP, OP_H); \
4806 V(sqdmull, NEON_SQDMULL_byelement, vn.IsScalar() || vn.IsD()) \
4807 V(sqdmull2, NEON_SQDMULL_byelement, vn.IsVector() && vn.IsQ()) \
4808 V(sqdmlal, NEON_SQDMLAL_byelement, vn.IsScalar() || vn.IsD()) \
4809 V(sqdmlal2, NEON_SQDMLAL_byelement, vn.IsVector() && vn.IsQ()) \
4810 V(sqdmlsl, NEON_SQDMLSL_byelement, vn.IsScalar() || vn.IsD()) \
4811 V(sqdmlsl2, NEON_SQDMLSL_byelement, vn.IsVector() && vn.IsQ()) \
4812 V(smull, NEON_SMULL_byelement, vn.IsVector() && vn.IsD()) \
4813 V(smull2, NEON_SMULL_byelement, vn.IsVector() && vn.IsQ()) \
4814 V(umull, NEON_UMULL_byelement, vn.IsVector() && vn.IsD()) \
4815 V(umull2, NEON_UMULL_byelement, vn.IsVector() && vn.IsQ()) \
4816 V(smlal, NEON_SMLAL_byelement, vn.IsVector() && vn.IsD()) \
4817 V(smlal2, NEON_SMLAL_byelement, vn.IsVector() && vn.IsQ()) \
4818 V(umlal, NEON_UMLAL_byelement, vn.IsVector() && vn.IsD()) \
4819 V(umlal2, NEON_UMLAL_byelement, vn.IsVector() && vn.IsQ()) \
4820 V(smlsl, NEON_SMLSL_byelement, vn.IsVector() && vn.IsD()) \
4821 V(smlsl2, NEON_SMLSL_byelement, vn.IsVector() && vn.IsQ()) \
4822 V(umlsl, NEON_UMLSL_byelement, vn.IsVector() && vn.IsD()) \
4823 V(umlsl2, NEON_UMLSL_byelement, vn.IsVector() && vn.IsQ())
4829 const VRegister& vn, \
4834 NEONByElementL(vd, vn, vm, vm_index, OP); \
4851 const VRegister& vn, \
4858 VIXL_ASSERT((vd.Is2S() && vn.Is2H()) || (vd.Is4S() && vn.Is4H())); \
4863 Emit(FPFormat(vd) | OP | Rd(vd) | Rn(vn) | Rm(vm) | \
4869 void Assembler::suqadd(const VRegister& vd, const VRegister& vn) {
4871 NEON2RegMisc(vd, vn, NEON_SUQADD);
4875 void Assembler::usqadd(const VRegister& vd, const VRegister& vn) {
4877 NEON2RegMisc(vd, vn, NEON_USQADD);
4881 void Assembler::abs(const VRegister& vd, const VRegister& vn) {
4884 NEON2RegMisc(vd, vn, NEON_ABS);
4888 void Assembler::sqabs(const VRegister& vd, const VRegister& vn) {
4890 NEON2RegMisc(vd, vn, NEON_SQABS);
4894 void Assembler::neg(const VRegister& vd, const VRegister& vn) {
4897 NEON2RegMisc(vd, vn, NEON_NEG);
4901 void Assembler::sqneg(const VRegister& vd, const VRegister& vn) {
4903 NEON2RegMisc(vd, vn, NEON_SQNEG);
4908 const VRegister& vn,
4913 VIXL_ASSERT((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) ||
4914 (vd.Is1S() && vn.Is1D()));
4918 VIXL_ASSERT((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
4919 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
4920 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
4923 Emit(format | op | Rn(vn) | Rd(vd));
4927 void Assembler::xtn(const VRegister& vd, const VRegister& vn) {
4930 NEONXtn(vd, vn, NEON_XTN);
4934 void Assembler::xtn2(const VRegister& vd, const VRegister& vn) {
4937 NEONXtn(vd, vn, NEON_XTN);
4941 void Assembler::sqxtn(const VRegister& vd, const VRegister& vn) {
4944 NEONXtn(vd, vn, NEON_SQXTN);
4948 void Assembler::sqxtn2(const VRegister& vd, const VRegister& vn) {
4951 NEONXtn(vd, vn, NEON_SQXTN);
4955 void Assembler::sqxtun(const VRegister& vd, const VRegister& vn) {
4958 NEONXtn(vd, vn, NEON_SQXTUN);
4962 void Assembler::sqxtun2(const VRegister& vd, const VRegister& vn) {
4965 NEONXtn(vd, vn, NEON_SQXTUN);
4969 void Assembler::uqxtn(const VRegister& vd, const VRegister& vn) {
4972 NEONXtn(vd, vn, NEON_UQXTN);
4976 void Assembler::uqxtn2(const VRegister& vd, const VRegister& vn) {
4979 NEONXtn(vd, vn, NEON_UQXTN);
4984 void Assembler::not_(const VRegister& vd, const VRegister& vn) {
4986 VIXL_ASSERT(AreSameFormat(vd, vn));
4988 Emit(VFormat(vd) | NEON_RBIT_NOT | Rn(vn) | Rd(vd));
4992 void Assembler::rbit(const VRegister& vd, const VRegister& vn) {
4994 VIXL_ASSERT(AreSameFormat(vd, vn));
4996 Emit(VFormat(vn) | (1 << NEONSize_offset) | NEON_RBIT_NOT | Rn(vn) | Rd(vd));
5001 const VRegister& vn,
5005 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
5008 Emit(VFormat(vd) | NEON_EXT | Rm(vm) | ImmNEONExt(index) | Rn(vn) | Rd(vd));
5012 void Assembler::dup(const VRegister& vd, const VRegister& vn, int vn_index) {
5016 // We support vn arguments of the form vn.VxT() or vn.T(), where x is the
5018 int lane_size = vn.GetLaneSizeInBytes();
5044 Emit(q | scalar | NEON_DUP_ELEMENT | ImmNEON5(format, vn_index) | Rn(vn) |
5049 void Assembler::mov(const VRegister& vd, const VRegister& vn, int vn_index) {
5052 dup(vd, vn, vn_index);
5067 const VRegister& vn,
5070 VIXL_ASSERT(AreSameFormat(vd, vn));
5098 ImmNEON4(format, vn_index) | Rn(vn) | Rd(vd));
5104 const VRegister& vn,
5107 ins(vd, vd_index, vn, vn_index);
5150 void Assembler::umov(const Register& rd, const VRegister& vn, int vn_index) {
5152 // We support vn arguments of the form vn.VxT() or vn.T(), where x is the
5154 int lane_size = vn.GetLaneSizeInBytes();
5181 Emit(q | NEON_UMOV | ImmNEON5(format, vn_index) | Rn(vn) | Rd(rd));
5185 void Assembler::mov(const Register& rd, const VRegister& vn, int vn_index) {
5187 VIXL_ASSERT(vn.GetSizeInBytes() >= 4);
5188 umov(rd, vn, vn_index);
5192 void Assembler::smov(const Register& rd, const VRegister& vn, int vn_index) {
5194 // We support vn arguments of the form vn.VxT() or vn.T(), where x is the
5196 int lane_size = vn.GetLaneSizeInBytes();
5217 Emit(q | NEON_SMOV | ImmNEON5(format, vn_index) | Rn(vn) | Rd(rd));
5221 void Assembler::cls(const VRegister& vd, const VRegister& vn) {
5223 VIXL_ASSERT(AreSameFormat(vd, vn));
5225 Emit(VFormat(vn) | NEON_CLS | Rn(vn) | Rd(vd));
5229 void Assembler::clz(const VRegister& vd, const VRegister& vn) {
5231 VIXL_ASSERT(AreSameFormat(vd, vn));
5233 Emit(VFormat(vn) | NEON_CLZ | Rn(vn) | Rd(vd));
5237 void Assembler::cnt(const VRegister& vd, const VRegister& vn) {
5239 VIXL_ASSERT(AreSameFormat(vd, vn));
5241 Emit(VFormat(vn) | NEON_CNT | Rn(vn) | Rd(vd));
5245 void Assembler::rev16(const VRegister& vd, const VRegister& vn) {
5247 VIXL_ASSERT(AreSameFormat(vd, vn));
5249 Emit(VFormat(vn) | NEON_REV16 | Rn(vn) | Rd(vd));
5253 void Assembler::rev32(const VRegister& vd, const VRegister& vn) {
5255 VIXL_ASSERT(AreSameFormat(vd, vn));
5257 Emit(VFormat(vn) | NEON_REV32 | Rn(vn) | Rd(vd));
5261 void Assembler::rev64(const VRegister& vd, const VRegister& vn) {
5263 VIXL_ASSERT(AreSameFormat(vd, vn));
5265 Emit(VFormat(vn) | NEON_REV64 | Rn(vn) | Rd(vd));
5269 void Assembler::ursqrte(const VRegister& vd, const VRegister& vn) {
5271 VIXL_ASSERT(AreSameFormat(vd, vn));
5273 Emit(VFormat(vn) | NEON_URSQRTE | Rn(vn) | Rd(vd));
5277 void Assembler::urecpe(const VRegister& vd, const VRegister& vn) {
5279 VIXL_ASSERT(AreSameFormat(vd, vn));
5281 Emit(VFormat(vn) | NEON_URECPE | Rn(vn) | Rd(vd));
5286 const VRegister& vn,
5292 VIXL_ASSERT((vn.Is8B() && vd.Is4H()) || (vn.Is4H() && vd.Is2S()) ||
5293 (vn.Is2S() && vd.Is1D()) || (vn.Is16B() && vd.Is8H()) ||
5294 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
5295 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd));
5299 void Assembler::saddlp(const VRegister& vd, const VRegister& vn) {
5301 NEONAddlp(vd, vn, NEON_SADDLP);
5305 void Assembler::uaddlp(const VRegister& vd, const VRegister& vn) {
5307 NEONAddlp(vd, vn, NEON_UADDLP);
5311 void Assembler::sadalp(const VRegister& vd, const VRegister& vn) {
5313 NEONAddlp(vd, vn, NEON_SADALP);
5317 void Assembler::uadalp(const VRegister& vd, const VRegister& vn) {
5319 NEONAddlp(vd, vn, NEON_UADALP);
5324 const VRegister& vn,
5326 VIXL_ASSERT((vn.Is8B() && vd.Is1H()) || (vn.Is16B() && vd.Is1H()) ||
5327 (vn.Is4H() && vd.Is1S()) || (vn.Is8H() && vd.Is1S()) ||
5328 (vn.Is4S() && vd.Is1D()));
5329 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd));
5333 void Assembler::saddlv(const VRegister& vd, const VRegister& vn) {
5335 NEONAcrossLanesL(vd, vn, NEON_SADDLV);
5339 void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) {
5341 NEONAcrossLanesL(vd, vn, NEON_UADDLV);
5346 const VRegister& vn,
5349 VIXL_ASSERT((vn.Is8B() && vd.Is1B()) || (vn.Is16B() && vd.Is1B()) ||
5350 (vn.Is4H() && vd.Is1H()) || (vn.Is8H() && vd.Is1H()) ||
5351 (vn.Is4S() && vd.Is1S()));
5356 if (vn.Is8H()) {
5359 Emit(vop | Rn(vn) | Rd(vd));
5361 Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd));
5364 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd));
5378 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
5380 NEONAcrossLanes(vd, vn, OP, 0); \
5395 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
5399 NEONAcrossLanes(vd, vn, OP, OP_H); \
5406 const VRegister& vn,
5409 VIXL_ASSERT(AreSameFormat(vd, vn, vm));
5411 Emit(VFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
5416 const VRegister& vn,
5419 NEONPerm(vd, vn, vm, NEON_TRN1);
5424 const VRegister& vn,
5427 NEONPerm(vd, vn, vm, NEON_TRN2);
5432 const VRegister& vn,
5435 NEONPerm(vd, vn, vm, NEON_UZP1);
5440 const VRegister& vn,
5443 NEONPerm(vd, vn, vm, NEON_UZP2);
5448 const VRegister& vn,
5451 NEONPerm(vd, vn, vm, NEON_ZIP1);
5456 const VRegister& vn,
5459 NEONPerm(vd, vn, vm, NEON_ZIP2);
5464 const VRegister& vn,
5467 VIXL_ASSERT(AreSameFormat(vd, vn));
5469 if (vn.IsScalar()) {
5476 Emit(q | op | scalar | immh_immb | Rn(vn) | Rd(vd));
5481 const VRegister& vn,
5484 int lane_size_in_bits = vn.GetLaneSizeInBits();
5486 NEONShiftImmediate(vd, vn, op, (lane_size_in_bits + shift) << 16);
5491 const VRegister& vn,
5494 int lane_size_in_bits = vn.GetLaneSizeInBits();
5496 NEONShiftImmediate(vd, vn, op, ((2 * lane_size_in_bits) - shift) << 16);
5501 const VRegister& vn,
5504 int lane_size_in_bits = vn.GetLaneSizeInBits();
5508 VIXL_ASSERT((vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) ||
5509 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) ||
5510 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
5512 q = vn.IsD() ? 0 : NEON_Q;
5513 Emit(q | op | immh_immb | Rn(vn) | Rd(vd));
5518 const VRegister& vn,
5526 if (vn.IsScalar()) {
5527 VIXL_ASSERT((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) ||
5528 (vd.Is1S() && vn.Is1D()));
5532 VIXL_ASSERT((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
5533 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
5534 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
5538 Emit(q | op | scalar | immh_immb | Rn(vn) | Rd(vd));
5542 void Assembler::shl(const VRegister& vd, const VRegister& vn, int shift) {
5545 NEONShiftLeftImmediate(vd, vn, shift, NEON_SHL);
5549 void Assembler::sli(const VRegister& vd, const VRegister& vn, int shift) {
5552 NEONShiftLeftImmediate(vd, vn, shift, NEON_SLI);
5556 void Assembler::sqshl(const VRegister& vd, const VRegister& vn, int shift) {
5558 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHL_imm);
5562 void Assembler::sqshlu(const VRegister& vd, const VRegister& vn, int shift) {
5564 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHLU);
5568 void Assembler::uqshl(const VRegister& vd, const VRegister& vn, int shift) {
5570 NEONShiftLeftImmediate(vd, vn, shift, NEON_UQSHL_imm);
5574 void Assembler::sshll(const VRegister& vd, const VRegister& vn, int shift) {
5576 VIXL_ASSERT(vn.IsD());
5577 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL);
5581 void Assembler::sshll2(const VRegister& vd, const VRegister& vn, int shift) {
5583 VIXL_ASSERT(vn.IsQ());
5584 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL);
5588 void Assembler::sxtl(const VRegister& vd, const VRegister& vn) {
5590 sshll(vd, vn, 0);
5594 void Assembler::sxtl2(const VRegister& vd, const VRegister& vn) {
5596 sshll2(vd, vn, 0);
5600 void Assembler::ushll(const VRegister& vd, const VRegister& vn, int shift) {
5602 VIXL_ASSERT(vn.IsD());
5603 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL);
5607 void Assembler::ushll2(const VRegister& vd, const VRegister& vn, int shift) {
5609 VIXL_ASSERT(vn.IsQ());
5610 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL);
5614 void Assembler::uxtl(const VRegister& vd, const VRegister& vn) {
5616 ushll(vd, vn, 0);
5620 void Assembler::uxtl2(const VRegister& vd, const VRegister& vn) {
5622 ushll2(vd, vn, 0);
5626 void Assembler::sri(const VRegister& vd, const VRegister& vn, int shift) {
5629 NEONShiftRightImmediate(vd, vn, shift, NEON_SRI);
5633 void Assembler::sshr(const VRegister& vd, const VRegister& vn, int shift) {
5636 NEONShiftRightImmediate(vd, vn, shift, NEON_SSHR);
5640 void Assembler::ushr(const VRegister& vd, const VRegister& vn, int shift) {
5643 NEONShiftRightImmediate(vd, vn, shift, NEON_USHR);
5647 void Assembler::srshr(const VRegister& vd, const VRegister& vn, int shift) {
5650 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSHR);
5654 void Assembler::urshr(const VRegister& vd, const VRegister& vn, int shift) {
5657 NEONShiftRightImmediate(vd, vn, shift, NEON_URSHR);
5661 void Assembler::ssra(const VRegister& vd, const VRegister& vn, int shift) {
5664 NEONShiftRightImmediate(vd, vn, shift, NEON_SSRA);
5668 void Assembler::usra(const VRegister& vd, const VRegister& vn, int shift) {
5671 NEONShiftRightImmediate(vd, vn, shift, NEON_USRA);
5675 void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) {
5678 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSRA);
5682 void Assembler::ursra(const VRegister& vd, const VRegister& vn, int shift) {
5685 NEONShiftRightImmediate(vd, vn, shift, NEON_URSRA);
5689 void Assembler::shrn(const VRegister& vd, const VRegister& vn, int shift) {
5691 VIXL_ASSERT(vn.IsVector() && vd.IsD());
5692 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN);
5696 void Assembler::shrn2(const VRegister& vd, const VRegister& vn, int shift) {
5698 VIXL_ASSERT(vn.IsVector() && vd.IsQ());
5699 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN);
5703 void Assembler::rshrn(const VRegister& vd, const VRegister& vn, int shift) {
5705 VIXL_ASSERT(vn.IsVector() && vd.IsD());
5706 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN);
5710 void Assembler::rshrn2(const VRegister& vd, const VRegister& vn, int shift) {
5712 VIXL_ASSERT(vn.IsVector() && vd.IsQ());
5713 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN);
5717 void Assembler::sqshrn(const VRegister& vd, const VRegister& vn, int shift) {
5719 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
5720 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN);
5724 void Assembler::sqshrn2(const VRegister& vd, const VRegister& vn, int shift) {
5726 VIXL_ASSERT(vn.IsVector() && vd.IsQ());
5727 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN);
5731 void Assembler::sqrshrn(const VRegister& vd, const VRegister& vn, int shift) {
5733 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
5734 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN);
5738 void Assembler::sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) {
5740 VIXL_ASSERT(vn.IsVector() && vd.IsQ());
5741 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN);
5745 void Assembler::sqshrun(const VRegister& vd, const VRegister& vn, int shift) {
5747 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
5748 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN);
5752 void Assembler::sqshrun2(const VRegister& vd, const VRegister& vn, int shift) {
5754 VIXL_ASSERT(vn.IsVector() && vd.IsQ());
5755 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN);
5759 void Assembler::sqrshrun(const VRegister& vd, const VRegister& vn, int shift) {
5761 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
5762 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN);
5766 void Assembler::sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) {
5768 VIXL_ASSERT(vn.IsVector() && vd.IsQ());
5769 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN);
5773 void Assembler::uqshrn(const VRegister& vd, const VRegister& vn, int shift) {
5775 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
5776 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN);
5780 void Assembler::uqshrn2(const VRegister& vd, const VRegister& vn, int shift) {
5782 VIXL_ASSERT(vn.IsVector() && vd.IsQ());
5783 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN);
5787 void Assembler::uqrshrn(const VRegister& vd, const VRegister& vn, int shift) {
5789 VIXL_ASSERT(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
5790 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN);
5794 void Assembler::uqrshrn2(const VRegister& vd, const VRegister& vn, int shift) {
5796 VIXL_ASSERT(vn.IsVector() && vd.IsQ());
5797 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN);
5800 void Assembler::smmla(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
5804 VIXL_ASSERT(vn.IsLaneSizeB() && vm.IsLaneSizeB());
5806 Emit(0x4e80a400 | Rd(vd) | Rn(vn) | Rm(vm));
5809 void Assembler::usmmla(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
5813 VIXL_ASSERT(vn.IsLaneSizeB() && vm.IsLaneSizeB());
5815 Emit(0x4e80ac00 | Rd(vd) | Rn(vn) | Rm(vm));
5818 void Assembler::ummla(const VRegister& vd, const VRegister& vn, const VRegister& vm) {
5822 VIXL_ASSERT(vn.IsLaneSizeB() && vm.IsLaneSizeB());
5824 Emit(0x6e80a400 | Rd(vd) | Rn(vn) | Rm(vm));
6123 const VRegister& vn,
6126 Emit(FPType(vn) | op | Rn(vn) | Rd(vd));
6131 const VRegister& vn,
6136 VIXL_ASSERT(AreSameSizeAndType(vd, vn, vm, va));
6137 Emit(FPType(vd) | op | Rm(vm) | Rn(vn) | Rd(vd) | Ra(va));