Lines Matching defs:operand
472 const Operand& operand) {
473 AddSub(rd, rn, operand, LeaveFlags, ADD);
479 const Operand& operand) {
480 AddSub(rd, rn, operand, SetFlags, ADD);
484 void Assembler::cmn(const Register& rn, const Operand& operand) {
486 adds(zr, rn, operand);
492 const Operand& operand) {
493 AddSub(rd, rn, operand, LeaveFlags, SUB);
499 const Operand& operand) {
500 AddSub(rd, rn, operand, SetFlags, SUB);
504 void Assembler::cmp(const Register& rn, const Operand& operand) {
506 subs(zr, rn, operand);
510 void Assembler::neg(const Register& rd, const Operand& operand) {
512 sub(rd, zr, operand);
516 void Assembler::negs(const Register& rd, const Operand& operand) {
518 subs(rd, zr, operand);
524 const Operand& operand) {
525 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC);
531 const Operand& operand) {
532 AddSubWithCarry(rd, rn, operand, SetFlags, ADC);
538 const Operand& operand) {
539 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC);
545 const Operand& operand) {
546 AddSubWithCarry(rd, rn, operand, SetFlags, SBC);
569 void Assembler::ngc(const Register& rd, const Operand& operand) {
571 sbc(rd, zr, operand);
575 void Assembler::ngcs(const Register& rd, const Operand& operand) {
577 sbcs(rd, zr, operand);
584 const Operand& operand) {
585 Logical(rd, rn, operand, AND);
591 const Operand& operand) {
592 Logical(rd, rn, operand, ANDS);
596 void Assembler::tst(const Register& rn, const Operand& operand) {
597 ands(AppropriateZeroRegFor(rn), rn, operand);
603 const Operand& operand) {
604 Logical(rd, rn, operand, BIC);
610 const Operand& operand) {
611 Logical(rd, rn, operand, BICS);
617 const Operand& operand) {
618 Logical(rd, rn, operand, ORR);
624 const Operand& operand) {
625 Logical(rd, rn, operand, ORN);
631 const Operand& operand) {
632 Logical(rd, rn, operand, EOR);
638 const Operand& operand) {
639 Logical(rd, rn, operand, EON);
801 const Operand& operand,
804 ConditionalCompare(rn, operand, nzcv, cond, CCMN);
809 const Operand& operand,
812 ConditionalCompare(rn, operand, nzcv, cond, CCMP);
3110 // second operand of zero. Otherwise, orr with first operand zr is
3191 void Assembler::mvn(const Register& rd, const Operand& operand) {
3192 orn(rd, AppropriateZeroRegFor(rd), operand);
5976 const Operand& operand,
5980 if (operand.IsImmediate()) {
5981 int64_t immediate = operand.GetImmediate();
5986 } else if (operand.IsShiftedRegister()) {
5987 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() == rd.GetSizeInBits());
5988 VIXL_ASSERT(operand.GetShift() != ROR);
5995 // or their 64-bit register equivalents, convert the operand from shifted to
6001 operand.ToExtendedRegister(),
6005 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
6008 VIXL_ASSERT(operand.IsExtendedRegister());
6009 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
6016 const Operand& operand,
6020 VIXL_ASSERT(rd.GetSizeInBits() == operand.GetRegister().GetSizeInBits());
6021 VIXL_ASSERT(operand.IsShiftedRegister() && (operand.GetShiftAmount() == 0));
6022 Emit(SF(rd) | op | Flags(S) | Rm(operand.GetRegister()) | Rn(rn) | Rd(rd));
6047 const Operand operand,
6050 if (operand.IsImmediate()) {
6051 int64_t immediate = operand.GetImmediate();
6073 VIXL_ASSERT(operand.IsShiftedRegister());
6074 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() == rd.GetSizeInBits());
6076 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
6096 const Operand& operand,
6101 if (operand.IsImmediate()) {
6102 int64_t immediate = operand.GetImmediate();
6107 VIXL_ASSERT(operand.IsShiftedRegister() && (operand.GetShiftAmount() == 0));
6108 ccmpop = ConditionalCompareRegisterFixed | op | Rm(operand.GetRegister());
6258 const Operand& operand,
6261 VIXL_ASSERT(operand.IsShiftedRegister());
6263 (rn.Is32Bits() && IsUint5(operand.GetShiftAmount())));
6264 Emit(SF(rd) | op | Flags(S) | ShiftDP(operand.GetShift()) |
6265 ImmDPShift(operand.GetShiftAmount()) | Rm(operand.GetRegister()) |
6272 const Operand& operand,
6276 Emit(SF(rd) | op | Flags(S) | Rm(operand.GetRegister()) |
6277 ExtendMode(operand.GetExtend()) |
6278 ImmExtendShift(operand.GetShiftAmount()) | dest_reg | RnSP(rn));