Lines Matching refs:LSL
57 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {}
59 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {}
66 : imm_(0), rm_(rm), shift_(LSL), amount_(0), rs_(NoReg) {
81 // <shift> is one of {LSL, LSR, ASR, ROR}, and
89 case LSL:
109 // <shift> is one of {LSL, LSR, ASR, ROR}, and
642 shift_(LSL),
659 shift_(LSL),
669 shift_(LSL),
686 shift_(LSL),
700 shift_(LSL),
747 // <shift> is one of {LSL, LSR, ASR, ROR}, applied to value from rm
769 // <shift> is one of {LSL, LSR, ASR, ROR}, applied to value from rm
838 // Disallow any zero shift other than RRX #0 and LSL #0 .
847 case LSL: