Lines Matching defs:shift
47 // <Rm>, <shift> <#amount> - immediate shifted register
48 // <Rm>, <shift> <Rs> - register shifted register
70 // rm, <shift>
72 // <shift> is RRX
73 Operand(Register rm, Shift shift)
74 : imm_(0), rm_(rm), shift_(shift), amount_(0), rs_(NoReg) {
79 // rm, <shift> #<amount>
81 // <shift> is one of {LSL, LSR, ASR, ROR}, and
83 Operand(Register rm, Shift shift, uint32_t amount)
84 : imm_(0), rm_(rm), shift_(shift), amount_(amount), rs_(NoReg) {
107 // rm, <shift> rs
109 // <shift> is one of {LSL, LSR, ASR, ROR}, and
111 Operand(Register rm, Shift shift, Register rs)
112 : imm_(0), rm_(rm), shift_(shift), amount_(0), rs_(rs) {
615 // - a shifted index register <Rm>, <shift> #<amount>
706 // rn, {+/-}rm, <shift>
710 // <shift> is RRX, applied to value from rm
714 Shift shift,
720 shift_(shift),
727 // rn, rm, <shift>
730 // <shift> is RRX, applied to value from rm
731 MemOperand(Register rn, Register rm, Shift shift, AddrMode addrmode = Offset)
736 shift_(shift),
743 // rn, {+/-}rm, <shift> #<amount>
747 // <shift> is one of {LSL, LSR, ASR, ROR}, applied to value from rm
752 Shift shift,
759 shift_(shift),
766 // rn, rm, <shift> #<amount>
769 // <shift> is one of {LSL, LSR, ASR, ROR}, applied to value from rm
773 Shift shift,
780 shift_(shift),
838 // Disallow any zero shift other than RRX #0 and LSL #0 .
842 "A shift by 0 is only accepted in "
844 "no shift.\n");