Lines Matching defs:rm_
57 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {}
59 : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {}
66 : imm_(0), rm_(rm), shift_(LSL), amount_(0), rs_(NoReg) {
67 VIXL_ASSERT(rm_.IsValid());
74 : imm_(0), rm_(rm), shift_(shift), amount_(0), rs_(NoReg) {
75 VIXL_ASSERT(rm_.IsValid());
84 : imm_(0), rm_(rm), shift_(shift), amount_(amount), rs_(NoReg) {
85 VIXL_ASSERT(rm_.IsValid());
112 : imm_(0), rm_(rm), shift_(shift), amount_(0), rs_(rs) {
113 VIXL_ASSERT(rm_.IsValid() && rs_.IsValid());
142 bool IsImmediate() const { return !rm_.IsValid(); }
145 return rm_.IsValid() && !shift_.IsRRX() && !rs_.IsValid() && (amount_ == 0);
149 return rm_.IsValid() && !rs_.IsValid();
153 return rm_.IsValid() && rs_.IsValid();
170 return rm_;
216 Register rm_;
359 : imm_(immediate), rm_(NoDReg) {}
361 : imm_(immediate), rm_(NoDReg) {}
363 : imm_(immediate), rm_(NoDReg) {}
365 : imm_(immediate), rm_(NoDReg) {}
367 : imm_(immediate), rm_(NoDReg) {}
369 : imm_(immediate), rm_(NoDReg) {}
371 : imm_(imm), rm_(NoDReg) {}
373 : imm_(0), rm_(rm) {
374 VIXL_ASSERT(rm_.IsValid());
377 bool IsImmediate() const { return !rm_.IsValid(); }
378 bool IsRegister() const { return rm_.IsValid(); }
388 return rm_;
393 VRegister rm_;
426 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kSRegister));
427 return SRegister(rm_.GetCode());
468 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kDRegister));
469 return DRegister(rm_.GetCode());
503 VIXL_ASSERT(rm_.IsValid());
507 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kQRegister));
508 return QRegister(rm_.GetCode());
641 rm_(NoReg),
658 rm_(NoReg),
668 rm_(NoReg),
685 rm_(rm),
689 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
699 rm_(rm),
703 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
719 rm_(rm),
723 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
735 rm_(rm),
739 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
758 rm_(rm),
762 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
779 rm_(rm),
783 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
796 Register GetOffsetRegister() const { return rm_; }
806 bool IsImmediate() const { return !rm_.IsValid(); }
807 bool IsImmediateZero() const { return !rm_.IsValid() && (offset_ == 0); }
809 return rm_.IsValid() && shift_.IsLSL() && (shift_amount_ == 0);
811 bool IsShiftedRegister() const { return rm_.IsValid(); }
813 return (GetAddrMode() == Offset) && !rm_.IsValid();
816 return (GetAddrMode() == Offset) && !rm_.IsValid() && (offset_ == 0);
819 return (GetAddrMode() == Offset) && rm_.IsValid() && shift_.IsLSL() &&
823 return (GetAddrMode() == Offset) && rm_.IsValid();
867 Register rm_;