Lines Matching refs:operand
566 bool AliasesAvailableScratchRegister([[maybe_unused]] const Operand& operand) {
568 if (operand.IsImmediate()) return false;
569 return AliasesAvailableScratchRegister(operand.GetBaseRegister()) ||
570 (operand.IsRegisterShiftedRegister() &&
571 AliasesAvailableScratchRegister(operand.GetShiftRegister()));
576 bool AliasesAvailableScratchRegister([[maybe_unused]] const NeonOperand& operand) {
578 if (operand.IsImmediate()) return false;
579 return AliasesAvailableScratchRegister(operand.GetRegister());
621 bool AliasesAvailableScratchRegister([[maybe_unused]] const MemOperand& operand) {
623 return AliasesAvailableScratchRegister(operand.GetBaseRegister()) ||
624 (operand.IsShiftedRegister() &&
625 AliasesAvailableScratchRegister(operand.GetOffsetRegister()));
1002 const Operand& operand) VIXL_OVERRIDE;
1009 const Operand& operand) VIXL_OVERRIDE;
1017 const Operand& operand) VIXL_OVERRIDE;
1038 const Operand& operand) VIXL_OVERRIDE;
1050 const SOperand& operand) VIXL_OVERRIDE;
1057 const DOperand& operand) VIXL_OVERRIDE;
1064 const QOperand& operand) VIXL_OVERRIDE;
1071 const MemOperand& operand) VIXL_OVERRIDE;
1089 const MemOperand& operand) VIXL_OVERRIDE;
1096 const MemOperand& operand) VIXL_OVERRIDE;
1103 const MemOperand& operand) VIXL_OVERRIDE;
1109 const Operand& operand) VIXL_OVERRIDE;
1125 void Adc(Condition cond, Register rd, Register rn, const Operand& operand) {
1128 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1134 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) &&
1135 operand.GetBaseRegister().IsLow();
1141 adc(cond, rd, rn, operand);
1143 void Adc(Register rd, Register rn, const Operand& operand) {
1144 Adc(al, rd, rn, operand);
1150 const Operand& operand) {
1153 Adc(cond, rd, rn, operand);
1156 Adcs(cond, rd, rn, operand);
1160 rn.Is(rd) && operand.IsPlainRegister() &&
1161 operand.GetBaseRegister().IsLow();
1163 Adcs(cond, rd, rn, operand);
1165 Adc(cond, rd, rn, operand);
1173 const Operand& operand) {
1174 Adc(flags, al, rd, rn, operand);
1177 void Adcs(Condition cond, Register rd, Register rn, const Operand& operand) {
1180 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1189 adcs(cond, rd, rn, operand);
1191 void Adcs(Register rd, Register rn, const Operand& operand) {
1192 Adcs(al, rd, rn, operand);
1195 void Add(Condition cond, Register rd, Register rn, const Operand& operand) {
1198 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1202 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
1203 uint32_t immediate = operand.GetImmediate();
1210 (operand.IsImmediate() && (operand.GetImmediate() <= 7) && rn.IsLow() &&
1213 (operand.IsImmediate() && (operand.GetImmediate() <= 255) &&
1216 (operand.IsImmediate() && (operand.GetImmediate() <= 1020) &&
1217 ((operand.GetImmediate() & 0x3) == 0) && rd.IsLow() && rn.IsSP()) ||
1219 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
1220 operand.GetBaseRegister().IsLow()) ||
1222 (operand.IsPlainRegister() && !rd.IsPC() && rn.Is(rd) &&
1223 !operand.GetBaseRegister().IsSP() &&
1224 !operand.GetBaseRegister().IsPC()) ||
1226 (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() &&
1227 operand.GetBaseRegister().Is(rd));
1233 add(cond, rd, rn, operand);
1235 void Add(Register rd, Register rn, const Operand& operand) {
1236 Add(al, rd, rn, operand);
1242 const Operand& operand) {
1245 Add(cond, rd, rn, operand);
1248 Adds(cond, rd, rn, operand);
1253 ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
1254 !rd.Is(rn) && operand.GetBaseRegister().IsLow()) ||
1255 (operand.IsImmediate() &&
1256 ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) ||
1257 (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256)))));
1259 Adds(cond, rd, rn, operand);
1262 operand.IsImmediate() && (operand.GetSignedImmediate() < 0) &&
1264 (operand.GetSignedImmediate() >= -7)) ||
1266 (operand.GetSignedImmediate() >= -255)));
1268 Subs(cond, rd, rn, -operand.GetSignedImmediate());
1270 Add(cond, rd, rn, operand);
1279 const Operand& operand) {
1280 Add(flags, al, rd, rn, operand);
1283 void Adds(Condition cond, Register rd, Register rn, const Operand& operand) {
1286 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1295 adds(cond, rd, rn, operand);
1297 void Adds(Register rd, Register rn, const Operand& operand) {
1298 Adds(al, rd, rn, operand);
1301 void And(Condition cond, Register rd, Register rn, const Operand& operand) {
1304 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1308 if (rd.Is(rn) && operand.IsPlainRegister() &&
1309 rd.Is(operand.GetBaseRegister())) {
1312 if (cond.Is(al) && operand.IsImmediate()) {
1313 uint32_t immediate = operand.GetImmediate();
1324 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1325 operand.GetBaseRegister().IsLow();
1331 and_(cond, rd, rn, operand);
1333 void And(Register rd, Register rn, const Operand& operand) {
1334 And(al, rd, rn, operand);
1340 const Operand& operand) {
1343 And(cond, rd, rn, operand);
1346 Ands(cond, rd, rn, operand);
1349 if (operand.IsPlainRegister() && rd.Is(rn) &&
1350 rd.Is(operand.GetBaseRegister())) {
1354 rn.Is(rd) && operand.IsPlainRegister() &&
1355 operand.GetBaseRegister().IsLow();
1357 Ands(cond, rd, rn, operand);
1359 And(cond, rd, rn, operand);
1367 const Operand& operand) {
1368 And(flags, al, rd, rn, operand);
1371 void Ands(Condition cond, Register rd, Register rn, const Operand& operand) {
1374 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1383 ands(cond, rd, rn, operand);
1385 void Ands(Register rd, Register rn, const Operand& operand) {
1386 Ands(al, rd, rn, operand);
1389 void Asr(Condition cond, Register rd, Register rm, const Operand& operand) {
1392 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1398 (operand.IsImmediate() && (operand.GetImmediate() >= 1) &&
1399 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) ||
1401 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
1402 operand.GetBaseRegister().IsLow());
1408 asr(cond, rd, rm, operand);
1410 void Asr(Register rd, Register rm, const Operand& operand) {
1411 Asr(al, rd, rm, operand);
1417 const Operand& operand) {
1420 Asr(cond, rd, rm, operand);
1423 Asrs(cond, rd, rm, operand);
1428 ((operand.IsImmediate() && (operand.GetImmediate() >= 1) &&
1429 (operand.GetImmediate() <= 32)) ||
1430 (operand.IsPlainRegister() && rd.Is(rm)));
1432 Asrs(cond, rd, rm, operand);
1434 Asr(cond, rd, rm, operand);
1442 const Operand& operand) {
1443 Asr(flags, al, rd, rm, operand);
1446 void Asrs(Condition cond, Register rd, Register rm, const Operand& operand) {
1449 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1458 asrs(cond, rd, rm, operand);
1460 void Asrs(Register rd, Register rm, const Operand& operand) {
1461 Asrs(al, rd, rm, operand);
1523 void Bic(Condition cond, Register rd, Register rn, const Operand& operand) {
1526 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1530 if (cond.Is(al) && operand.IsImmediate()) {
1531 uint32_t immediate = operand.GetImmediate();
1542 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1543 operand.GetBaseRegister().IsLow();
1549 bic(cond, rd, rn, operand);
1551 void Bic(Register rd, Register rn, const Operand& operand) {
1552 Bic(al, rd, rn, operand);
1558 const Operand& operand) {
1561 Bic(cond, rd, rn, operand);
1564 Bics(cond, rd, rn, operand);
1568 rn.Is(rd) && operand.IsPlainRegister() &&
1569 operand.GetBaseRegister().IsLow();
1571 Bics(cond, rd, rn, operand);
1573 Bic(cond, rd, rn, operand);
1581 const Operand& operand) {
1582 Bic(flags, al, rd, rn, operand);
1585 void Bics(Condition cond, Register rd, Register rn, const Operand& operand) {
1588 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1597 bics(cond, rd, rn, operand);
1599 void Bics(Register rd, Register rn, const Operand& operand) {
1600 Bics(al, rd, rn, operand);
1778 void Cmn(Condition cond, Register rn, const Operand& operand) {
1780 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1786 operand.IsPlainRegister() && rn.IsLow() &&
1787 operand.GetBaseRegister().IsLow();
1793 cmn(cond, rn, operand);
1795 void Cmn(Register rn, const Operand& operand) { Cmn(al, rn, operand); }
1797 void Cmp(Condition cond, Register rn, const Operand& operand) {
1799 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1805 (operand.IsImmediate() && (operand.GetImmediate() <= 255) &&
1808 (operand.IsPlainRegister() && !rn.IsPC() &&
1809 !operand.GetBaseRegister().IsPC());
1815 cmp(cond, rn, operand);
1817 void Cmp(Register rn, const Operand& operand) { Cmp(al, rn, operand); }
1947 void Eor(Condition cond, Register rd, Register rn, const Operand& operand) {
1950 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
1954 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
1955 uint32_t immediate = operand.GetImmediate();
1966 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1967 operand.GetBaseRegister().IsLow();
1973 eor(cond, rd, rn, operand);
1975 void Eor(Register rd, Register rn, const Operand& operand) {
1976 Eor(al, rd, rn, operand);
1982 const Operand& operand) {
1985 Eor(cond, rd, rn, operand);
1988 Eors(cond, rd, rn, operand);
1992 rn.Is(rd) && operand.IsPlainRegister() &&
1993 operand.GetBaseRegister().IsLow();
1995 Eors(cond, rd, rn, operand);
1997 Eor(cond, rd, rn, operand);
2005 const Operand& operand) {
2006 Eor(flags, al, rd, rn, operand);
2009 void Eors(Condition cond, Register rd, Register rn, const Operand& operand) {
2012 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2021 eors(cond, rd, rn, operand);
2023 void Eors(Register rd, Register rn, const Operand& operand) {
2024 Eors(al, rd, rn, operand);
2146 void Lda(Condition cond, Register rt, const MemOperand& operand) {
2148 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2157 lda(cond, rt, operand);
2159 void Lda(Register rt, const MemOperand& operand) { Lda(al, rt, operand); }
2161 void Ldab(Condition cond, Register rt, const MemOperand& operand) {
2163 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2172 ldab(cond, rt, operand);
2174 void Ldab(Register rt, const MemOperand& operand) { Ldab(al, rt, operand); }
2176 void Ldaex(Condition cond, Register rt, const MemOperand& operand) {
2178 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2187 ldaex(cond, rt, operand);
2189 void Ldaex(Register rt, const MemOperand& operand) { Ldaex(al, rt, operand); }
2191 void Ldaexb(Condition cond, Register rt, const MemOperand& operand) {
2193 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2202 ldaexb(cond, rt, operand);
2204 void Ldaexb(Register rt, const MemOperand& operand) {
2205 Ldaexb(al, rt, operand);
2211 const MemOperand& operand) {
2214 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2223 ldaexd(cond, rt, rt2, operand);
2225 void Ldaexd(Register rt, Register rt2, const MemOperand& operand) {
2226 Ldaexd(al, rt, rt2, operand);
2229 void Ldaexh(Condition cond, Register rt, const MemOperand& operand) {
2231 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2240 ldaexh(cond, rt, operand);
2242 void Ldaexh(Register rt, const MemOperand& operand) {
2243 Ldaexh(al, rt, operand);
2246 void Ldah(Condition cond, Register rt, const MemOperand& operand) {
2248 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2257 ldah(cond, rt, operand);
2259 void Ldah(Register rt, const MemOperand& operand) { Ldah(al, rt, operand); }
2421 void Ldr(Condition cond, Register rt, const MemOperand& operand) {
2423 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2429 (operand.IsImmediate() && rt.IsLow() &&
2430 operand.GetBaseRegister().IsLow() &&
2431 operand.IsOffsetImmediateWithinRange(0, 124, 4) &&
2432 (operand.GetAddrMode() == Offset)) ||
2434 (operand.IsImmediate() && rt.IsLow() &&
2435 operand.GetBaseRegister().IsSP() &&
2436 operand.IsOffsetImmediateWithinRange(0, 1020, 4) &&
2437 (operand.GetAddrMode() == Offset)) ||
2439 (operand.IsPlainRegister() && rt.IsLow() &&
2440 operand.GetBaseRegister().IsLow() &&
2441 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
2442 (operand.GetAddrMode() == Offset));
2448 ldr(cond, rt, operand);
2450 void Ldr(Register rt, const MemOperand& operand) { Ldr(al, rt, operand); }
2453 void Ldrb(Condition cond, Register rt, const MemOperand& operand) {
2455 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2461 (operand.IsImmediate() && rt.IsLow() &&
2462 operand.GetBaseRegister().IsLow() &&
2463 operand.IsOffsetImmediateWithinRange(0, 31) &&
2464 (operand.GetAddrMode() == Offset)) ||
2466 (operand.IsPlainRegister() && rt.IsLow() &&
2467 operand.GetBaseRegister().IsLow() &&
2468 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
2469 (operand.GetAddrMode() == Offset));
2475 ldrb(cond, rt, operand);
2477 void Ldrb(Register rt, const MemOperand& operand) { Ldrb(al, rt, operand); }
2483 const MemOperand& operand) {
2486 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2495 ldrd(cond, rt, rt2, operand);
2497 void Ldrd(Register rt, Register rt2, const MemOperand& operand) {
2498 Ldrd(al, rt, rt2, operand);
2502 void Ldrex(Condition cond, Register rt, const MemOperand& operand) {
2504 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2513 ldrex(cond, rt, operand);
2515 void Ldrex(Register rt, const MemOperand& operand) { Ldrex(al, rt, operand); }
2517 void Ldrexb(Condition cond, Register rt, const MemOperand& operand) {
2519 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2528 ldrexb(cond, rt, operand);
2530 void Ldrexb(Register rt, const MemOperand& operand) {
2531 Ldrexb(al, rt, operand);
2537 const MemOperand& operand) {
2540 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2549 ldrexd(cond, rt, rt2, operand);
2551 void Ldrexd(Register rt, Register rt2, const MemOperand& operand) {
2552 Ldrexd(al, rt, rt2, operand);
2555 void Ldrexh(Condition cond, Register rt, const MemOperand& operand) {
2557 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2566 ldrexh(cond, rt, operand);
2568 void Ldrexh(Register rt, const MemOperand& operand) {
2569 Ldrexh(al, rt, operand);
2572 void Ldrh(Condition cond, Register rt, const MemOperand& operand) {
2574 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2580 (operand.IsImmediate() && rt.IsLow() &&
2581 operand.GetBaseRegister().IsLow() &&
2582 operand.IsOffsetImmediateWithinRange(0, 62, 2) &&
2583 (operand.GetAddrMode() == Offset)) ||
2585 (operand.IsPlainRegister() && rt.IsLow() &&
2586 operand.GetBaseRegister().IsLow() &&
2587 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
2588 (operand.GetAddrMode() == Offset));
2594 ldrh(cond, rt, operand);
2596 void Ldrh(Register rt, const MemOperand& operand) { Ldrh(al, rt, operand); }
2599 void Ldrsb(Condition cond, Register rt, const MemOperand& operand) {
2601 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2607 operand.IsPlainRegister() && rt.IsLow() &&
2608 operand.GetBaseRegister().IsLow() &&
2609 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
2610 (operand.GetAddrMode() == Offset);
2616 ldrsb(cond, rt, operand);
2618 void Ldrsb(Register rt, const MemOperand& operand) { Ldrsb(al, rt, operand); }
2621 void Ldrsh(Condition cond, Register rt, const MemOperand& operand) {
2623 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2629 operand.IsPlainRegister() && rt.IsLow() &&
2630 operand.GetBaseRegister().IsLow() &&
2631 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
2632 (operand.GetAddrMode() == Offset);
2638 ldrsh(cond, rt, operand);
2640 void Ldrsh(Register rt, const MemOperand& operand) { Ldrsh(al, rt, operand); }
2643 void Lsl(Condition cond, Register rd, Register rm, const Operand& operand) {
2646 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2652 (operand.IsImmediate() && (operand.GetImmediate() >= 1) &&
2653 (operand.GetImmediate() <= 31) && rd.IsLow() && rm.IsLow()) ||
2655 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
2656 operand.GetBaseRegister().IsLow());
2662 lsl(cond, rd, rm, operand);
2664 void Lsl(Register rd, Register rm, const Operand& operand) {
2665 Lsl(al, rd, rm, operand);
2671 const Operand& operand) {
2674 Lsl(cond, rd, rm, operand);
2677 Lsls(cond, rd, rm, operand);
2682 ((operand.IsImmediate() && (operand.GetImmediate() >= 1) &&
2683 (operand.GetImmediate() < 32)) ||
2684 (operand.IsPlainRegister() && rd.Is(rm)));
2686 Lsls(cond, rd, rm, operand);
2688 Lsl(cond, rd, rm, operand);
2696 const Operand& operand) {
2697 Lsl(flags, al, rd, rm, operand);
2700 void Lsls(Condition cond, Register rd, Register rm, const Operand& operand) {
2703 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2712 lsls(cond, rd, rm, operand);
2714 void Lsls(Register rd, Register rm, const Operand& operand) {
2715 Lsls(al, rd, rm, operand);
2718 void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) {
2721 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2727 (operand.IsImmediate() && (operand.GetImmediate() >= 1) &&
2728 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) ||
2730 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
2731 operand.GetBaseRegister().IsLow());
2737 lsr(cond, rd, rm, operand);
2739 void Lsr(Register rd, Register rm, const Operand& operand) {
2740 Lsr(al, rd, rm, operand);
2746 const Operand& operand) {
2749 Lsr(cond, rd, rm, operand);
2752 Lsrs(cond, rd, rm, operand);
2757 ((operand.IsImmediate() && (operand.GetImmediate() >= 1) &&
2758 (operand.GetImmediate() <= 32)) ||
2759 (operand.IsPlainRegister() && rd.Is(rm)));
2761 Lsrs(cond, rd, rm, operand);
2763 Lsr(cond, rd, rm, operand);
2771 const Operand& operand) {
2772 Lsr(flags, al, rd, rm, operand);
2775 void Lsrs(Condition cond, Register rd, Register rm, const Operand& operand) {
2778 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2787 lsrs(cond, rd, rm, operand);
2789 void Lsrs(Register rd, Register rm, const Operand& operand) {
2790 Lsrs(al, rd, rm, operand);
2873 void Mov(Condition cond, Register rd, const Operand& operand) {
2875 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2879 if (operand.IsPlainRegister() && rd.Is(operand.GetBaseRegister())) {
2884 (operand.IsImmediate() && rd.IsLow() &&
2885 (operand.GetImmediate() <= 255)) ||
2887 (operand.IsPlainRegister() && !rd.IsPC() &&
2888 !operand.GetBaseRegister().IsPC()) ||
2890 (operand.IsImmediateShiftedRegister() && rd.IsLow() &&
2891 operand.GetBaseRegister().IsLow() &&
2892 (operand.GetShift().Is(LSL) || operand.GetShift().Is(LSR) ||
2893 operand.GetShift().Is(ASR))) ||
2898 (operand.IsRegisterShiftedRegister() &&
2899 rd.Is(operand.GetBaseRegister()) && rd.IsLow() &&
2900 (operand.GetShift().Is(LSL) || operand.GetShift().Is(LSR) ||
2901 operand.GetShift().Is(ASR) || operand.GetShift().Is(ROR)) &&
2902 operand.GetShiftRegister().IsLow());
2908 mov(cond, rd, operand);
2910 void Mov(Register rd, const Operand& operand) { Mov(al, rd, operand); }
2914 const Operand& operand) {
2917 Mov(cond, rd, operand);
2920 Movs(cond, rd, operand);
2923 if (operand.IsPlainRegister() && rd.Is(operand.GetBaseRegister())) {
2928 ((operand.IsImmediateShiftedRegister() && rd.IsLow() &&
2929 operand.GetBaseRegister().IsLow() &&
2930 (operand.GetShiftAmount() >= 1) &&
2931 (((operand.GetShiftAmount() <= 32) &&
2932 ((operand.GetShift().IsLSR() || operand.GetShift().IsASR()))) ||
2933 ((operand.GetShiftAmount() < 32) &&
2934 operand.GetShift().IsLSL()))) ||
2935 (operand.IsRegisterShiftedRegister() && rd.IsLow() &&
2936 operand.GetBaseRegister().Is(rd) &&
2937 operand.GetShiftRegister().IsLow() &&
2938 (operand.GetShift().IsLSL() || operand.GetShift().IsLSR() ||
2939 operand.GetShift().IsASR() || operand.GetShift().IsROR())) ||
2940 (operand.IsImmediate() && rd.IsLow() &&
2941 (operand.GetImmediate() < 256)));
2943 Movs(cond, rd, operand);
2945 Mov(cond, rd, operand);
2950 void Mov(FlagsUpdate flags, Register rd, const Operand& operand) {
2951 Mov(flags, al, rd, operand);
2954 void Movs(Condition cond, Register rd, const Operand& operand) {
2956 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2965 movs(cond, rd, operand);
2967 void Movs(Register rd, const Operand& operand) { Movs(al, rd, operand); }
2969 void Movt(Condition cond, Register rd, const Operand& operand) {
2971 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
2980 movt(cond, rd, operand);
2982 void Movt(Register rd, const Operand& operand) { Movt(al, rd, operand); }
3000 const Operand& operand) {
3001 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3010 msr(cond, spec_reg, operand);
3012 void Msr(MaskedSpecialRegister spec_reg, const Operand& operand) {
3013 Msr(al, spec_reg, operand);
3077 void Mvn(Condition cond, Register rd, const Operand& operand) {
3079 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3085 operand.IsPlainRegister() && rd.IsLow() &&
3086 operand.GetBaseRegister().IsLow();
3092 mvn(cond, rd, operand);
3094 void Mvn(Register rd, const Operand& operand) { Mvn(al, rd, operand); }
3098 const Operand& operand) {
3101 Mvn(cond, rd, operand);
3104 Mvns(cond, rd, operand);
3108 operand.IsPlainRegister() &&
3109 operand.GetBaseRegister().IsLow();
3111 Mvns(cond, rd, operand);
3113 Mvn(cond, rd, operand);
3118 void Mvn(FlagsUpdate flags, Register rd, const Operand& operand) {
3119 Mvn(flags, al, rd, operand);
3122 void Mvns(Condition cond, Register rd, const Operand& operand) {
3124 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3133 mvns(cond, rd, operand);
3135 void Mvns(Register rd, const Operand& operand) { Mvns(al, rd, operand); }
3150 void Orn(Condition cond, Register rd, Register rn, const Operand& operand) {
3153 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3157 if (cond.Is(al) && operand.IsImmediate()) {
3158 uint32_t immediate = operand.GetImmediate();
3172 orn(cond, rd, rn, operand);
3174 void Orn(Register rd, Register rn, const Operand& operand) {
3175 Orn(al, rd, rn, operand);
3181 const Operand& operand) {
3184 Orn(cond, rd, rn, operand);
3187 Orns(cond, rd, rn, operand);
3190 Orn(cond, rd, rn, operand);
3197 const Operand& operand) {
3198 Orn(flags, al, rd, rn, operand);
3201 void Orns(Condition cond, Register rd, Register rn, const Operand& operand) {
3204 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3213 orns(cond, rd, rn, operand);
3215 void Orns(Register rd, Register rn, const Operand& operand) {
3216 Orns(al, rd, rn, operand);
3219 void Orr(Condition cond, Register rd, Register rn, const Operand& operand) {
3222 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3226 if (rd.Is(rn) && operand.IsPlainRegister() &&
3227 rd.Is(operand.GetBaseRegister())) {
3230 if (cond.Is(al) && operand.IsImmediate()) {
3231 uint32_t immediate = operand.GetImmediate();
3242 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
3243 operand.GetBaseRegister().IsLow();
3249 orr(cond, rd, rn, operand);
3251 void Orr(Register rd, Register rn, const Operand& operand) {
3252 Orr(al, rd, rn, operand);
3258 const Operand& operand) {
3261 Orr(cond, rd, rn, operand);
3264 Orrs(cond, rd, rn, operand);
3267 if (operand.IsPlainRegister() && rd.Is(rn) &&
3268 rd.Is(operand.GetBaseRegister())) {
3272 rn.Is(rd) && operand.IsPlainRegister() &&
3273 operand.GetBaseRegister().IsLow();
3275 Orrs(cond, rd, rn, operand);
3277 Orr(cond, rd, rn, operand);
3285 const Operand& operand) {
3286 Orr(flags, al, rd, rn, operand);
3289 void Orrs(Condition cond, Register rd, Register rn, const Operand& operand) {
3292 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3301 orrs(cond, rd, rn, operand);
3303 void Orrs(Register rd, Register rn, const Operand& operand) {
3304 Orrs(al, rd, rn, operand);
3307 void Pkhbt(Condition cond, Register rd, Register rn, const Operand& operand) {
3310 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3319 pkhbt(cond, rd, rn, operand);
3321 void Pkhbt(Register rd, Register rn, const Operand& operand) {
3322 Pkhbt(al, rd, rn, operand);
3325 void Pkhtb(Condition cond, Register rd, Register rn, const Operand& operand) {
3328 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3337 pkhtb(cond, rd, rn, operand);
3339 void Pkhtb(Register rd, Register rn, const Operand& operand) {
3340 Pkhtb(al, rd, rn, operand);
3344 void Pld(Condition cond, const MemOperand& operand) {
3345 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3354 pld(cond, operand);
3356 void Pld(const MemOperand& operand) { Pld(al, operand); }
3358 void Pldw(Condition cond, const MemOperand& operand) {
3359 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3368 pldw(cond, operand);
3370 void Pldw(const MemOperand& operand) { Pldw(al, operand); }
3372 void Pli(Condition cond, const MemOperand& operand) {
3373 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3382 pli(cond, operand);
3384 void Pli(const MemOperand& operand) { Pli(al, operand); }
3678 void Ror(Condition cond, Register rd, Register rm, const Operand& operand) {
3681 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3687 operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
3688 operand.GetBaseRegister().IsLow();
3694 ror(cond, rd, rm, operand);
3696 void Ror(Register rd, Register rm, const Operand& operand) {
3697 Ror(al, rd, rm, operand);
3703 const Operand& operand) {
3706 Ror(cond, rd, rm, operand);
3709 Rors(cond, rd, rm, operand);
3713 rm.IsLow() && operand.IsPlainRegister() &&
3716 Rors(cond, rd, rm, operand);
3718 Ror(cond, rd, rm, operand);
3726 const Operand& operand) {
3727 Ror(flags, al, rd, rm, operand);
3730 void Rors(Condition cond, Register rd, Register rm, const Operand& operand) {
3733 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3742 rors(cond, rd, rm, operand);
3744 void Rors(Register rd, Register rm, const Operand& operand) {
3745 Rors(al, rd, rm, operand);
3794 void Rsb(Condition cond, Register rd, Register rn, const Operand& operand) {
3797 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3803 operand.IsImmediate() && rd.IsLow() && rn.IsLow() &&
3804 (operand.GetImmediate() == 0);
3810 rsb(cond, rd, rn, operand);
3812 void Rsb(Register rd, Register rn, const Operand& operand) {
3813 Rsb(al, rd, rn, operand);
3819 const Operand& operand) {
3822 Rsb(cond, rd, rn, operand);
3825 Rsbs(cond, rd, rn, operand);
3829 rn.IsLow() && operand.IsImmediate() &&
3830 (operand.GetImmediate() == 0);
3832 Rsbs(cond, rd, rn, operand);
3834 Rsb(cond, rd, rn, operand);
3842 const Operand& operand) {
3843 Rsb(flags, al, rd, rn, operand);
3846 void Rsbs(Condition cond, Register rd, Register rn, const Operand& operand) {
3849 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3858 rsbs(cond, rd, rn, operand);
3860 void Rsbs(Register rd, Register rn, const Operand& operand) {
3861 Rsbs(al, rd, rn, operand);
3864 void Rsc(Condition cond, Register rd, Register rn, const Operand& operand) {
3867 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3876 rsc(cond, rd, rn, operand);
3878 void Rsc(Register rd, Register rn, const Operand& operand) {
3879 Rsc(al, rd, rn, operand);
3885 const Operand& operand) {
3888 Rsc(cond, rd, rn, operand);
3891 Rscs(cond, rd, rn, operand);
3894 Rsc(cond, rd, rn, operand);
3901 const Operand& operand) {
3902 Rsc(flags, al, rd, rn, operand);
3905 void Rscs(Condition cond, Register rd, Register rn, const Operand& operand) {
3908 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3917 rscs(cond, rd, rn, operand);
3919 void Rscs(Register rd, Register rn, const Operand& operand) {
3920 Rscs(al, rd, rn, operand);
3971 void Sbc(Condition cond, Register rd, Register rn, const Operand& operand) {
3974 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
3980 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) &&
3981 operand.GetBaseRegister().IsLow();
3987 sbc(cond, rd, rn, operand);
3989 void Sbc(Register rd, Register rn, const Operand& operand) {
3990 Sbc(al, rd, rn, operand);
3996 const Operand& operand) {
3999 Sbc(cond, rd, rn, operand);
4002 Sbcs(cond, rd, rn, operand);
4006 rn.Is(rd) && operand.IsPlainRegister() &&
4007 operand.GetBaseRegister().IsLow();
4009 Sbcs(cond, rd, rn, operand);
4011 Sbc(cond, rd, rn, operand);
4019 const Operand& operand) {
4020 Sbc(flags, al, rd, rn, operand);
4023 void Sbcs(Condition cond, Register rd, Register rn, const Operand& operand) {
4026 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
4035 sbcs(cond, rd, rn, operand);
4037 void Sbcs(Register rd, Register rn, const Operand& operand) {
4038 Sbcs(al, rd, rn, operand);
4928 void Ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand) {
4930 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
4939 ssat(cond, rd, imm, operand);
4941 void Ssat(Register rd, uint32_t imm, const Operand& operand) {
4942 Ssat(al, rd, imm, operand);
5010 void Stl(Condition cond, Register rt, const MemOperand& operand) {
5012 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5021 stl(cond, rt, operand);
5023 void Stl(Register rt, const MemOperand& operand) { Stl(al, rt, operand); }
5025 void Stlb(Condition cond, Register rt, const MemOperand& operand) {
5027 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5036 stlb(cond, rt, operand);
5038 void Stlb(Register rt, const MemOperand& operand) { Stlb(al, rt, operand); }
5043 const MemOperand& operand) {
5046 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5055 stlex(cond, rd, rt, operand);
5057 void Stlex(Register rd, Register rt, const MemOperand& operand) {
5058 Stlex(al, rd, rt, operand);
5064 const MemOperand& operand) {
5067 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5076 stlexb(cond, rd, rt, operand);
5078 void Stlexb(Register rd, Register rt, const MemOperand& operand) {
5079 Stlexb(al, rd, rt, operand);
5086 const MemOperand& operand) {
5090 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5099 stlexd(cond, rd, rt, rt2, operand);
5104 const MemOperand& operand) {
5105 Stlexd(al, rd, rt, rt2, operand);
5111 const MemOperand& operand) {
5114 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5123 stlexh(cond, rd, rt, operand);
5125 void Stlexh(Register rd, Register rt, const MemOperand& operand) {
5126 Stlexh(al, rd, rt, operand);
5129 void Stlh(Condition cond, Register rt, const MemOperand& operand) {
5131 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5140 stlh(cond, rt, operand);
5142 void Stlh(Register rt, const MemOperand& operand) { Stlh(al, rt, operand); }
5304 void Str(Condition cond, Register rt, const MemOperand& operand) {
5306 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5312 (operand.IsImmediate() && rt.IsLow() &&
5313 operand.GetBaseRegister().IsLow() &&
5314 operand.IsOffsetImmediateWithinRange(0, 124, 4) &&
5315 (operand.GetAddrMode() == Offset)) ||
5317 (operand.IsImmediate() && rt.IsLow() &&
5318 operand.GetBaseRegister().IsSP() &&
5319 operand.IsOffsetImmediateWithinRange(0, 1020, 4) &&
5320 (operand.GetAddrMode() == Offset)) ||
5322 (operand.IsPlainRegister() && rt.IsLow() &&
5323 operand.GetBaseRegister().IsLow() &&
5324 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
5325 (operand.GetAddrMode() == Offset));
5331 str(cond, rt, operand);
5333 void Str(Register rt, const MemOperand& operand) { Str(al, rt, operand); }
5335 void Strb(Condition cond, Register rt, const MemOperand& operand) {
5337 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5343 (operand.IsImmediate() && rt.IsLow() &&
5344 operand.GetBaseRegister().IsLow() &&
5345 operand.IsOffsetImmediateWithinRange(0, 31) &&
5346 (operand.GetAddrMode() == Offset)) ||
5348 (operand.IsPlainRegister() && rt.IsLow() &&
5349 operand.GetBaseRegister().IsLow() &&
5350 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
5351 (operand.GetAddrMode() == Offset));
5357 strb(cond, rt, operand);
5359 void Strb(Register rt, const MemOperand& operand) { Strb(al, rt, operand); }
5364 const MemOperand& operand) {
5367 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5376 strd(cond, rt, rt2, operand);
5378 void Strd(Register rt, Register rt2, const MemOperand& operand) {
5379 Strd(al, rt, rt2, operand);
5385 const MemOperand& operand) {
5388 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5397 strex(cond, rd, rt, operand);
5399 void Strex(Register rd, Register rt, const MemOperand& operand) {
5400 Strex(al, rd, rt, operand);
5406 const MemOperand& operand) {
5409 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5418 strexb(cond, rd, rt, operand);
5420 void Strexb(Register rd, Register rt, const MemOperand& operand) {
5421 Strexb(al, rd, rt, operand);
5428 const MemOperand& operand) {
5432 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5441 strexd(cond, rd, rt, rt2, operand);
5446 const MemOperand& operand) {
5447 Strexd(al, rd, rt, rt2, operand);
5453 const MemOperand& operand) {
5456 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5465 strexh(cond, rd, rt, operand);
5467 void Strexh(Register rd, Register rt, const MemOperand& operand) {
5468 Strexh(al, rd, rt, operand);
5471 void Strh(Condition cond, Register rt, const MemOperand& operand) {
5473 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5479 (operand.IsImmediate() && rt.IsLow() &&
5480 operand.GetBaseRegister().IsLow() &&
5481 operand.IsOffsetImmediateWithinRange(0, 62, 2) &&
5482 (operand.GetAddrMode() == Offset)) ||
5484 (operand.IsPlainRegister() && rt.IsLow() &&
5485 operand.GetBaseRegister().IsLow() &&
5486 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() &&
5487 (operand.GetAddrMode() == Offset));
5493 strh(cond, rt, operand);
5495 void Strh(Register rt, const MemOperand& operand) { Strh(al, rt, operand); }
5497 void Sub(Condition cond, Register rd, Register rn, const Operand& operand) {
5500 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5504 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
5505 uint32_t immediate = operand.GetImmediate();
5512 (operand.IsImmediate() && (operand.GetImmediate() <= 7) && rn.IsLow() &&
5515 (operand.IsImmediate() && (operand.GetImmediate() <= 255) &&
5518 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
5519 operand.GetBaseRegister().IsLow());
5525 sub(cond, rd, rn, operand);
5527 void Sub(Register rd, Register rn, const Operand& operand) {
5528 Sub(al, rd, rn, operand);
5534 const Operand& operand) {
5537 Sub(cond, rd, rn, operand);
5540 Subs(cond, rd, rn, operand);
5545 ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
5546 operand.GetBaseRegister().IsLow()) ||
5547 (operand.IsImmediate() &&
5548 ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) ||
5549 (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256)))));
5551 Subs(cond, rd, rn, operand);
5554 operand.IsImmediate() && (operand.GetSignedImmediate() < 0) &&
5556 (operand.GetSignedImmediate() >= -7)) ||
5558 (operand.GetSignedImmediate() >= -255)));
5560 Adds(cond, rd, rn, -operand.GetSignedImmediate());
5562 Sub(cond, rd, rn, operand);
5571 const Operand& operand) {
5572 Sub(flags, al, rd, rn, operand);
5575 void Subs(Condition cond, Register rd, Register rn, const Operand& operand) {
5578 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5587 subs(cond, rd, rn, operand);
5589 void Subs(Register rd, Register rn, const Operand& operand) {
5590 Subs(al, rd, rn, operand);
5606 void Sxtab(Condition cond, Register rd, Register rn, const Operand& operand) {
5609 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5618 sxtab(cond, rd, rn, operand);
5620 void Sxtab(Register rd, Register rn, const Operand& operand) {
5621 Sxtab(al, rd, rn, operand);
5627 const Operand& operand) {
5630 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5639 sxtab16(cond, rd, rn, operand);
5641 void Sxtab16(Register rd, Register rn, const Operand& operand) {
5642 Sxtab16(al, rd, rn, operand);
5645 void Sxtah(Condition cond, Register rd, Register rn, const Operand& operand) {
5648 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5657 sxtah(cond, rd, rn, operand);
5659 void Sxtah(Register rd, Register rn, const Operand& operand) {
5660 Sxtah(al, rd, rn, operand);
5663 void Sxtb(Condition cond, Register rd, const Operand& operand) {
5665 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5674 sxtb(cond, rd, operand);
5676 void Sxtb(Register rd, const Operand& operand) { Sxtb(al, rd, operand); }
5678 void Sxtb16(Condition cond, Register rd, const Operand& operand) {
5680 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5689 sxtb16(cond, rd, operand);
5691 void Sxtb16(Register rd, const Operand& operand) { Sxtb16(al, rd, operand); }
5693 void Sxth(Condition cond, Register rd, const Operand& operand) {
5695 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5704 sxth(cond, rd, operand);
5706 void Sxth(Register rd, const Operand& operand) { Sxth(al, rd, operand); }
5708 void Teq(Condition cond, Register rn, const Operand& operand) {
5710 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5719 teq(cond, rn, operand);
5721 void Teq(Register rn, const Operand& operand) { Teq(al, rn, operand); }
5723 void Tst(Condition cond, Register rn, const Operand& operand) {
5725 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
5731 operand.IsPlainRegister() && rn.IsLow() &&
5732 operand.GetBaseRegister().IsLow();
5738 tst(cond, rn, operand);
5740 void Tst(Register rn, const Operand& operand) { Tst(al, rn, operand); }
6223 void Usat(Condition cond, Register rd, uint32_t imm, const Operand& operand) {
6225 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
6234 usat(cond, rd, imm, operand);
6236 void Usat(Register rd, uint32_t imm, const Operand& operand) {
6237 Usat(al, rd, imm, operand);
6305 void Uxtab(Condition cond, Register rd, Register rn, const Operand& operand) {
6308 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
6317 uxtab(cond, rd, rn, operand);
6319 void Uxtab(Register rd, Register rn, const Operand& operand) {
6320 Uxtab(al, rd, rn, operand);
6326 const Operand& operand) {
6329 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
6338 uxtab16(cond, rd, rn, operand);
6340 void Uxtab16(Register rd, Register rn, const Operand& operand) {
6341 Uxtab16(al, rd, rn, operand);
6344 void Uxtah(Condition cond, Register rd, Register rn, const Operand& operand) {
6347 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
6356 uxtah(cond, rd, rn, operand);
6358 void Uxtah(Register rd, Register rn, const Operand& operand) {
6359 Uxtah(al, rd, rn, operand);
6362 void Uxtb(Condition cond, Register rd, const Operand& operand) {
6364 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
6373 uxtb(cond, rd, operand);
6375 void Uxtb(Register rd, const Operand& operand) { Uxtb(al, rd, operand); }
6377 void Uxtb16(Condition cond, Register rd, const Operand& operand) {
6379 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
6388 uxtb16(cond, rd, operand);
6390 void Uxtb16(Register rd, const Operand& operand) { Uxtb16(al, rd, operand); }
6392 void Uxth(Condition cond, Register rd, const Operand& operand) {
6394 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
6403 uxth(cond, rd, operand);
6405 void Uxth(Register rd, const Operand& operand) { Uxth(al, rd, operand); }
6836 const DOperand& operand) {
6839 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
6848 vand(cond, dt, rd, rn, operand);
6850 void Vand(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
6851 Vand(al, dt, rd, rn, operand);
6858 const QOperand& operand) {
6861 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
6870 vand(cond, dt, rd, rn, operand);
6872 void Vand(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
6873 Vand(al, dt, rd, rn, operand);
6880 const DOperand& operand) {
6883 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
6892 vbic(cond, dt, rd, rn, operand);
6894 void Vbic(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
6895 Vbic(al, dt, rd, rn, operand);
6902 const QOperand& operand) {
6905 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
6914 vbic(cond, dt, rd, rn, operand);
6916 void Vbic(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
6917 Vbic(al, dt, rd, rn, operand);
7074 const DOperand& operand) {
7077 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7086 vceq(cond, dt, rd, rm, operand);
7088 void Vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
7089 Vceq(al, dt, rd, rm, operand);
7096 const QOperand& operand) {
7099 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7108 vceq(cond, dt, rd, rm, operand);
7110 void Vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
7111 Vceq(al, dt, rd, rm, operand);
7156 const DOperand& operand) {
7159 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7168 vcge(cond, dt, rd, rm, operand);
7170 void Vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
7171 Vcge(al, dt, rd, rm, operand);
7178 const QOperand& operand) {
7181 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7190 vcge(cond, dt, rd, rm, operand);
7192 void Vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
7193 Vcge(al, dt, rd, rm, operand);
7238 const DOperand& operand) {
7241 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7250 vcgt(cond, dt, rd, rm, operand);
7252 void Vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
7253 Vcgt(al, dt, rd, rm, operand);
7260 const QOperand& operand) {
7263 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7272 vcgt(cond, dt, rd, rm, operand);
7274 void Vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
7275 Vcgt(al, dt, rd, rm, operand);
7320 const DOperand& operand) {
7323 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7332 vcle(cond, dt, rd, rm, operand);
7334 void Vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
7335 Vcle(al, dt, rd, rm, operand);
7342 const QOperand& operand) {
7345 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7354 vcle(cond, dt, rd, rm, operand);
7356 void Vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
7357 Vcle(al, dt, rd, rm, operand);
7432 const DOperand& operand) {
7435 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7444 vclt(cond, dt, rd, rm, operand);
7446 void Vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
7447 Vclt(al, dt, rd, rm, operand);
7454 const QOperand& operand) {
7457 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7466 vclt(cond, dt, rd, rm, operand);
7468 void Vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
7469 Vclt(al, dt, rd, rm, operand);
7543 const SOperand& operand) {
7545 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7554 vcmp(cond, dt, rd, operand);
7556 void Vcmp(DataType dt, SRegister rd, const SOperand& operand) {
7557 Vcmp(al, dt, rd, operand);
7563 const DOperand& operand) {
7565 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7574 vcmp(cond, dt, rd, operand);
7576 void Vcmp(DataType dt, DRegister rd, const DOperand& operand) {
7577 Vcmp(al, dt, rd, operand);
7583 const SOperand& operand) {
7585 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7594 vcmpe(cond, dt, rd, operand);
7596 void Vcmpe(DataType dt, SRegister rd, const SOperand& operand) {
7597 Vcmpe(al, dt, rd, operand);
7603 const DOperand& operand) {
7605 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
7614 vcmpe(cond, dt, rd, operand);
7616 void Vcmpe(DataType dt, DRegister rd, const DOperand& operand) {
7617 Vcmpe(al, dt, rd, operand);
8290 const DOperand& operand) {
8294 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
8303 vext(cond, dt, rd, rn, rm, operand);
8309 const DOperand& operand) {
8310 Vext(al, dt, rd, rn, rm, operand);
8318 const QOperand& operand) {
8322 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
8331 vext(cond, dt, rd, rn, rm, operand);
8337 const QOperand& operand) {
8338 Vext(al, dt, rd, rn, rm, operand);
8610 const AlignedMemOperand& operand) {
8612 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
8621 vld1(cond, dt, nreglist, operand);
8625 const AlignedMemOperand& operand) {
8626 Vld1(al, dt, nreglist, operand);
8632 const AlignedMemOperand& operand) {
8634 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
8643 vld2(cond, dt, nreglist, operand);
8647 const AlignedMemOperand& operand) {
8648 Vld2(al, dt, nreglist, operand);
8654 const AlignedMemOperand& operand) {
8656 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
8665 vld3(cond, dt, nreglist, operand);
8669 const AlignedMemOperand& operand) {
8670 Vld3(al, dt, nreglist, operand);
8676 const MemOperand& operand) {
8678 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
8687 vld3(cond, dt, nreglist, operand);
8691 const MemOperand& operand) {
8692 Vld3(al, dt, nreglist, operand);
8698 const AlignedMemOperand& operand) {
8700 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
8709 vld4(cond, dt, nreglist, operand);
8713 const AlignedMemOperand& operand) {
8714 Vld4(al, dt, nreglist, operand);
8919 const MemOperand& operand) {
8921 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
8930 vldr(cond, dt, rd, operand);
8932 void Vldr(DataType dt, DRegister rd, const MemOperand& operand) {
8933 Vldr(al, dt, rd, operand);
8935 void Vldr(Condition cond, DRegister rd, const MemOperand& operand) {
8936 Vldr(cond, Untyped64, rd, operand);
8938 void Vldr(DRegister rd, const MemOperand& operand) {
8939 Vldr(al, Untyped64, rd, operand);
8946 const MemOperand& operand) {
8948 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
8957 vldr(cond, dt, rd, operand);
8959 void Vldr(DataType dt, SRegister rd, const MemOperand& operand) {
8960 Vldr(al, dt, rd, operand);
8962 void Vldr(Condition cond, SRegister rd, const MemOperand& operand) {
8963 Vldr(cond, Untyped32, rd, operand);
8965 void Vldr(SRegister rd, const MemOperand& operand) {
8966 Vldr(al, Untyped32, rd, operand);
9517 const DOperand& operand) {
9519 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
9528 vmov(cond, dt, rd, operand);
9530 void Vmov(DataType dt, DRegister rd, const DOperand& operand) {
9531 Vmov(al, dt, rd, operand);
9537 const QOperand& operand) {
9539 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
9548 vmov(cond, dt, rd, operand);
9550 void Vmov(DataType dt, QRegister rd, const QOperand& operand) {
9551 Vmov(al, dt, rd, operand);
9557 const SOperand& operand) {
9559 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
9568 vmov(cond, dt, rd, operand);
9570 void Vmov(DataType dt, SRegister rd, const SOperand& operand) {
9571 Vmov(al, dt, rd, operand);
9810 const DOperand& operand) {
9812 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
9821 vmvn(cond, dt, rd, operand);
9823 void Vmvn(DataType dt, DRegister rd, const DOperand& operand) {
9824 Vmvn(al, dt, rd, operand);
9830 const QOperand& operand) {
9832 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
9841 vmvn(cond, dt, rd, operand);
9843 void Vmvn(DataType dt, QRegister rd, const QOperand& operand) {
9844 Vmvn(al, dt, rd, operand);
10010 const DOperand& operand) {
10013 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10022 vorn(cond, dt, rd, rn, operand);
10024 void Vorn(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
10025 Vorn(al, dt, rd, rn, operand);
10032 const QOperand& operand) {
10035 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10044 vorn(cond, dt, rd, rn, operand);
10046 void Vorn(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
10047 Vorn(al, dt, rd, rn, operand);
10054 const DOperand& operand) {
10057 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10066 vorr(cond, dt, rd, rn, operand);
10068 void Vorr(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
10069 Vorr(al, dt, rd, rn, operand);
10074 const DOperand& operand) {
10075 Vorr(cond, kDataTypeValueNone, rd, rn, operand);
10077 void Vorr(DRegister rd, DRegister rn, const DOperand& operand) {
10078 Vorr(al, kDataTypeValueNone, rd, rn, operand);
10085 const QOperand& operand) {
10088 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10097 vorr(cond, dt, rd, rn, operand);
10099 void Vorr(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
10100 Vorr(al, dt, rd, rn, operand);
10105 const QOperand& operand) {
10106 Vorr(cond, kDataTypeValueNone, rd, rn, operand);
10108 void Vorr(QRegister rd, QRegister rn, const QOperand& operand) {
10109 Vorr(al, kDataTypeValueNone, rd, rn, operand);
10778 const QOperand& operand) {
10781 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10790 vqrshrn(cond, dt, rd, rm, operand);
10795 const QOperand& operand) {
10796 Vqrshrn(al, dt, rd, rm, operand);
10803 const QOperand& operand) {
10806 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10815 vqrshrun(cond, dt, rd, rm, operand);
10820 const QOperand& operand) {
10821 Vqrshrun(al, dt, rd, rm, operand);
10828 const DOperand& operand) {
10831 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10840 vqshl(cond, dt, rd, rm, operand);
10842 void Vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
10843 Vqshl(al, dt, rd, rm, operand);
10850 const QOperand& operand) {
10853 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10862 vqshl(cond, dt, rd, rm, operand);
10864 void Vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
10865 Vqshl(al, dt, rd, rm, operand);
10872 const DOperand& operand) {
10875 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10884 vqshlu(cond, dt, rd, rm, operand);
10889 const DOperand& operand) {
10890 Vqshlu(al, dt, rd, rm, operand);
10897 const QOperand& operand) {
10900 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10909 vqshlu(cond, dt, rd, rm, operand);
10914 const QOperand& operand) {
10915 Vqshlu(al, dt, rd, rm, operand);
10922 const QOperand& operand) {
10925 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10934 vqshrn(cond, dt, rd, rm, operand);
10939 const QOperand& operand) {
10940 Vqshrn(al, dt, rd, rm, operand);
10947 const QOperand& operand) {
10950 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
10959 vqshrun(cond, dt, rd, rm, operand);
10964 const QOperand& operand) {
10965 Vqshrun(al, dt, rd, rm, operand);
11507 const DOperand& operand) {
11510 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11519 vrshr(cond, dt, rd, rm, operand);
11521 void Vrshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
11522 Vrshr(al, dt, rd, rm, operand);
11529 const QOperand& operand) {
11532 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11541 vrshr(cond, dt, rd, rm, operand);
11543 void Vrshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
11544 Vrshr(al, dt, rd, rm, operand);
11551 const QOperand& operand) {
11554 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11563 vrshrn(cond, dt, rd, rm, operand);
11568 const QOperand& operand) {
11569 Vrshrn(al, dt, rd, rm, operand);
11648 const DOperand& operand) {
11651 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11660 vrsra(cond, dt, rd, rm, operand);
11662 void Vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
11663 Vrsra(al, dt, rd, rm, operand);
11670 const QOperand& operand) {
11673 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11682 vrsra(cond, dt, rd, rm, operand);
11684 void Vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
11685 Vrsra(al, dt, rd, rm, operand);
11791 const DOperand& operand) {
11794 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11803 vshl(cond, dt, rd, rm, operand);
11805 void Vshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
11806 Vshl(al, dt, rd, rm, operand);
11813 const QOperand& operand) {
11816 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11825 vshl(cond, dt, rd, rm, operand);
11827 void Vshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
11828 Vshl(al, dt, rd, rm, operand);
11835 const DOperand& operand) {
11838 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11847 vshll(cond, dt, rd, rm, operand);
11849 void Vshll(DataType dt, QRegister rd, DRegister rm, const DOperand& operand) {
11850 Vshll(al, dt, rd, rm, operand);
11857 const DOperand& operand) {
11860 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11869 vshr(cond, dt, rd, rm, operand);
11871 void Vshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
11872 Vshr(al, dt, rd, rm, operand);
11879 const QOperand& operand) {
11882 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11891 vshr(cond, dt, rd, rm, operand);
11893 void Vshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
11894 Vshr(al, dt, rd, rm, operand);
11901 const QOperand& operand) {
11904 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11913 vshrn(cond, dt, rd, rm, operand);
11915 void Vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) {
11916 Vshrn(al, dt, rd, rm, operand);
11923 const DOperand& operand) {
11926 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11935 vsli(cond, dt, rd, rm, operand);
11937 void Vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
11938 Vsli(al, dt, rd, rm, operand);
11945 const QOperand& operand) {
11948 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
11957 vsli(cond, dt, rd, rm, operand);
11959 void Vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
11960 Vsli(al, dt, rd, rm, operand);
11997 const DOperand& operand) {
12000 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
12009 vsra(cond, dt, rd, rm, operand);
12011 void Vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
12012 Vsra(al, dt, rd, rm, operand);
12019 const QOperand& operand) {
12022 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
12031 vsra(cond, dt, rd, rm, operand);
12033 void Vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
12034 Vsra(al, dt, rd, rm, operand);
12041 const DOperand& operand) {
12044 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
12053 vsri(cond, dt, rd, rm, operand);
12055 void Vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
12056 Vsri(al, dt, rd, rm, operand);
12063 const QOperand& operand) {
12066 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
12075 vsri(cond, dt, rd, rm, operand);
12077 void Vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
12078 Vsri(al, dt, rd, rm, operand);
12084 const AlignedMemOperand& operand) {
12086 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
12095 vst1(cond, dt, nreglist, operand);
12099 const AlignedMemOperand& operand) {
12100 Vst1(al, dt, nreglist, operand);
12106 const AlignedMemOperand& operand) {
12108 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
12117 vst2(cond, dt, nreglist, operand);
12121 const AlignedMemOperand& operand) {
12122 Vst2(al, dt, nreglist, operand);
12128 const AlignedMemOperand& operand) {
12130 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
12139 vst3(cond, dt, nreglist, operand);
12143 const AlignedMemOperand& operand) {
12144 Vst3(al, dt, nreglist, operand);
12150 const MemOperand& operand) {
12152 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
12161 vst3(cond, dt, nreglist, operand);
12165 const MemOperand& operand) {
12166 Vst3(al, dt, nreglist, operand);
12172 const AlignedMemOperand& operand) {
12174 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
12183 vst4(cond, dt, nreglist, operand);
12187 const AlignedMemOperand& operand) {
12188 Vst4(al, dt, nreglist, operand);
12392 const MemOperand& operand) {
12394 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
12403 vstr(cond, dt, rd, operand);
12405 void Vstr(DataType dt, DRegister rd, const MemOperand& operand) {
12406 Vstr(al, dt, rd, operand);
12408 void Vstr(Condition cond, DRegister rd, const MemOperand& operand) {
12409 Vstr(cond, Untyped64, rd, operand);
12411 void Vstr(DRegister rd, const MemOperand& operand) {
12412 Vstr(al, Untyped64, rd, operand);
12418 const MemOperand& operand) {
12420 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand));
12429 vstr(cond, dt, rd, operand);
12431 void Vstr(DataType dt, SRegister rd, const MemOperand& operand) {
12432 Vstr(al, dt, rd, operand);
12434 void Vstr(Condition cond, SRegister rd, const MemOperand& operand) {
12435 Vstr(cond, Untyped32, rd, operand);
12437 void Vstr(SRegister rd, const MemOperand& operand) {
12438 Vstr(al, Untyped32, rd, operand);
13461 // A convenience helper to exclude any registers used by the operand.
13462 void Exclude(const Operand& operand);