Lines Matching refs:rd
632 void Adr(Condition cond, Register rd, RawLiteral* literal) {
633 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
640 bool can_encode = adr_info(cond, Best, rd, literal, &info);
652 adr(cond, Best, rd, literal);
655 void Adr(Register rd, RawLiteral* literal) { Adr(al, rd, literal); }
812 void Vldr(Condition cond, DataType dt, DRegister rd, RawLiteral* literal) {
813 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
820 bool can_encode = vldr_info(cond, dt, rd, literal, &info);
832 vldr(cond, dt, rd, literal);
835 void Vldr(DataType dt, DRegister rd, RawLiteral* literal) {
836 Vldr(al, dt, rd, literal);
838 void Vldr(Condition cond, DRegister rd, RawLiteral* literal) {
839 Vldr(cond, Untyped64, rd, literal);
841 void Vldr(DRegister rd, RawLiteral* literal) {
842 Vldr(al, Untyped64, rd, literal);
845 void Vldr(Condition cond, DataType dt, SRegister rd, RawLiteral* literal) {
846 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
853 bool can_encode = vldr_info(cond, dt, rd, literal, &info);
865 vldr(cond, dt, rd, literal);
868 void Vldr(DataType dt, SRegister rd, RawLiteral* literal) {
869 Vldr(al, dt, rd, literal);
871 void Vldr(Condition cond, SRegister rd, RawLiteral* literal) {
872 Vldr(cond, Untyped32, rd, literal);
874 void Vldr(SRegister rd, RawLiteral* literal) {
875 Vldr(al, Untyped32, rd, literal);
917 void Vldr(Condition cond, SRegister rd, float v) {
918 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
928 Vldr(cond, rd, literal);
930 void Vldr(SRegister rd, float v) { Vldr(al, rd, v); }
932 void Vldr(Condition cond, DRegister rd, double v) {
933 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
943 Vldr(cond, rd, literal);
945 void Vldr(DRegister rd, double v) { Vldr(al, rd, v); }
1015 Register rd,
1024 Register rd,
1028 Register rd,
1036 Register rd,
1049 SRegister rd,
1056 DRegister rd,
1063 QRegister rd,
1070 Register rd,
1095 SRegister rd,
1102 DRegister rd,
1114 DRegister rd,
1120 SRegister rd,
1125 void Adc(Condition cond, Register rd, Register rn, const Operand& operand) {
1126 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1134 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) &&
1141 adc(cond, rd, rn, operand);
1143 void Adc(Register rd, Register rn, const Operand& operand) {
1144 Adc(al, rd, rn, operand);
1148 Register rd,
1153 Adc(cond, rd, rn, operand);
1156 Adcs(cond, rd, rn, operand);
1159 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1160 rn.Is(rd) && operand.IsPlainRegister() &&
1163 Adcs(cond, rd, rn, operand);
1165 Adc(cond, rd, rn, operand);
1171 Register rd,
1174 Adc(flags, al, rd, rn, operand);
1177 void Adcs(Condition cond, Register rd, Register rn, const Operand& operand) {
1178 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1189 adcs(cond, rd, rn, operand);
1191 void Adcs(Register rd, Register rn, const Operand& operand) {
1192 Adcs(al, rd, rn, operand);
1195 void Add(Condition cond, Register rd, Register rn, const Operand& operand) {
1196 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1202 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
1211 rd.IsLow()) ||
1214 rd.IsLow() && rn.Is(rd)) ||
1217 ((operand.GetImmediate() & 0x3) == 0) && rd.IsLow() && rn.IsSP()) ||
1219 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
1222 (operand.IsPlainRegister() && !rd.IsPC() && rn.Is(rd) &&
1226 (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() &&
1227 operand.GetBaseRegister().Is(rd));
1233 add(cond, rd, rn, operand);
1235 void Add(Register rd, Register rn, const Operand& operand) {
1236 Add(al, rd, rn, operand);
1240 Register rd,
1245 Add(cond, rd, rn, operand);
1248 Adds(cond, rd, rn, operand);
1253 ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
1254 !rd.Is(rn) && operand.GetBaseRegister().IsLow()) ||
1256 ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) ||
1257 (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256)))));
1259 Adds(cond, rd, rn, operand);
1263 ((rd.IsLow() && rn.IsLow() &&
1265 (rd.IsLow() && rn.Is(rd) &&
1268 Subs(cond, rd, rn, -operand.GetSignedImmediate());
1270 Add(cond, rd, rn, operand);
1277 Register rd,
1280 Add(flags, al, rd, rn, operand);
1283 void Adds(Condition cond, Register rd, Register rn, const Operand& operand) {
1284 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1295 adds(cond, rd, rn, operand);
1297 void Adds(Register rd, Register rn, const Operand& operand) {
1298 Adds(al, rd, rn, operand);
1301 void And(Condition cond, Register rd, Register rn, const Operand& operand) {
1302 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1308 if (rd.Is(rn) && operand.IsPlainRegister() &&
1309 rd.Is(operand.GetBaseRegister())) {
1315 mov(rd, 0);
1318 if ((immediate == 0xffffffff) && rd.Is(rn)) {
1324 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1331 and_(cond, rd, rn, operand);
1333 void And(Register rd, Register rn, const Operand& operand) {
1334 And(al, rd, rn, operand);
1338 Register rd,
1343 And(cond, rd, rn, operand);
1346 Ands(cond, rd, rn, operand);
1349 if (operand.IsPlainRegister() && rd.Is(rn) &&
1350 rd.Is(operand.GetBaseRegister())) {
1353 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1354 rn.Is(rd) && operand.IsPlainRegister() &&
1357 Ands(cond, rd, rn, operand);
1359 And(cond, rd, rn, operand);
1365 Register rd,
1368 And(flags, al, rd, rn, operand);
1371 void Ands(Condition cond, Register rd, Register rn, const Operand& operand) {
1372 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1383 ands(cond, rd, rn, operand);
1385 void Ands(Register rd, Register rn, const Operand& operand) {
1386 Ands(al, rd, rn, operand);
1389 void Asr(Condition cond, Register rd, Register rm, const Operand& operand) {
1390 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1399 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) ||
1401 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
1408 asr(cond, rd, rm, operand);
1410 void Asr(Register rd, Register rm, const Operand& operand) {
1411 Asr(al, rd, rm, operand);
1415 Register rd,
1420 Asr(cond, rd, rm, operand);
1423 Asrs(cond, rd, rm, operand);
1427 IsUsingT32() && cond.Is(al) && rd.IsLow() && rm.IsLow() &&
1430 (operand.IsPlainRegister() && rd.Is(rm)));
1432 Asrs(cond, rd, rm, operand);
1434 Asr(cond, rd, rm, operand);
1440 Register rd,
1443 Asr(flags, al, rd, rm, operand);
1446 void Asrs(Condition cond, Register rd, Register rm, const Operand& operand) {
1447 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1458 asrs(cond, rd, rm, operand);
1460 void Asrs(Register rd, Register rm, const Operand& operand) {
1461 Asrs(al, rd, rm, operand);
1489 void Bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width) {
1490 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1499 bfc(cond, rd, lsb, width);
1501 void Bfc(Register rd, uint32_t lsb, uint32_t width) {
1502 Bfc(al, rd, lsb, width);
1506 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
1507 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1517 bfi(cond, rd, rn, lsb, width);
1519 void Bfi(Register rd, Register rn, uint32_t lsb, uint32_t width) {
1520 Bfi(al, rd, rn, lsb, width);
1523 void Bic(Condition cond, Register rd, Register rn, const Operand& operand) {
1524 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1532 if ((immediate == 0) && rd.Is(rn)) {
1536 mov(rd, 0);
1542 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1549 bic(cond, rd, rn, operand);
1551 void Bic(Register rd, Register rn, const Operand& operand) {
1552 Bic(al, rd, rn, operand);
1556 Register rd,
1561 Bic(cond, rd, rn, operand);
1564 Bics(cond, rd, rn, operand);
1567 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1568 rn.Is(rd) && operand.IsPlainRegister() &&
1571 Bics(cond, rd, rn, operand);
1573 Bic(cond, rd, rn, operand);
1579 Register rd,
1582 Bic(flags, al, rd, rn, operand);
1585 void Bics(Condition cond, Register rd, Register rn, const Operand& operand) {
1586 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1597 bics(cond, rd, rn, operand);
1599 void Bics(Register rd, Register rn, const Operand& operand) {
1600 Bics(al, rd, rn, operand);
1763 void Clz(Condition cond, Register rd, Register rm) {
1764 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1774 clz(cond, rd, rm);
1776 void Clz(Register rd, Register rm) { Clz(al, rd, rm); }
1819 void Crc32b(Condition cond, Register rd, Register rn, Register rm) {
1820 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1831 crc32b(cond, rd, rn, rm);
1833 void Crc32b(Register rd, Register rn, Register rm) { Crc32b(al, rd, rn, rm); }
1835 void Crc32cb(Condition cond, Register rd, Register rn, Register rm) {
1836 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1847 crc32cb(cond, rd, rn, rm);
1849 void Crc32cb(Register rd, Register rn, Register rm) {
1850 Crc32cb(al, rd, rn, rm);
1853 void Crc32ch(Condition cond, Register rd, Register rn, Register rm) {
1854 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1865 crc32ch(cond, rd, rn, rm);
1867 void Crc32ch(Register rd, Register rn, Register rm) {
1868 Crc32ch(al, rd, rn, rm);
1871 void Crc32cw(Condition cond, Register rd, Register rn, Register rm) {
1872 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1883 crc32cw(cond, rd, rn, rm);
1885 void Crc32cw(Register rd, Register rn, Register rm) {
1886 Crc32cw(al, rd, rn, rm);
1889 void Crc32h(Condition cond, Register rd, Register rn, Register rm) {
1890 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1901 crc32h(cond, rd, rn, rm);
1903 void Crc32h(Register rd, Register rn, Register rm) { Crc32h(al, rd, rn, rm); }
1905 void Crc32w(Condition cond, Register rd, Register rn, Register rm) {
1906 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1917 crc32w(cond, rd, rn, rm);
1919 void Crc32w(Register rd, Register rn, Register rm) { Crc32w(al, rd, rn, rm); }
1947 void Eor(Condition cond, Register rd, Register rn, const Operand& operand) {
1948 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
1954 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
1960 mvn(rd, rn);
1966 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
1973 eor(cond, rd, rn, operand);
1975 void Eor(Register rd, Register rn, const Operand& operand) {
1976 Eor(al, rd, rn, operand);
1980 Register rd,
1985 Eor(cond, rd, rn, operand);
1988 Eors(cond, rd, rn, operand);
1991 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
1992 rn.Is(rd) && operand.IsPlainRegister() &&
1995 Eors(cond, rd, rn, operand);
1997 Eor(cond, rd, rn, operand);
2003 Register rd,
2006 Eor(flags, al, rd, rn, operand);
2009 void Eors(Condition cond, Register rd, Register rn, const Operand& operand) {
2010 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2021 eors(cond, rd, rn, operand);
2023 void Eors(Register rd, Register rn, const Operand& operand) {
2024 Eors(al, rd, rn, operand);
2643 void Lsl(Condition cond, Register rd, Register rm, const Operand& operand) {
2644 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2653 (operand.GetImmediate() <= 31) && rd.IsLow() && rm.IsLow()) ||
2655 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
2662 lsl(cond, rd, rm, operand);
2664 void Lsl(Register rd, Register rm, const Operand& operand) {
2665 Lsl(al, rd, rm, operand);
2669 Register rd,
2674 Lsl(cond, rd, rm, operand);
2677 Lsls(cond, rd, rm, operand);
2681 IsUsingT32() && cond.Is(al) && rd.IsLow() && rm.IsLow() &&
2684 (operand.IsPlainRegister() && rd.Is(rm)));
2686 Lsls(cond, rd, rm, operand);
2688 Lsl(cond, rd, rm, operand);
2694 Register rd,
2697 Lsl(flags, al, rd, rm, operand);
2700 void Lsls(Condition cond, Register rd, Register rm, const Operand& operand) {
2701 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2712 lsls(cond, rd, rm, operand);
2714 void Lsls(Register rd, Register rm, const Operand& operand) {
2715 Lsls(al, rd, rm, operand);
2718 void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) {
2719 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2728 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) ||
2730 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
2737 lsr(cond, rd, rm, operand);
2739 void Lsr(Register rd, Register rm, const Operand& operand) {
2740 Lsr(al, rd, rm, operand);
2744 Register rd,
2749 Lsr(cond, rd, rm, operand);
2752 Lsrs(cond, rd, rm, operand);
2756 IsUsingT32() && cond.Is(al) && rd.IsLow() && rm.IsLow() &&
2759 (operand.IsPlainRegister() && rd.Is(rm)));
2761 Lsrs(cond, rd, rm, operand);
2763 Lsr(cond, rd, rm, operand);
2769 Register rd,
2772 Lsr(flags, al, rd, rm, operand);
2775 void Lsrs(Condition cond, Register rd, Register rm, const Operand& operand) {
2776 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2787 lsrs(cond, rd, rm, operand);
2789 void Lsrs(Register rd, Register rm, const Operand& operand) {
2790 Lsrs(al, rd, rm, operand);
2793 void Mla(Condition cond, Register rd, Register rn, Register rm, Register ra) {
2794 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2806 mla(cond, rd, rn, rm, ra);
2808 void Mla(Register rd, Register rn, Register rm, Register ra) {
2809 Mla(al, rd, rn, rm, ra);
2813 Register rd,
2819 Mla(cond, rd, rn, rm, ra);
2822 Mlas(cond, rd, rn, rm, ra);
2825 Mla(cond, rd, rn, rm, ra);
2830 FlagsUpdate flags, Register rd, Register rn, Register rm, Register ra) {
2831 Mla(flags, al, rd, rn, rm, ra);
2835 Condition cond, Register rd, Register rn, Register rm, Register ra) {
2836 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2848 mlas(cond, rd, rn, rm, ra);
2850 void Mlas(Register rd, Register rn, Register rm, Register ra) {
2851 Mlas(al, rd, rn, rm, ra);
2854 void Mls(Condition cond, Register rd, Register rn, Register rm, Register ra) {
2855 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2867 mls(cond, rd, rn, rm, ra);
2869 void Mls(Register rd, Register rn, Register rm, Register ra) {
2870 Mls(al, rd, rn, rm, ra);
2873 void Mov(Condition cond, Register rd, const Operand& operand) {
2874 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2879 if (operand.IsPlainRegister() && rd.Is(operand.GetBaseRegister())) {
2884 (operand.IsImmediate() && rd.IsLow() &&
2887 (operand.IsPlainRegister() && !rd.IsPC() &&
2890 (operand.IsImmediateShiftedRegister() && rd.IsLow() &&
2899 rd.Is(operand.GetBaseRegister()) && rd.IsLow() &&
2908 mov(cond, rd, operand);
2910 void Mov(Register rd, const Operand& operand) { Mov(al, rd, operand); }
2913 Register rd,
2917 Mov(cond, rd, operand);
2920 Movs(cond, rd, operand);
2923 if (operand.IsPlainRegister() && rd.Is(operand.GetBaseRegister())) {
2928 ((operand.IsImmediateShiftedRegister() && rd.IsLow() &&
2935 (operand.IsRegisterShiftedRegister() && rd.IsLow() &&
2936 operand.GetBaseRegister().Is(rd) &&
2940 (operand.IsImmediate() && rd.IsLow() &&
2943 Movs(cond, rd, operand);
2945 Mov(cond, rd, operand);
2950 void Mov(FlagsUpdate flags, Register rd, const Operand& operand) {
2951 Mov(flags, al, rd, operand);
2954 void Movs(Condition cond, Register rd, const Operand& operand) {
2955 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2965 movs(cond, rd, operand);
2967 void Movs(Register rd, const Operand& operand) { Movs(al, rd, operand); }
2969 void Movt(Condition cond, Register rd, const Operand& operand) {
2970 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2980 movt(cond, rd, operand);
2982 void Movt(Register rd, const Operand& operand) { Movt(al, rd, operand); }
2984 void Mrs(Condition cond, Register rd, SpecialRegister spec_reg) {
2985 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
2994 mrs(cond, rd, spec_reg);
2996 void Mrs(Register rd, SpecialRegister spec_reg) { Mrs(al, rd, spec_reg); }
3016 void Mul(Condition cond, Register rd, Register rn, Register rm) {
3017 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3025 rd.Is(rm) && rn.IsLow() && rm.IsLow();
3031 mul(cond, rd, rn, rm);
3033 void Mul(Register rd, Register rn, Register rm) { Mul(al, rd, rn, rm); }
3036 Register rd,
3041 Mul(cond, rd, rn, rm);
3044 Muls(cond, rd, rn, rm);
3047 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
3048 rn.IsLow() && rm.Is(rd);
3050 Muls(cond, rd, rn, rm);
3052 Mul(cond, rd, rn, rm);
3057 void Mul(FlagsUpdate flags, Register rd, Register rn, Register rm) {
3058 Mul(flags, al, rd, rn, rm);
3061 void Muls(Condition cond, Register rd, Register rn, Register rm) {
3062 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3073 muls(cond, rd, rn, rm);
3075 void Muls(Register rd, Register rn, Register rm) { Muls(al, rd, rn, rm); }
3077 void Mvn(Condition cond, Register rd, const Operand& operand) {
3078 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3085 operand.IsPlainRegister() && rd.IsLow() &&
3092 mvn(cond, rd, operand);
3094 void Mvn(Register rd, const Operand& operand) { Mvn(al, rd, operand); }
3097 Register rd,
3101 Mvn(cond, rd, operand);
3104 Mvns(cond, rd, operand);
3107 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
3111 Mvns(cond, rd, operand);
3113 Mvn(cond, rd, operand);
3118 void Mvn(FlagsUpdate flags, Register rd, const Operand& operand) {
3119 Mvn(flags, al, rd, operand);
3122 void Mvns(Condition cond, Register rd, const Operand& operand) {
3123 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3133 mvns(cond, rd, operand);
3135 void Mvns(Register rd, const Operand& operand) { Mvns(al, rd, operand); }
3150 void Orn(Condition cond, Register rd, Register rn, const Operand& operand) {
3151 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3160 mvn(rd, 0);
3163 if ((immediate == 0xffffffff) && rd.Is(rn)) {
3172 orn(cond, rd, rn, operand);
3174 void Orn(Register rd, Register rn, const Operand& operand) {
3175 Orn(al, rd, rn, operand);
3179 Register rd,
3184 Orn(cond, rd, rn, operand);
3187 Orns(cond, rd, rn, operand);
3190 Orn(cond, rd, rn, operand);
3195 Register rd,
3198 Orn(flags, al, rd, rn, operand);
3201 void Orns(Condition cond, Register rd, Register rn, const Operand& operand) {
3202 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3213 orns(cond, rd, rn, operand);
3215 void Orns(Register rd, Register rn, const Operand& operand) {
3216 Orns(al, rd, rn, operand);
3219 void Orr(Condition cond, Register rd, Register rn, const Operand& operand) {
3220 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3226 if (rd.Is(rn) && operand.IsPlainRegister() &&
3227 rd.Is(operand.GetBaseRegister())) {
3232 if ((immediate == 0) && rd.Is(rn)) {
3236 mvn(rd, 0);
3242 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() &&
3249 orr(cond, rd, rn, operand);
3251 void Orr(Register rd, Register rn, const Operand& operand) {
3252 Orr(al, rd, rn, operand);
3256 Register rd,
3261 Orr(cond, rd, rn, operand);
3264 Orrs(cond, rd, rn, operand);
3267 if (operand.IsPlainRegister() && rd.Is(rn) &&
3268 rd.Is(operand.GetBaseRegister())) {
3271 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
3272 rn.Is(rd) && operand.IsPlainRegister() &&
3275 Orrs(cond, rd, rn, operand);
3277 Orr(cond, rd, rn, operand);
3283 Register rd,
3286 Orr(flags, al, rd, rn, operand);
3289 void Orrs(Condition cond, Register rd, Register rn, const Operand& operand) {
3290 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3301 orrs(cond, rd, rn, operand);
3303 void Orrs(Register rd, Register rn, const Operand& operand) {
3304 Orrs(al, rd, rn, operand);
3307 void Pkhbt(Condition cond, Register rd, Register rn, const Operand& operand) {
3308 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3319 pkhbt(cond, rd, rn, operand);
3321 void Pkhbt(Register rd, Register rn, const Operand& operand) {
3322 Pkhbt(al, rd, rn, operand);
3325 void Pkhtb(Condition cond, Register rd, Register rn, const Operand& operand) {
3326 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3337 pkhtb(cond, rd, rn, operand);
3339 void Pkhtb(Register rd, Register rn, const Operand& operand) {
3340 Pkhtb(al, rd, rn, operand);
3458 void Qadd(Condition cond, Register rd, Register rm, Register rn) {
3459 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3470 qadd(cond, rd, rm, rn);
3472 void Qadd(Register rd, Register rm, Register rn) { Qadd(al, rd, rm, rn); }
3474 void Qadd16(Condition cond, Register rd, Register rn, Register rm) {
3475 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3486 qadd16(cond, rd, rn, rm);
3488 void Qadd16(Register rd, Register rn, Register rm) { Qadd16(al, rd, rn, rm); }
3490 void Qadd8(Condition cond, Register rd, Register rn, Register rm) {
3491 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3502 qadd8(cond, rd, rn, rm);
3504 void Qadd8(Register rd, Register rn, Register rm) { Qadd8(al, rd, rn, rm); }
3506 void Qasx(Condition cond, Register rd, Register rn, Register rm) {
3507 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3518 qasx(cond, rd, rn, rm);
3520 void Qasx(Register rd, Register rn, Register rm) { Qasx(al, rd, rn, rm); }
3522 void Qdadd(Condition cond, Register rd, Register rm, Register rn) {
3523 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3534 qdadd(cond, rd, rm, rn);
3536 void Qdadd(Register rd, Register rm, Register rn) { Qdadd(al, rd, rm, rn); }
3538 void Qdsub(Condition cond, Register rd, Register rm, Register rn) {
3539 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3550 qdsub(cond, rd, rm, rn);
3552 void Qdsub(Register rd, Register rm, Register rn) { Qdsub(al, rd, rm, rn); }
3554 void Qsax(Condition cond, Register rd, Register rn, Register rm) {
3555 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3566 qsax(cond, rd, rn, rm);
3568 void Qsax(Register rd, Register rn, Register rm) { Qsax(al, rd, rn, rm); }
3570 void Qsub(Condition cond, Register rd, Register rm, Register rn) {
3571 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3582 qsub(cond, rd, rm, rn);
3584 void Qsub(Register rd, Register rm, Register rn) { Qsub(al, rd, rm, rn); }
3586 void Qsub16(Condition cond, Register rd, Register rn, Register rm) {
3587 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3598 qsub16(cond, rd, rn, rm);
3600 void Qsub16(Register rd, Register rn, Register rm) { Qsub16(al, rd, rn, rm); }
3602 void Qsub8(Condition cond, Register rd, Register rn, Register rm) {
3603 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3614 qsub8(cond, rd, rn, rm);
3616 void Qsub8(Register rd, Register rn, Register rm) { Qsub8(al, rd, rn, rm); }
3618 void Rbit(Condition cond, Register rd, Register rm) {
3619 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3629 rbit(cond, rd, rm);
3631 void Rbit(Register rd, Register rm) { Rbit(al, rd, rm); }
3633 void Rev(Condition cond, Register rd, Register rm) {
3634 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3644 rev(cond, rd, rm);
3646 void Rev(Register rd, Register rm) { Rev(al, rd, rm); }
3648 void Rev16(Condition cond, Register rd, Register rm) {
3649 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3659 rev16(cond, rd, rm);
3661 void Rev16(Register rd, Register rm) { Rev16(al, rd, rm); }
3663 void Revsh(Condition cond, Register rd, Register rm) {
3664 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3674 revsh(cond, rd, rm);
3676 void Revsh(Register rd, Register rm) { Revsh(al, rd, rm); }
3678 void Ror(Condition cond, Register rd, Register rm, const Operand& operand) {
3679 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3687 operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() &&
3694 ror(cond, rd, rm, operand);
3696 void Ror(Register rd, Register rm, const Operand& operand) {
3697 Ror(al, rd, rm, operand);
3701 Register rd,
3706 Ror(cond, rd, rm, operand);
3709 Rors(cond, rd, rm, operand);
3712 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
3714 rd.Is(rm);
3716 Rors(cond, rd, rm, operand);
3718 Ror(cond, rd, rm, operand);
3724 Register rd,
3727 Ror(flags, al, rd, rm, operand);
3730 void Rors(Condition cond, Register rd, Register rm, const Operand& operand) {
3731 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3742 rors(cond, rd, rm, operand);
3744 void Rors(Register rd, Register rm, const Operand& operand) {
3745 Rors(al, rd, rm, operand);
3748 void Rrx(Condition cond, Register rd, Register rm) {
3749 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3759 rrx(cond, rd, rm);
3761 void Rrx(Register rd, Register rm) { Rrx(al, rd, rm); }
3762 void Rrx(FlagsUpdate flags, Condition cond, Register rd, Register rm) {
3765 Rrx(cond, rd, rm);
3768 Rrxs(cond, rd, rm);
3771 Rrx(cond, rd, rm);
3775 void Rrx(FlagsUpdate flags, Register rd, Register rm) {
3776 Rrx(flags, al, rd, rm);
3779 void Rrxs(Condition cond, Register rd, Register rm) {
3780 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3790 rrxs(cond, rd, rm);
3792 void Rrxs(Register rd, Register rm) { Rrxs(al, rd, rm); }
3794 void Rsb(Condition cond, Register rd, Register rn, const Operand& operand) {
3795 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3803 operand.IsImmediate() && rd.IsLow() && rn.IsLow() &&
3810 rsb(cond, rd, rn, operand);
3812 void Rsb(Register rd, Register rn, const Operand& operand) {
3813 Rsb(al, rd, rn, operand);
3817 Register rd,
3822 Rsb(cond, rd, rn, operand);
3825 Rsbs(cond, rd, rn, operand);
3828 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
3832 Rsbs(cond, rd, rn, operand);
3834 Rsb(cond, rd, rn, operand);
3840 Register rd,
3843 Rsb(flags, al, rd, rn, operand);
3846 void Rsbs(Condition cond, Register rd, Register rn, const Operand& operand) {
3847 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3858 rsbs(cond, rd, rn, operand);
3860 void Rsbs(Register rd, Register rn, const Operand& operand) {
3861 Rsbs(al, rd, rn, operand);
3864 void Rsc(Condition cond, Register rd, Register rn, const Operand& operand) {
3865 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3876 rsc(cond, rd, rn, operand);
3878 void Rsc(Register rd, Register rn, const Operand& operand) {
3879 Rsc(al, rd, rn, operand);
3883 Register rd,
3888 Rsc(cond, rd, rn, operand);
3891 Rscs(cond, rd, rn, operand);
3894 Rsc(cond, rd, rn, operand);
3899 Register rd,
3902 Rsc(flags, al, rd, rn, operand);
3905 void Rscs(Condition cond, Register rd, Register rn, const Operand& operand) {
3906 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3917 rscs(cond, rd, rn, operand);
3919 void Rscs(Register rd, Register rn, const Operand& operand) {
3920 Rscs(al, rd, rn, operand);
3923 void Sadd16(Condition cond, Register rd, Register rn, Register rm) {
3924 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3935 sadd16(cond, rd, rn, rm);
3937 void Sadd16(Register rd, Register rn, Register rm) { Sadd16(al, rd, rn, rm); }
3939 void Sadd8(Condition cond, Register rd, Register rn, Register rm) {
3940 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3951 sadd8(cond, rd, rn, rm);
3953 void Sadd8(Register rd, Register rn, Register rm) { Sadd8(al, rd, rn, rm); }
3955 void Sasx(Condition cond, Register rd, Register rn, Register rm) {
3956 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3967 sasx(cond, rd, rn, rm);
3969 void Sasx(Register rd, Register rn, Register rm) { Sasx(al, rd, rn, rm); }
3971 void Sbc(Condition cond, Register rd, Register rn, const Operand& operand) {
3972 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
3980 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) &&
3987 sbc(cond, rd, rn, operand);
3989 void Sbc(Register rd, Register rn, const Operand& operand) {
3990 Sbc(al, rd, rn, operand);
3994 Register rd,
3999 Sbc(cond, rd, rn, operand);
4002 Sbcs(cond, rd, rn, operand);
4005 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() &&
4006 rn.Is(rd) && operand.IsPlainRegister() &&
4009 Sbcs(cond, rd, rn, operand);
4011 Sbc(cond, rd, rn, operand);
4017 Register rd,
4020 Sbc(flags, al, rd, rn, operand);
4023 void Sbcs(Condition cond, Register rd, Register rn, const Operand& operand) {
4024 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4035 sbcs(cond, rd, rn, operand);
4037 void Sbcs(Register rd, Register rn, const Operand& operand) {
4038 Sbcs(al, rd, rn, operand);
4042 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
4043 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4053 sbfx(cond, rd, rn, lsb, width);
4055 void Sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width) {
4056 Sbfx(al, rd, rn, lsb, width);
4059 void Sdiv(Condition cond, Register rd, Register rn, Register rm) {
4060 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4071 sdiv(cond, rd, rn, rm);
4073 void Sdiv(Register rd, Register rn, Register rm) { Sdiv(al, rd, rn, rm); }
4075 void Sel(Condition cond, Register rd, Register rn, Register rm) {
4076 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4087 sel(cond, rd, rn, rm);
4089 void Sel(Register rd, Register rn, Register rm) { Sel(al, rd, rn, rm); }
4091 void Shadd16(Condition cond, Register rd, Register rn, Register rm) {
4092 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4103 shadd16(cond, rd, rn, rm);
4105 void Shadd16(Register rd, Register rn, Register rm) {
4106 Shadd16(al, rd, rn, rm);
4109 void Shadd8(Condition cond, Register rd, Register rn, Register rm) {
4110 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4121 shadd8(cond, rd, rn, rm);
4123 void Shadd8(Register rd, Register rn, Register rm) { Shadd8(al, rd, rn, rm); }
4125 void Shasx(Condition cond, Register rd, Register rn, Register rm) {
4126 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4137 shasx(cond, rd, rn, rm);
4139 void Shasx(Register rd, Register rn, Register rm) { Shasx(al, rd, rn, rm); }
4141 void Shsax(Condition cond, Register rd, Register rn, Register rm) {
4142 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4153 shsax(cond, rd, rn, rm);
4155 void Shsax(Register rd, Register rn, Register rm) { Shsax(al, rd, rn, rm); }
4157 void Shsub16(Condition cond, Register rd, Register rn, Register rm) {
4158 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4169 shsub16(cond, rd, rn, rm);
4171 void Shsub16(Register rd, Register rn, Register rm) {
4172 Shsub16(al, rd, rn, rm);
4175 void Shsub8(Condition cond, Register rd, Register rn, Register rm) {
4176 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4187 shsub8(cond, rd, rn, rm);
4189 void Shsub8(Register rd, Register rn, Register rm) { Shsub8(al, rd, rn, rm); }
4192 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4193 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4205 smlabb(cond, rd, rn, rm, ra);
4207 void Smlabb(Register rd, Register rn, Register rm, Register ra) {
4208 Smlabb(al, rd, rn, rm, ra);
4212 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4213 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4225 smlabt(cond, rd, rn, rm, ra);
4227 void Smlabt(Register rd, Register rn, Register rm, Register ra) {
4228 Smlabt(al, rd, rn, rm, ra);
4232 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4233 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4245 smlad(cond, rd, rn, rm, ra);
4247 void Smlad(Register rd, Register rn, Register rm, Register ra) {
4248 Smlad(al, rd, rn, rm, ra);
4252 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4253 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4265 smladx(cond, rd, rn, rm, ra);
4267 void Smladx(Register rd, Register rn, Register rm, Register ra) {
4268 Smladx(al, rd, rn, rm, ra);
4432 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4433 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4445 smlatb(cond, rd, rn, rm, ra);
4447 void Smlatb(Register rd, Register rn, Register rm, Register ra) {
4448 Smlatb(al, rd, rn, rm, ra);
4452 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4453 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4465 smlatt(cond, rd, rn, rm, ra);
4467 void Smlatt(Register rd, Register rn, Register rm, Register ra) {
4468 Smlatt(al, rd, rn, rm, ra);
4472 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4473 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4485 smlawb(cond, rd, rn, rm, ra);
4487 void Smlawb(Register rd, Register rn, Register rm, Register ra) {
4488 Smlawb(al, rd, rn, rm, ra);
4492 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4493 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4505 smlawt(cond, rd, rn, rm, ra);
4507 void Smlawt(Register rd, Register rn, Register rm, Register ra) {
4508 Smlawt(al, rd, rn, rm, ra);
4512 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4513 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4525 smlsd(cond, rd, rn, rm, ra);
4527 void Smlsd(Register rd, Register rn, Register rm, Register ra) {
4528 Smlsd(al, rd, rn, rm, ra);
4532 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4533 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4545 smlsdx(cond, rd, rn, rm, ra);
4547 void Smlsdx(Register rd, Register rn, Register rm, Register ra) {
4548 Smlsdx(al, rd, rn, rm, ra);
4592 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4593 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4605 smmla(cond, rd, rn, rm, ra);
4607 void Smmla(Register rd, Register rn, Register rm, Register ra) {
4608 Smmla(al, rd, rn, rm, ra);
4612 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4613 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4625 smmlar(cond, rd, rn, rm, ra);
4627 void Smmlar(Register rd, Register rn, Register rm, Register ra) {
4628 Smmlar(al, rd, rn, rm, ra);
4632 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4633 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4645 smmls(cond, rd, rn, rm, ra);
4647 void Smmls(Register rd, Register rn, Register rm, Register ra) {
4648 Smmls(al, rd, rn, rm, ra);
4652 Condition cond, Register rd, Register rn, Register rm, Register ra) {
4653 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4665 smmlsr(cond, rd, rn, rm, ra);
4667 void Smmlsr(Register rd, Register rn, Register rm, Register ra) {
4668 Smmlsr(al, rd, rn, rm, ra);
4671 void Smmul(Condition cond, Register rd, Register rn, Register rm) {
4672 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4683 smmul(cond, rd, rn, rm);
4685 void Smmul(Register rd, Register rn, Register rm) { Smmul(al, rd, rn, rm); }
4687 void Smmulr(Condition cond, Register rd, Register rn, Register rm) {
4688 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4699 smmulr(cond, rd, rn, rm);
4701 void Smmulr(Register rd, Register rn, Register rm) { Smmulr(al, rd, rn, rm); }
4703 void Smuad(Condition cond, Register rd, Register rn, Register rm) {
4704 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4715 smuad(cond, rd, rn, rm);
4717 void Smuad(Register rd, Register rn, Register rm) { Smuad(al, rd, rn, rm); }
4719 void Smuadx(Condition cond, Register rd, Register rn, Register rm) {
4720 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4731 smuadx(cond, rd, rn, rm);
4733 void Smuadx(Register rd, Register rn, Register rm) { Smuadx(al, rd, rn, rm); }
4735 void Smulbb(Condition cond, Register rd, Register rn, Register rm) {
4736 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4747 smulbb(cond, rd, rn, rm);
4749 void Smulbb(Register rd, Register rn, Register rm) { Smulbb(al, rd, rn, rm); }
4751 void Smulbt(Condition cond, Register rd, Register rn, Register rm) {
4752 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4763 smulbt(cond, rd, rn, rm);
4765 void Smulbt(Register rd, Register rn, Register rm) { Smulbt(al, rd, rn, rm); }
4832 void Smultb(Condition cond, Register rd, Register rn, Register rm) {
4833 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4844 smultb(cond, rd, rn, rm);
4846 void Smultb(Register rd, Register rn, Register rm) { Smultb(al, rd, rn, rm); }
4848 void Smultt(Condition cond, Register rd, Register rn, Register rm) {
4849 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4860 smultt(cond, rd, rn, rm);
4862 void Smultt(Register rd, Register rn, Register rm) { Smultt(al, rd, rn, rm); }
4864 void Smulwb(Condition cond, Register rd, Register rn, Register rm) {
4865 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4876 smulwb(cond, rd, rn, rm);
4878 void Smulwb(Register rd, Register rn, Register rm) { Smulwb(al, rd, rn, rm); }
4880 void Smulwt(Condition cond, Register rd, Register rn, Register rm) {
4881 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4892 smulwt(cond, rd, rn, rm);
4894 void Smulwt(Register rd, Register rn, Register rm) { Smulwt(al, rd, rn, rm); }
4896 void Smusd(Condition cond, Register rd, Register rn, Register rm) {
4897 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4908 smusd(cond, rd, rn, rm);
4910 void Smusd(Register rd, Register rn, Register rm) { Smusd(al, rd, rn, rm); }
4912 void Smusdx(Condition cond, Register rd, Register rn, Register rm) {
4913 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4924 smusdx(cond, rd, rn, rm);
4926 void Smusdx(Register rd, Register rn, Register rm) { Smusdx(al, rd, rn, rm); }
4928 void Ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand) {
4929 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4939 ssat(cond, rd, imm, operand);
4941 void Ssat(Register rd, uint32_t imm, const Operand& operand) {
4942 Ssat(al, rd, imm, operand);
4945 void Ssat16(Condition cond, Register rd, uint32_t imm, Register rn) {
4946 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4956 ssat16(cond, rd, imm, rn);
4958 void Ssat16(Register rd, uint32_t imm, Register rn) {
4959 Ssat16(al, rd, imm, rn);
4962 void Ssax(Condition cond, Register rd, Register rn, Register rm) {
4963 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4974 ssax(cond, rd, rn, rm);
4976 void Ssax(Register rd, Register rn, Register rm) { Ssax(al, rd, rn, rm); }
4978 void Ssub16(Condition cond, Register rd, Register rn, Register rm) {
4979 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
4990 ssub16(cond, rd, rn, rm);
4992 void Ssub16(Register rd, Register rn, Register rm) { Ssub16(al, rd, rn, rm); }
4994 void Ssub8(Condition cond, Register rd, Register rn, Register rm) {
4995 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5006 ssub8(cond, rd, rn, rm);
5008 void Ssub8(Register rd, Register rn, Register rm) { Ssub8(al, rd, rn, rm); }
5041 Register rd,
5044 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5055 stlex(cond, rd, rt, operand);
5057 void Stlex(Register rd, Register rt, const MemOperand& operand) {
5058 Stlex(al, rd, rt, operand);
5062 Register rd,
5065 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5076 stlexb(cond, rd, rt, operand);
5078 void Stlexb(Register rd, Register rt, const MemOperand& operand) {
5079 Stlexb(al, rd, rt, operand);
5083 Register rd,
5087 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5099 stlexd(cond, rd, rt, rt2, operand);
5101 void Stlexd(Register rd,
5105 Stlexd(al, rd, rt, rt2, operand);
5109 Register rd,
5112 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5123 stlexh(cond, rd, rt, operand);
5125 void Stlexh(Register rd, Register rt, const MemOperand& operand) {
5126 Stlexh(al, rd, rt, operand);
5383 Register rd,
5386 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5397 strex(cond, rd, rt, operand);
5399 void Strex(Register rd, Register rt, const MemOperand& operand) {
5400 Strex(al, rd, rt, operand);
5404 Register rd,
5407 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5418 strexb(cond, rd, rt, operand);
5420 void Strexb(Register rd, Register rt, const MemOperand& operand) {
5421 Strexb(al, rd, rt, operand);
5425 Register rd,
5429 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5441 strexd(cond, rd, rt, rt2, operand);
5443 void Strexd(Register rd,
5447 Strexd(al, rd, rt, rt2, operand);
5451 Register rd,
5454 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5465 strexh(cond, rd, rt, operand);
5467 void Strexh(Register rd, Register rt, const MemOperand& operand) {
5468 Strexh(al, rd, rt, operand);
5497 void Sub(Condition cond, Register rd, Register rn, const Operand& operand) {
5498 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5504 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) {
5513 rd.IsLow()) ||
5516 rd.IsLow() && rn.Is(rd)) ||
5518 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
5525 sub(cond, rd, rn, operand);
5527 void Sub(Register rd, Register rn, const Operand& operand) {
5528 Sub(al, rd, rn, operand);
5532 Register rd,
5537 Sub(cond, rd, rn, operand);
5540 Subs(cond, rd, rn, operand);
5545 ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() &&
5548 ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) ||
5549 (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256)))));
5551 Subs(cond, rd, rn, operand);
5555 ((rd.IsLow() && rn.IsLow() &&
5557 (rd.IsLow() && rn.Is(rd) &&
5560 Adds(cond, rd, rn, -operand.GetSignedImmediate());
5562 Sub(cond, rd, rn, operand);
5569 Register rd,
5572 Sub(flags, al, rd, rn, operand);
5575 void Subs(Condition cond, Register rd, Register rn, const Operand& operand) {
5576 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5587 subs(cond, rd, rn, operand);
5589 void Subs(Register rd, Register rn, const Operand& operand) {
5590 Subs(al, rd, rn, operand);
5606 void Sxtab(Condition cond, Register rd, Register rn, const Operand& operand) {
5607 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5618 sxtab(cond, rd, rn, operand);
5620 void Sxtab(Register rd, Register rn, const Operand& operand) {
5621 Sxtab(al, rd, rn, operand);
5625 Register rd,
5628 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5639 sxtab16(cond, rd, rn, operand);
5641 void Sxtab16(Register rd, Register rn, const Operand& operand) {
5642 Sxtab16(al, rd, rn, operand);
5645 void Sxtah(Condition cond, Register rd, Register rn, const Operand& operand) {
5646 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5657 sxtah(cond, rd, rn, operand);
5659 void Sxtah(Register rd, Register rn, const Operand& operand) {
5660 Sxtah(al, rd, rn, operand);
5663 void Sxtb(Condition cond, Register rd, const Operand& operand) {
5664 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5674 sxtb(cond, rd, operand);
5676 void Sxtb(Register rd, const Operand& operand) { Sxtb(al, rd, operand); }
5678 void Sxtb16(Condition cond, Register rd, const Operand& operand) {
5679 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5689 sxtb16(cond, rd, operand);
5691 void Sxtb16(Register rd, const Operand& operand) { Sxtb16(al, rd, operand); }
5693 void Sxth(Condition cond, Register rd, const Operand& operand) {
5694 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5704 sxth(cond, rd, operand);
5706 void Sxth(Register rd, const Operand& operand) { Sxth(al, rd, operand); }
5742 void Uadd16(Condition cond, Register rd, Register rn, Register rm) {
5743 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5754 uadd16(cond, rd, rn, rm);
5756 void Uadd16(Register rd, Register rn, Register rm) { Uadd16(al, rd, rn, rm); }
5758 void Uadd8(Condition cond, Register rd, Register rn, Register rm) {
5759 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5770 uadd8(cond, rd, rn, rm);
5772 void Uadd8(Register rd, Register rn, Register rm) { Uadd8(al, rd, rn, rm); }
5774 void Uasx(Condition cond, Register rd, Register rn, Register rm) {
5775 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5786 uasx(cond, rd, rn, rm);
5788 void Uasx(Register rd, Register rn, Register rm) { Uasx(al, rd, rn, rm); }
5791 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
5792 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5802 ubfx(cond, rd, rn, lsb, width);
5804 void Ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width) {
5805 Ubfx(al, rd, rn, lsb, width);
5821 void Udiv(Condition cond, Register rd, Register rn, Register rm) {
5822 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5833 udiv(cond, rd, rn, rm);
5835 void Udiv(Register rd, Register rn, Register rm) { Udiv(al, rd, rn, rm); }
5837 void Uhadd16(Condition cond, Register rd, Register rn, Register rm) {
5838 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5849 uhadd16(cond, rd, rn, rm);
5851 void Uhadd16(Register rd, Register rn, Register rm) {
5852 Uhadd16(al, rd, rn, rm);
5855 void Uhadd8(Condition cond, Register rd, Register rn, Register rm) {
5856 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5867 uhadd8(cond, rd, rn, rm);
5869 void Uhadd8(Register rd, Register rn, Register rm) { Uhadd8(al, rd, rn, rm); }
5871 void Uhasx(Condition cond, Register rd, Register rn, Register rm) {
5872 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5883 uhasx(cond, rd, rn, rm);
5885 void Uhasx(Register rd, Register rn, Register rm) { Uhasx(al, rd, rn, rm); }
5887 void Uhsax(Condition cond, Register rd, Register rn, Register rm) {
5888 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5899 uhsax(cond, rd, rn, rm);
5901 void Uhsax(Register rd, Register rn, Register rm) { Uhsax(al, rd, rn, rm); }
5903 void Uhsub16(Condition cond, Register rd, Register rn, Register rm) {
5904 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5915 uhsub16(cond, rd, rn, rm);
5917 void Uhsub16(Register rd, Register rn, Register rm) {
5918 Uhsub16(al, rd, rn, rm);
5921 void Uhsub8(Condition cond, Register rd, Register rn, Register rm) {
5922 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
5933 uhsub8(cond, rd, rn, rm);
5935 void Uhsub8(Register rd, Register rn, Register rm) { Uhsub8(al, rd, rn, rm); }
6087 void Uqadd16(Condition cond, Register rd, Register rn, Register rm) {
6088 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6099 uqadd16(cond, rd, rn, rm);
6101 void Uqadd16(Register rd, Register rn, Register rm) {
6102 Uqadd16(al, rd, rn, rm);
6105 void Uqadd8(Condition cond, Register rd, Register rn, Register rm) {
6106 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6117 uqadd8(cond, rd, rn, rm);
6119 void Uqadd8(Register rd, Register rn, Register rm) { Uqadd8(al, rd, rn, rm); }
6121 void Uqasx(Condition cond, Register rd, Register rn, Register rm) {
6122 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6133 uqasx(cond, rd, rn, rm);
6135 void Uqasx(Register rd, Register rn, Register rm) { Uqasx(al, rd, rn, rm); }
6137 void Uqsax(Condition cond, Register rd, Register rn, Register rm) {
6138 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6149 uqsax(cond, rd, rn, rm);
6151 void Uqsax(Register rd, Register rn, Register rm) { Uqsax(al, rd, rn, rm); }
6153 void Uqsub16(Condition cond, Register rd, Register rn, Register rm) {
6154 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6165 uqsub16(cond, rd, rn, rm);
6167 void Uqsub16(Register rd, Register rn, Register rm) {
6168 Uqsub16(al, rd, rn, rm);
6171 void Uqsub8(Condition cond, Register rd, Register rn, Register rm) {
6172 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6183 uqsub8(cond, rd, rn, rm);
6185 void Uqsub8(Register rd, Register rn, Register rm) { Uqsub8(al, rd, rn, rm); }
6187 void Usad8(Condition cond, Register rd, Register rn, Register rm) {
6188 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6199 usad8(cond, rd, rn, rm);
6201 void Usad8(Register rd, Register rn, Register rm) { Usad8(al, rd, rn, rm); }
6204 Condition cond, Register rd, Register rn, Register rm, Register ra) {
6205 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6217 usada8(cond, rd, rn, rm, ra);
6219 void Usada8(Register rd, Register rn, Register rm, Register ra) {
6220 Usada8(al, rd, rn, rm, ra);
6223 void Usat(Condition cond, Register rd, uint32_t imm, const Operand& operand) {
6224 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6234 usat(cond, rd, imm, operand);
6236 void Usat(Register rd, uint32_t imm, const Operand& operand) {
6237 Usat(al, rd, imm, operand);
6240 void Usat16(Condition cond, Register rd, uint32_t imm, Register rn) {
6241 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6251 usat16(cond, rd, imm, rn);
6253 void Usat16(Register rd, uint32_t imm, Register rn) {
6254 Usat16(al, rd, imm, rn);
6257 void Usax(Condition cond, Register rd, Register rn, Register rm) {
6258 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6269 usax(cond, rd, rn, rm);
6271 void Usax(Register rd, Register rn, Register rm) { Usax(al, rd, rn, rm); }
6273 void Usub16(Condition cond, Register rd, Register rn, Register rm) {
6274 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6285 usub16(cond, rd, rn, rm);
6287 void Usub16(Register rd, Register rn, Register rm) { Usub16(al, rd, rn, rm); }
6289 void Usub8(Condition cond, Register rd, Register rn, Register rm) {
6290 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6301 usub8(cond, rd, rn, rm);
6303 void Usub8(Register rd, Register rn, Register rm) { Usub8(al, rd, rn, rm); }
6305 void Uxtab(Condition cond, Register rd, Register rn, const Operand& operand) {
6306 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6317 uxtab(cond, rd, rn, operand);
6319 void Uxtab(Register rd, Register rn, const Operand& operand) {
6320 Uxtab(al, rd, rn, operand);
6324 Register rd,
6327 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6338 uxtab16(cond, rd, rn, operand);
6340 void Uxtab16(Register rd, Register rn, const Operand& operand) {
6341 Uxtab16(al, rd, rn, operand);
6344 void Uxtah(Condition cond, Register rd, Register rn, const Operand& operand) {
6345 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6356 uxtah(cond, rd, rn, operand);
6358 void Uxtah(Register rd, Register rn, const Operand& operand) {
6359 Uxtah(al, rd, rn, operand);
6362 void Uxtb(Condition cond, Register rd, const Operand& operand) {
6363 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6373 uxtb(cond, rd, operand);
6375 void Uxtb(Register rd, const Operand& operand) { Uxtb(al, rd, operand); }
6377 void Uxtb16(Condition cond, Register rd, const Operand& operand) {
6378 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6388 uxtb16(cond, rd, operand);
6390 void Uxtb16(Register rd, const Operand& operand) { Uxtb16(al, rd, operand); }
6392 void Uxth(Condition cond, Register rd, const Operand& operand) {
6393 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6403 uxth(cond, rd, operand);
6405 void Uxth(Register rd, const Operand& operand) { Uxth(al, rd, operand); }
6408 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6409 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6420 vaba(cond, dt, rd, rn, rm);
6422 void Vaba(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6423 Vaba(al, dt, rd, rn, rm);
6427 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6428 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6439 vaba(cond, dt, rd, rn, rm);
6441 void Vaba(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6442 Vaba(al, dt, rd, rn, rm);
6446 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6447 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6458 vabal(cond, dt, rd, rn, rm);
6460 void Vabal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6461 Vabal(al, dt, rd, rn, rm);
6465 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6466 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6477 vabd(cond, dt, rd, rn, rm);
6479 void Vabd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6480 Vabd(al, dt, rd, rn, rm);
6484 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6485 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6496 vabd(cond, dt, rd, rn, rm);
6498 void Vabd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6499 Vabd(al, dt, rd, rn, rm);
6503 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6504 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6515 vabdl(cond, dt, rd, rn, rm);
6517 void Vabdl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6518 Vabdl(al, dt, rd, rn, rm);
6521 void Vabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {
6522 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6532 vabs(cond, dt, rd, rm);
6534 void Vabs(DataType dt, DRegister rd, DRegister rm) { Vabs(al, dt, rd, rm); }
6536 void Vabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {
6537 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6547 vabs(cond, dt, rd, rm);
6549 void Vabs(DataType dt, QRegister rd, QRegister rm) { Vabs(al, dt, rd, rm); }
6551 void Vabs(Condition cond, DataType dt, SRegister rd, SRegister rm) {
6552 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6562 vabs(cond, dt, rd, rm);
6564 void Vabs(DataType dt, SRegister rd, SRegister rm) { Vabs(al, dt, rd, rm); }
6567 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6568 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6579 vacge(cond, dt, rd, rn, rm);
6581 void Vacge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6582 Vacge(al, dt, rd, rn, rm);
6586 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6587 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6598 vacge(cond, dt, rd, rn, rm);
6600 void Vacge(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6601 Vacge(al, dt, rd, rn, rm);
6605 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6606 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6617 vacgt(cond, dt, rd, rn, rm);
6619 void Vacgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6620 Vacgt(al, dt, rd, rn, rm);
6624 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6625 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6636 vacgt(cond, dt, rd, rn, rm);
6638 void Vacgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6639 Vacgt(al, dt, rd, rn, rm);
6643 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6644 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6655 vacle(cond, dt, rd, rn, rm);
6657 void Vacle(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6658 Vacle(al, dt, rd, rn, rm);
6662 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6663 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6674 vacle(cond, dt, rd, rn, rm);
6676 void Vacle(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6677 Vacle(al, dt, rd, rn, rm);
6681 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6682 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6693 vaclt(cond, dt, rd, rn, rm);
6695 void Vaclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6696 Vaclt(al, dt, rd, rn, rm);
6700 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6701 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6712 vaclt(cond, dt, rd, rn, rm);
6714 void Vaclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6715 Vaclt(al, dt, rd, rn, rm);
6719 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6720 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6731 vadd(cond, dt, rd, rn, rm);
6733 void Vadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6734 Vadd(al, dt, rd, rn, rm);
6738 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6739 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6750 vadd(cond, dt, rd, rn, rm);
6752 void Vadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6753 Vadd(al, dt, rd, rn, rm);
6757 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6758 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6769 vadd(cond, dt, rd, rn, rm);
6771 void Vadd(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
6772 Vadd(al, dt, rd, rn, rm);
6776 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
6777 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6788 vaddhn(cond, dt, rd, rn, rm);
6790 void Vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
6791 Vaddhn(al, dt, rd, rn, rm);
6795 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6796 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6807 vaddl(cond, dt, rd, rn, rm);
6809 void Vaddl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
6810 Vaddl(al, dt, rd, rn, rm);
6814 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
6815 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6826 vaddw(cond, dt, rd, rn, rm);
6828 void Vaddw(DataType dt, QRegister rd, QRegister rn, DRegister rm) {
6829 Vaddw(al, dt, rd, rn, rm);
6834 DRegister rd,
6837 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6848 vand(cond, dt, rd, rn, operand);
6850 void Vand(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
6851 Vand(al, dt, rd, rn, operand);
6856 QRegister rd,
6859 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6870 vand(cond, dt, rd, rn, operand);
6872 void Vand(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
6873 Vand(al, dt, rd, rn, operand);
6878 DRegister rd,
6881 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6892 vbic(cond, dt, rd, rn, operand);
6894 void Vbic(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
6895 Vbic(al, dt, rd, rn, operand);
6900 QRegister rd,
6903 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6914 vbic(cond, dt, rd, rn, operand);
6916 void Vbic(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
6917 Vbic(al, dt, rd, rn, operand);
6921 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6922 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6933 vbif(cond, dt, rd, rn, rm);
6935 void Vbif(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6936 Vbif(al, dt, rd, rn, rm);
6938 void Vbif(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
6939 Vbif(cond, kDataTypeValueNone, rd, rn, rm);
6941 void Vbif(DRegister rd, DRegister rn, DRegister rm) {
6942 Vbif(al, kDataTypeValueNone, rd, rn, rm);
6946 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6947 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6958 vbif(cond, dt, rd, rn, rm);
6960 void Vbif(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6961 Vbif(al, dt, rd, rn, rm);
6963 void Vbif(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
6964 Vbif(cond, kDataTypeValueNone, rd, rn, rm);
6966 void Vbif(QRegister rd, QRegister rn, QRegister rm) {
6967 Vbif(al, kDataTypeValueNone, rd, rn, rm);
6971 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6972 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
6983 vbit(cond, dt, rd, rn, rm);
6985 void Vbit(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
6986 Vbit(al, dt, rd, rn, rm);
6988 void Vbit(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
6989 Vbit(cond, kDataTypeValueNone, rd, rn, rm);
6991 void Vbit(DRegister rd, DRegister rn, DRegister rm) {
6992 Vbit(al, kDataTypeValueNone, rd, rn, rm);
6996 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
6997 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7008 vbit(cond, dt, rd, rn, rm);
7010 void Vbit(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7011 Vbit(al, dt, rd, rn, rm);
7013 void Vbit(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
7014 Vbit(cond, kDataTypeValueNone, rd, rn, rm);
7016 void Vbit(QRegister rd, QRegister rn, QRegister rm) {
7017 Vbit(al, kDataTypeValueNone, rd, rn, rm);
7021 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7022 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7033 vbsl(cond, dt, rd, rn, rm);
7035 void Vbsl(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7036 Vbsl(al, dt, rd, rn, rm);
7038 void Vbsl(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
7039 Vbsl(cond, kDataTypeValueNone, rd, rn, rm);
7041 void Vbsl(DRegister rd, DRegister rn, DRegister rm) {
7042 Vbsl(al, kDataTypeValueNone, rd, rn, rm);
7046 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7047 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7058 vbsl(cond, dt, rd, rn, rm);
7060 void Vbsl(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7061 Vbsl(al, dt, rd, rn, rm);
7063 void Vbsl(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
7064 Vbsl(cond, kDataTypeValueNone, rd, rn, rm);
7066 void Vbsl(QRegister rd, QRegister rn, QRegister rm) {
7067 Vbsl(al, kDataTypeValueNone, rd, rn, rm);
7072 DRegister rd,
7075 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7086 vceq(cond, dt, rd, rm, operand);
7088 void Vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
7089 Vceq(al, dt, rd, rm, operand);
7094 QRegister rd,
7097 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7108 vceq(cond, dt, rd, rm, operand);
7110 void Vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
7111 Vceq(al, dt, rd, rm, operand);
7115 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7116 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7127 vceq(cond, dt, rd, rn, rm);
7129 void Vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7130 Vceq(al, dt, rd, rn, rm);
7134 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7135 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7146 vceq(cond, dt, rd, rn, rm);
7148 void Vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7149 Vceq(al, dt, rd, rn, rm);
7154 DRegister rd,
7157 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7168 vcge(cond, dt, rd, rm, operand);
7170 void Vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
7171 Vcge(al, dt, rd, rm, operand);
7176 QRegister rd,
7179 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7190 vcge(cond, dt, rd, rm, operand);
7192 void Vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
7193 Vcge(al, dt, rd, rm, operand);
7197 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7198 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7209 vcge(cond, dt, rd, rn, rm);
7211 void Vcge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7212 Vcge(al, dt, rd, rn, rm);
7216 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7217 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7228 vcge(cond, dt, rd, rn, rm);
7230 void Vcge(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7231 Vcge(al, dt, rd, rn, rm);
7236 DRegister rd,
7239 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7250 vcgt(cond, dt, rd, rm, operand);
7252 void Vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
7253 Vcgt(al, dt, rd, rm, operand);
7258 QRegister rd,
7261 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7272 vcgt(cond, dt, rd, rm, operand);
7274 void Vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
7275 Vcgt(al, dt, rd, rm, operand);
7279 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7280 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7291 vcgt(cond, dt, rd, rn, rm);
7293 void Vcgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7294 Vcgt(al, dt, rd, rn, rm);
7298 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7299 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7310 vcgt(cond, dt, rd, rn, rm);
7312 void Vcgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7313 Vcgt(al, dt, rd, rn, rm);
7318 DRegister rd,
7321 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7332 vcle(cond, dt, rd, rm, operand);
7334 void Vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
7335 Vcle(al, dt, rd, rm, operand);
7340 QRegister rd,
7343 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7354 vcle(cond, dt, rd, rm, operand);
7356 void Vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
7357 Vcle(al, dt, rd, rm, operand);
7361 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7362 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7373 vcle(cond, dt, rd, rn, rm);
7375 void Vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7376 Vcle(al, dt, rd, rn, rm);
7380 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7381 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7392 vcle(cond, dt, rd, rn, rm);
7394 void Vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7395 Vcle(al, dt, rd, rn, rm);
7398 void Vcls(Condition cond, DataType dt, DRegister rd, DRegister rm) {
7399 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7409 vcls(cond, dt, rd, rm);
7411 void Vcls(DataType dt, DRegister rd, DRegister rm) { Vcls(al, dt, rd, rm); }
7413 void Vcls(Condition cond, DataType dt, QRegister rd, QRegister rm) {
7414 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7424 vcls(cond, dt, rd, rm);
7426 void Vcls(DataType dt, QRegister rd, QRegister rm) { Vcls(al, dt, rd, rm); }
7430 DRegister rd,
7433 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7444 vclt(cond, dt, rd, rm, operand);
7446 void Vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
7447 Vclt(al, dt, rd, rm, operand);
7452 QRegister rd,
7455 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7466 vclt(cond, dt, rd, rm, operand);
7468 void Vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
7469 Vclt(al, dt, rd, rm, operand);
7473 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7474 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7485 vclt(cond, dt, rd, rn, rm);
7487 void Vclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
7488 Vclt(al, dt, rd, rn, rm);
7492 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7493 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7504 vclt(cond, dt, rd, rn, rm);
7506 void Vclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
7507 Vclt(al, dt, rd, rn, rm);
7510 void Vclz(Condition cond, DataType dt, DRegister rd, DRegister rm) {
7511 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7521 vclz(cond, dt, rd, rm);
7523 void Vclz(DataType dt, DRegister rd, DRegister rm) { Vclz(al, dt, rd, rm); }
7525 void Vclz(Condition cond, DataType dt, QRegister rd, QRegister rm) {
7526 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7536 vclz(cond, dt, rd, rm);
7538 void Vclz(DataType dt, QRegister rd, QRegister rm) { Vclz(al, dt, rd, rm); }
7542 SRegister rd,
7544 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7554 vcmp(cond, dt, rd, operand);
7556 void Vcmp(DataType dt, SRegister rd, const SOperand& operand) {
7557 Vcmp(al, dt, rd, operand);
7562 DRegister rd,
7564 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7574 vcmp(cond, dt, rd, operand);
7576 void Vcmp(DataType dt, DRegister rd, const DOperand& operand) {
7577 Vcmp(al, dt, rd, operand);
7582 SRegister rd,
7584 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7594 vcmpe(cond, dt, rd, operand);
7596 void Vcmpe(DataType dt, SRegister rd, const SOperand& operand) {
7597 Vcmpe(al, dt, rd, operand);
7602 DRegister rd,
7604 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7614 vcmpe(cond, dt, rd, operand);
7616 void Vcmpe(DataType dt, DRegister rd, const DOperand& operand) {
7617 Vcmpe(al, dt, rd, operand);
7620 void Vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm) {
7621 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7631 vcnt(cond, dt, rd, rm);
7633 void Vcnt(DataType dt, DRegister rd, DRegister rm) { Vcnt(al, dt, rd, rm); }
7635 void Vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm) {
7636 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7646 vcnt(cond, dt, rd, rm);
7648 void Vcnt(DataType dt, QRegister rd, QRegister rm) { Vcnt(al, dt, rd, rm); }
7651 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
7652 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7662 vcvt(cond, dt1, dt2, rd, rm);
7664 void Vcvt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
7665 Vcvt(al, dt1, dt2, rd, rm);
7669 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
7670 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7680 vcvt(cond, dt1, dt2, rd, rm);
7682 void Vcvt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
7683 Vcvt(al, dt1, dt2, rd, rm);
7689 DRegister rd,
7692 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7702 vcvt(cond, dt1, dt2, rd, rm, fbits);
7705 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) {
7706 Vcvt(al, dt1, dt2, rd, rm, fbits);
7712 QRegister rd,
7715 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7725 vcvt(cond, dt1, dt2, rd, rm, fbits);
7728 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) {
7729 Vcvt(al, dt1, dt2, rd, rm, fbits);
7735 SRegister rd,
7738 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7748 vcvt(cond, dt1, dt2, rd, rm, fbits);
7751 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) {
7752 Vcvt(al, dt1, dt2, rd, rm, fbits);
7756 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7757 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7767 vcvt(cond, dt1, dt2, rd, rm);
7769 void Vcvt(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7770 Vcvt(al, dt1, dt2, rd, rm);
7774 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
7775 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7785 vcvt(cond, dt1, dt2, rd, rm);
7787 void Vcvt(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
7788 Vcvt(al, dt1, dt2, rd, rm);
7792 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm) {
7793 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7803 vcvt(cond, dt1, dt2, rd, rm);
7805 void Vcvt(DataType dt1, DataType dt2, DRegister rd, QRegister rm) {
7806 Vcvt(al, dt1, dt2, rd, rm);
7810 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm) {
7811 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7821 vcvt(cond, dt1, dt2, rd, rm);
7823 void Vcvt(DataType dt1, DataType dt2, QRegister rd, DRegister rm) {
7824 Vcvt(al, dt1, dt2, rd, rm);
7828 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7829 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7839 vcvt(cond, dt1, dt2, rd, rm);
7841 void Vcvt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7842 Vcvt(al, dt1, dt2, rd, rm);
7845 void Vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7846 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7851 vcvta(dt1, dt2, rd, rm);
7854 void Vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
7855 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7860 vcvta(dt1, dt2, rd, rm);
7863 void Vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7864 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7869 vcvta(dt1, dt2, rd, rm);
7872 void Vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
7873 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7878 vcvta(dt1, dt2, rd, rm);
7882 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7883 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7893 vcvtb(cond, dt1, dt2, rd, rm);
7895 void Vcvtb(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7896 Vcvtb(al, dt1, dt2, rd, rm);
7900 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
7901 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7911 vcvtb(cond, dt1, dt2, rd, rm);
7913 void Vcvtb(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
7914 Vcvtb(al, dt1, dt2, rd, rm);
7918 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
7919 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7929 vcvtb(cond, dt1, dt2, rd, rm);
7931 void Vcvtb(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
7932 Vcvtb(al, dt1, dt2, rd, rm);
7935 void Vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7936 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7941 vcvtm(dt1, dt2, rd, rm);
7944 void Vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
7945 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7950 vcvtm(dt1, dt2, rd, rm);
7953 void Vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7954 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7959 vcvtm(dt1, dt2, rd, rm);
7962 void Vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
7963 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7968 vcvtm(dt1, dt2, rd, rm);
7971 void Vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
7972 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7977 vcvtn(dt1, dt2, rd, rm);
7980 void Vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
7981 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7986 vcvtn(dt1, dt2, rd, rm);
7989 void Vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
7990 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
7995 vcvtn(dt1, dt2, rd, rm);
7998 void Vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
7999 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8004 vcvtn(dt1, dt2, rd, rm);
8007 void Vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
8008 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8013 vcvtp(dt1, dt2, rd, rm);
8016 void Vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
8017 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8022 vcvtp(dt1, dt2, rd, rm);
8025 void Vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
8026 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8031 vcvtp(dt1, dt2, rd, rm);
8034 void Vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
8035 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8040 vcvtp(dt1, dt2, rd, rm);
8044 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
8045 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8055 vcvtr(cond, dt1, dt2, rd, rm);
8057 void Vcvtr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
8058 Vcvtr(al, dt1, dt2, rd, rm);
8062 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
8063 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8073 vcvtr(cond, dt1, dt2, rd, rm);
8075 void Vcvtr(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
8076 Vcvtr(al, dt1, dt2, rd, rm);
8080 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
8081 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8091 vcvtt(cond, dt1, dt2, rd, rm);
8093 void Vcvtt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
8094 Vcvtt(al, dt1, dt2, rd, rm);
8098 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
8099 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8109 vcvtt(cond, dt1, dt2, rd, rm);
8111 void Vcvtt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
8112 Vcvtt(al, dt1, dt2, rd, rm);
8116 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
8117 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8127 vcvtt(cond, dt1, dt2, rd, rm);
8129 void Vcvtt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
8130 Vcvtt(al, dt1, dt2, rd, rm);
8134 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8135 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8146 vdiv(cond, dt, rd, rn, rm);
8148 void Vdiv(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8149 Vdiv(al, dt, rd, rn, rm);
8153 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8154 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8165 vdiv(cond, dt, rd, rn, rm);
8167 void Vdiv(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8168 Vdiv(al, dt, rd, rn, rm);
8171 void Vdup(Condition cond, DataType dt, QRegister rd, Register rt) {
8172 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8182 vdup(cond, dt, rd, rt);
8184 void Vdup(DataType dt, QRegister rd, Register rt) { Vdup(al, dt, rd, rt); }
8186 void Vdup(Condition cond, DataType dt, DRegister rd, Register rt) {
8187 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8197 vdup(cond, dt, rd, rt);
8199 void Vdup(DataType dt, DRegister rd, Register rt) { Vdup(al, dt, rd, rt); }
8201 void Vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm) {
8202 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8212 vdup(cond, dt, rd, rm);
8214 void Vdup(DataType dt, DRegister rd, DRegisterLane rm) {
8215 Vdup(al, dt, rd, rm);
8218 void Vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm) {
8219 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8229 vdup(cond, dt, rd, rm);
8231 void Vdup(DataType dt, QRegister rd, DRegisterLane rm) {
8232 Vdup(al, dt, rd, rm);
8236 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8237 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8248 veor(cond, dt, rd, rn, rm);
8250 void Veor(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8251 Veor(al, dt, rd, rn, rm);
8253 void Veor(Condition cond, DRegister rd, DRegister rn, DRegister rm) {
8254 Veor(cond, kDataTypeValueNone, rd, rn, rm);
8256 void Veor(DRegister rd, DRegister rn, DRegister rm) {
8257 Veor(al, kDataTypeValueNone, rd, rn, rm);
8261 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8262 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8273 veor(cond, dt, rd, rn, rm);
8275 void Veor(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8276 Veor(al, dt, rd, rn, rm);
8278 void Veor(Condition cond, QRegister rd, QRegister rn, QRegister rm) {
8279 Veor(cond, kDataTypeValueNone, rd, rn, rm);
8281 void Veor(QRegister rd, QRegister rn, QRegister rm) {
8282 Veor(al, kDataTypeValueNone, rd, rn, rm);
8287 DRegister rd,
8291 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8303 vext(cond, dt, rd, rn, rm, operand);
8306 DRegister rd,
8310 Vext(al, dt, rd, rn, rm, operand);
8315 QRegister rd,
8319 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8331 vext(cond, dt, rd, rn, rm, operand);
8334 QRegister rd,
8338 Vext(al, dt, rd, rn, rm, operand);
8342 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8343 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8354 vfma(cond, dt, rd, rn, rm);
8356 void Vfma(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8357 Vfma(al, dt, rd, rn, rm);
8361 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8362 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8373 vfma(cond, dt, rd, rn, rm);
8375 void Vfma(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8376 Vfma(al, dt, rd, rn, rm);
8380 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8381 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8392 vfma(cond, dt, rd, rn, rm);
8394 void Vfma(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8395 Vfma(al, dt, rd, rn, rm);
8399 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8400 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8411 vfms(cond, dt, rd, rn, rm);
8413 void Vfms(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8414 Vfms(al, dt, rd, rn, rm);
8418 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8419 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8430 vfms(cond, dt, rd, rn, rm);
8432 void Vfms(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8433 Vfms(al, dt, rd, rn, rm);
8437 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8438 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8449 vfms(cond, dt, rd, rn, rm);
8451 void Vfms(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8452 Vfms(al, dt, rd, rn, rm);
8456 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8457 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8468 vfnma(cond, dt, rd, rn, rm);
8470 void Vfnma(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8471 Vfnma(al, dt, rd, rn, rm);
8475 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8476 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8487 vfnma(cond, dt, rd, rn, rm);
8489 void Vfnma(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8490 Vfnma(al, dt, rd, rn, rm);
8494 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8495 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8506 vfnms(cond, dt, rd, rn, rm);
8508 void Vfnms(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
8509 Vfnms(al, dt, rd, rn, rm);
8513 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8514 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8525 vfnms(cond, dt, rd, rn, rm);
8527 void Vfnms(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8528 Vfnms(al, dt, rd, rn, rm);
8532 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8533 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8544 vhadd(cond, dt, rd, rn, rm);
8546 void Vhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8547 Vhadd(al, dt, rd, rn, rm);
8551 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8552 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8563 vhadd(cond, dt, rd, rn, rm);
8565 void Vhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8566 Vhadd(al, dt, rd, rn, rm);
8570 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8571 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8582 vhsub(cond, dt, rd, rn, rm);
8584 void Vhsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8585 Vhsub(al, dt, rd, rn, rm);
8589 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8590 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8601 vhsub(cond, dt, rd, rn, rm);
8603 void Vhsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8604 Vhsub(al, dt, rd, rn, rm);
8918 DRegister rd,
8920 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8930 vldr(cond, dt, rd, operand);
8932 void Vldr(DataType dt, DRegister rd, const MemOperand& operand) {
8933 Vldr(al, dt, rd, operand);
8935 void Vldr(Condition cond, DRegister rd, const MemOperand& operand) {
8936 Vldr(cond, Untyped64, rd, operand);
8938 void Vldr(DRegister rd, const MemOperand& operand) {
8939 Vldr(al, Untyped64, rd, operand);
8945 SRegister rd,
8947 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8957 vldr(cond, dt, rd, operand);
8959 void Vldr(DataType dt, SRegister rd, const MemOperand& operand) {
8960 Vldr(al, dt, rd, operand);
8962 void Vldr(Condition cond, SRegister rd, const MemOperand& operand) {
8963 Vldr(cond, Untyped32, rd, operand);
8965 void Vldr(SRegister rd, const MemOperand& operand) {
8966 Vldr(al, Untyped32, rd, operand);
8970 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8971 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
8982 vmax(cond, dt, rd, rn, rm);
8984 void Vmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
8985 Vmax(al, dt, rd, rn, rm);
8989 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
8990 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9001 vmax(cond, dt, rd, rn, rm);
9003 void Vmax(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9004 Vmax(al, dt, rd, rn, rm);
9007 void Vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9008 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9014 vmaxnm(dt, rd, rn, rm);
9017 void Vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9018 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9024 vmaxnm(dt, rd, rn, rm);
9027 void Vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9028 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9034 vmaxnm(dt, rd, rn, rm);
9038 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9039 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9050 vmin(cond, dt, rd, rn, rm);
9052 void Vmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9053 Vmin(al, dt, rd, rn, rm);
9057 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9058 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9069 vmin(cond, dt, rd, rn, rm);
9071 void Vmin(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9072 Vmin(al, dt, rd, rn, rm);
9075 void Vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9076 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9082 vminnm(dt, rd, rn, rm);
9085 void Vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9086 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9092 vminnm(dt, rd, rn, rm);
9095 void Vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9096 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9102 vminnm(dt, rd, rn, rm);
9107 DRegister rd,
9110 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9121 vmla(cond, dt, rd, rn, rm);
9123 void Vmla(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
9124 Vmla(al, dt, rd, rn, rm);
9129 QRegister rd,
9132 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9143 vmla(cond, dt, rd, rn, rm);
9145 void Vmla(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
9146 Vmla(al, dt, rd, rn, rm);
9150 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9151 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9162 vmla(cond, dt, rd, rn, rm);
9164 void Vmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9165 Vmla(al, dt, rd, rn, rm);
9169 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9170 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9181 vmla(cond, dt, rd, rn, rm);
9183 void Vmla(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9184 Vmla(al, dt, rd, rn, rm);
9188 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9189 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9200 vmla(cond, dt, rd, rn, rm);
9202 void Vmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9203 Vmla(al, dt, rd, rn, rm);
9208 QRegister rd,
9211 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9222 vmlal(cond, dt, rd, rn, rm);
9224 void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
9225 Vmlal(al, dt, rd, rn, rm);
9229 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
9230 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9241 vmlal(cond, dt, rd, rn, rm);
9243 void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
9244 Vmlal(al, dt, rd, rn, rm);
9249 DRegister rd,
9252 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9263 vmls(cond, dt, rd, rn, rm);
9265 void Vmls(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
9266 Vmls(al, dt, rd, rn, rm);
9271 QRegister rd,
9274 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9285 vmls(cond, dt, rd, rn, rm);
9287 void Vmls(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
9288 Vmls(al, dt, rd, rn, rm);
9292 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9293 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9304 vmls(cond, dt, rd, rn, rm);
9306 void Vmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9307 Vmls(al, dt, rd, rn, rm);
9311 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9312 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9323 vmls(cond, dt, rd, rn, rm);
9325 void Vmls(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9326 Vmls(al, dt, rd, rn, rm);
9330 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9331 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9342 vmls(cond, dt, rd, rn, rm);
9344 void Vmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9345 Vmls(al, dt, rd, rn, rm);
9350 QRegister rd,
9353 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9364 vmlsl(cond, dt, rd, rn, rm);
9366 void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
9367 Vmlsl(al, dt, rd, rn, rm);
9371 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
9372 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9383 vmlsl(cond, dt, rd, rn, rm);
9385 void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
9386 Vmlsl(al, dt, rd, rn, rm);
9491 void Vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt) {
9492 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9502 vmov(cond, dt, rd, rt);
9504 void Vmov(DataType dt, DRegisterLane rd, Register rt) {
9505 Vmov(al, dt, rd, rt);
9507 void Vmov(Condition cond, DRegisterLane rd, Register rt) {
9508 Vmov(cond, kDataTypeValueNone, rd, rt);
9510 void Vmov(DRegisterLane rd, Register rt) {
9511 Vmov(al, kDataTypeValueNone, rd, rt);
9516 DRegister rd,
9518 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9528 vmov(cond, dt, rd, operand);
9530 void Vmov(DataType dt, DRegister rd, const DOperand& operand) {
9531 Vmov(al, dt, rd, operand);
9536 QRegister rd,
9538 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9548 vmov(cond, dt, rd, operand);
9550 void Vmov(DataType dt, QRegister rd, const QOperand& operand) {
9551 Vmov(al, dt, rd, operand);
9556 SRegister rd,
9558 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9568 vmov(cond, dt, rd, operand);
9570 void Vmov(DataType dt, SRegister rd, const SOperand& operand) {
9571 Vmov(al, dt, rd, operand);
9597 void Vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm) {
9598 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9608 vmovl(cond, dt, rd, rm);
9610 void Vmovl(DataType dt, QRegister rd, DRegister rm) { Vmovl(al, dt, rd, rm); }
9612 void Vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) {
9613 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9623 vmovn(cond, dt, rd, rm);
9625 void Vmovn(DataType dt, DRegister rd, QRegister rm) { Vmovn(al, dt, rd, rm); }
9661 DRegister rd,
9665 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9676 vmul(cond, dt, rd, rn, dm, index);
9679 DataType dt, DRegister rd, DRegister rn, DRegister dm, unsigned index) {
9680 Vmul(al, dt, rd, rn, dm, index);
9685 QRegister rd,
9689 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9700 vmul(cond, dt, rd, rn, dm, index);
9703 DataType dt, QRegister rd, QRegister rn, DRegister dm, unsigned index) {
9704 Vmul(al, dt, rd, rn, dm, index);
9708 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9709 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9720 vmul(cond, dt, rd, rn, rm);
9722 void Vmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9723 Vmul(al, dt, rd, rn, rm);
9727 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9728 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9739 vmul(cond, dt, rd, rn, rm);
9741 void Vmul(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
9742 Vmul(al, dt, rd, rn, rm);
9746 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9747 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9758 vmul(cond, dt, rd, rn, rm);
9760 void Vmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9761 Vmul(al, dt, rd, rn, rm);
9766 QRegister rd,
9770 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9781 vmull(cond, dt, rd, rn, dm, index);
9784 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
9785 Vmull(al, dt, rd, rn, dm, index);
9789 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
9790 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9801 vmull(cond, dt, rd, rn, rm);
9803 void Vmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
9804 Vmull(al, dt, rd, rn, rm);
9809 DRegister rd,
9811 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9821 vmvn(cond, dt, rd, operand);
9823 void Vmvn(DataType dt, DRegister rd, const DOperand& operand) {
9824 Vmvn(al, dt, rd, operand);
9829 QRegister rd,
9831 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9841 vmvn(cond, dt, rd, operand);
9843 void Vmvn(DataType dt, QRegister rd, const QOperand& operand) {
9844 Vmvn(al, dt, rd, operand);
9847 void Vneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {
9848 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9858 vneg(cond, dt, rd, rm);
9860 void Vneg(DataType dt, DRegister rd, DRegister rm) { Vneg(al, dt, rd, rm); }
9862 void Vneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {
9863 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9873 vneg(cond, dt, rd, rm);
9875 void Vneg(DataType dt, QRegister rd, QRegister rm) { Vneg(al, dt, rd, rm); }
9877 void Vneg(Condition cond, DataType dt, SRegister rd, SRegister rm) {
9878 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9888 vneg(cond, dt, rd, rm);
9890 void Vneg(DataType dt, SRegister rd, SRegister rm) { Vneg(al, dt, rd, rm); }
9893 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9894 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9905 vnmla(cond, dt, rd, rn, rm);
9907 void Vnmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9908 Vnmla(al, dt, rd, rn, rm);
9912 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9913 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9924 vnmla(cond, dt, rd, rn, rm);
9926 void Vnmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9927 Vnmla(al, dt, rd, rn, rm);
9931 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9932 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9943 vnmls(cond, dt, rd, rn, rm);
9945 void Vnmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9946 Vnmls(al, dt, rd, rn, rm);
9950 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9951 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9962 vnmls(cond, dt, rd, rn, rm);
9964 void Vnmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9965 Vnmls(al, dt, rd, rn, rm);
9969 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9970 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
9981 vnmul(cond, dt, rd, rn, rm);
9983 void Vnmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
9984 Vnmul(al, dt, rd, rn, rm);
9988 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
9989 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10000 vnmul(cond, dt, rd, rn, rm);
10002 void Vnmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10003 Vnmul(al, dt, rd, rn, rm);
10008 DRegister rd,
10011 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10022 vorn(cond, dt, rd, rn, operand);
10024 void Vorn(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
10025 Vorn(al, dt, rd, rn, operand);
10030 QRegister rd,
10033 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10044 vorn(cond, dt, rd, rn, operand);
10046 void Vorn(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
10047 Vorn(al, dt, rd, rn, operand);
10052 DRegister rd,
10055 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10066 vorr(cond, dt, rd, rn, operand);
10068 void Vorr(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) {
10069 Vorr(al, dt, rd, rn, operand);
10072 DRegister rd,
10075 Vorr(cond, kDataTypeValueNone, rd, rn, operand);
10077 void Vorr(DRegister rd, DRegister rn, const DOperand& operand) {
10078 Vorr(al, kDataTypeValueNone, rd, rn, operand);
10083 QRegister rd,
10086 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10097 vorr(cond, dt, rd, rn, operand);
10099 void Vorr(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) {
10100 Vorr(al, dt, rd, rn, operand);
10103 QRegister rd,
10106 Vorr(cond, kDataTypeValueNone, rd, rn, operand);
10108 void Vorr(QRegister rd, QRegister rn, const QOperand& operand) {
10109 Vorr(al, kDataTypeValueNone, rd, rn, operand);
10112 void Vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm) {
10113 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10123 vpadal(cond, dt, rd, rm);
10125 void Vpadal(DataType dt, DRegister rd, DRegister rm) {
10126 Vpadal(al, dt, rd, rm);
10129 void Vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm) {
10130 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10140 vpadal(cond, dt, rd, rm);
10142 void Vpadal(DataType dt, QRegister rd, QRegister rm) {
10143 Vpadal(al, dt, rd, rm);
10147 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10148 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10159 vpadd(cond, dt, rd, rn, rm);
10161 void Vpadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10162 Vpadd(al, dt, rd, rn, rm);
10165 void Vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm) {
10166 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10176 vpaddl(cond, dt, rd, rm);
10178 void Vpaddl(DataType dt, DRegister rd, DRegister rm) {
10179 Vpaddl(al, dt, rd, rm);
10182 void Vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm) {
10183 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10193 vpaddl(cond, dt, rd, rm);
10195 void Vpaddl(DataType dt, QRegister rd, QRegister rm) {
10196 Vpaddl(al, dt, rd, rm);
10200 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10201 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10212 vpmax(cond, dt, rd, rn, rm);
10214 void Vpmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10215 Vpmax(al, dt, rd, rn, rm);
10219 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10220 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10231 vpmin(cond, dt, rd, rn, rm);
10233 void Vpmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10234 Vpmin(al, dt, rd, rn, rm);
10313 void Vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {
10314 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10324 vqabs(cond, dt, rd, rm);
10326 void Vqabs(DataType dt, DRegister rd, DRegister rm) { Vqabs(al, dt, rd, rm); }
10328 void Vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {
10329 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10339 vqabs(cond, dt, rd, rm);
10341 void Vqabs(DataType dt, QRegister rd, QRegister rm) { Vqabs(al, dt, rd, rm); }
10344 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10345 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10356 vqadd(cond, dt, rd, rn, rm);
10358 void Vqadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10359 Vqadd(al, dt, rd, rn, rm);
10363 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
10364 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10375 vqadd(cond, dt, rd, rn, rm);
10377 void Vqadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
10378 Vqadd(al, dt, rd, rn, rm);
10382 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
10383 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10394 vqdmlal(cond, dt, rd, rn, rm);
10396 void Vqdmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
10397 Vqdmlal(al, dt, rd, rn, rm);
10402 QRegister rd,
10406 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10417 vqdmlal(cond, dt, rd, rn, dm, index);
10420 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
10421 Vqdmlal(al, dt, rd, rn, dm, index);
10425 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
10426 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10437 vqdmlsl(cond, dt, rd, rn, rm);
10439 void Vqdmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
10440 Vqdmlsl(al, dt, rd, rn, rm);
10445 QRegister rd,
10449 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10460 vqdmlsl(cond, dt, rd, rn, dm, index);
10463 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) {
10464 Vqdmlsl(al, dt, rd, rn, dm, index);
10468 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10469 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10480 vqdmulh(cond, dt, rd, rn, rm);
10482 void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10483 Vqdmulh(al, dt, rd, rn, rm);
10487 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
10488 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10499 vqdmulh(cond, dt, rd, rn, rm);
10501 void Vqdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
10502 Vqdmulh(al, dt, rd, rn, rm);
10507 DRegister rd,
10510 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10521 vqdmulh(cond, dt, rd, rn, rm);
10523 void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
10524 Vqdmulh(al, dt, rd, rn, rm);
10529 QRegister rd,
10532 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10543 vqdmulh(cond, dt, rd, rn, rm);
10545 void Vqdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
10546 Vqdmulh(al, dt, rd, rn, rm);
10550 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
10551 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10562 vqdmull(cond, dt, rd, rn, rm);
10564 void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
10565 Vqdmull(al, dt, rd, rn, rm);
10570 QRegister rd,
10573 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10584 vqdmull(cond, dt, rd, rn, rm);
10586 void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
10587 Vqdmull(al, dt, rd, rn, rm);
10590 void Vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) {
10591 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10601 vqmovn(cond, dt, rd, rm);
10603 void Vqmovn(DataType dt, DRegister rd, QRegister rm) {
10604 Vqmovn(al, dt, rd, rm);
10607 void Vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm) {
10608 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10618 vqmovun(cond, dt, rd, rm);
10620 void Vqmovun(DataType dt, DRegister rd, QRegister rm) {
10621 Vqmovun(al, dt, rd, rm);
10624 void Vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {
10625 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10635 vqneg(cond, dt, rd, rm);
10637 void Vqneg(DataType dt, DRegister rd, DRegister rm) { Vqneg(al, dt, rd, rm); }
10639 void Vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {
10640 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10650 vqneg(cond, dt, rd, rm);
10652 void Vqneg(DataType dt, QRegister rd, QRegister rm) { Vqneg(al, dt, rd, rm); }
10655 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10656 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10667 vqrdmulh(cond, dt, rd, rn, rm);
10669 void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10670 Vqrdmulh(al, dt, rd, rn, rm);
10674 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
10675 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10686 vqrdmulh(cond, dt, rd, rn, rm);
10688 void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
10689 Vqrdmulh(al, dt, rd, rn, rm);
10694 DRegister rd,
10697 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10708 vqrdmulh(cond, dt, rd, rn, rm);
10710 void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
10711 Vqrdmulh(al, dt, rd, rn, rm);
10716 QRegister rd,
10719 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10730 vqrdmulh(cond, dt, rd, rn, rm);
10732 void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
10733 Vqrdmulh(al, dt, rd, rn, rm);
10737 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
10738 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10749 vqrshl(cond, dt, rd, rm, rn);
10751 void Vqrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) {
10752 Vqrshl(al, dt, rd, rm, rn);
10756 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
10757 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10768 vqrshl(cond, dt, rd, rm, rn);
10770 void Vqrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) {
10771 Vqrshl(al, dt, rd, rm, rn);
10776 DRegister rd,
10779 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10790 vqrshrn(cond, dt, rd, rm, operand);
10793 DRegister rd,
10796 Vqrshrn(al, dt, rd, rm, operand);
10801 DRegister rd,
10804 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10815 vqrshrun(cond, dt, rd, rm, operand);
10818 DRegister rd,
10821 Vqrshrun(al, dt, rd, rm, operand);
10826 DRegister rd,
10829 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10840 vqshl(cond, dt, rd, rm, operand);
10842 void Vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
10843 Vqshl(al, dt, rd, rm, operand);
10848 QRegister rd,
10851 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10862 vqshl(cond, dt, rd, rm, operand);
10864 void Vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
10865 Vqshl(al, dt, rd, rm, operand);
10870 DRegister rd,
10873 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10884 vqshlu(cond, dt, rd, rm, operand);
10887 DRegister rd,
10890 Vqshlu(al, dt, rd, rm, operand);
10895 QRegister rd,
10898 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10909 vqshlu(cond, dt, rd, rm, operand);
10912 QRegister rd,
10915 Vqshlu(al, dt, rd, rm, operand);
10920 DRegister rd,
10923 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10934 vqshrn(cond, dt, rd, rm, operand);
10937 DRegister rd,
10940 Vqshrn(al, dt, rd, rm, operand);
10945 DRegister rd,
10948 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10959 vqshrun(cond, dt, rd, rm, operand);
10962 DRegister rd,
10965 Vqshrun(al, dt, rd, rm, operand);
10969 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10970 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
10981 vqsub(cond, dt, rd, rn, rm);
10983 void Vqsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
10984 Vqsub(al, dt, rd, rn, rm);
10988 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
10989 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11000 vqsub(cond, dt, rd, rn, rm);
11002 void Vqsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
11003 Vqsub(al, dt, rd, rn, rm);
11007 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
11008 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11019 vraddhn(cond, dt, rd, rn, rm);
11021 void Vraddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
11022 Vraddhn(al, dt, rd, rn, rm);
11025 void Vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm) {
11026 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11036 vrecpe(cond, dt, rd, rm);
11038 void Vrecpe(DataType dt, DRegister rd, DRegister rm) {
11039 Vrecpe(al, dt, rd, rm);
11042 void Vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm) {
11043 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11053 vrecpe(cond, dt, rd, rm);
11055 void Vrecpe(DataType dt, QRegister rd, QRegister rm) {
11056 Vrecpe(al, dt, rd, rm);
11060 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
11061 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11072 vrecps(cond, dt, rd, rn, rm);
11074 void Vrecps(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
11075 Vrecps(al, dt, rd, rn, rm);
11079 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
11080 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11091 vrecps(cond, dt, rd, rn, rm);
11093 void Vrecps(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
11094 Vrecps(al, dt, rd, rn, rm);
11097 void Vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm) {
11098 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11108 vrev16(cond, dt, rd, rm);
11110 void Vrev16(DataType dt, DRegister rd, DRegister rm) {
11111 Vrev16(al, dt, rd, rm);
11114 void Vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm) {
11115 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11125 vrev16(cond, dt, rd, rm);
11127 void Vrev16(DataType dt, QRegister rd, QRegister rm) {
11128 Vrev16(al, dt, rd, rm);
11131 void Vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm) {
11132 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11142 vrev32(cond, dt, rd, rm);
11144 void Vrev32(DataType dt, DRegister rd, DRegister rm) {
11145 Vrev32(al, dt, rd, rm);
11148 void Vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm) {
11149 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11159 vrev32(cond, dt, rd, rm);
11161 void Vrev32(DataType dt, QRegister rd, QRegister rm) {
11162 Vrev32(al, dt, rd, rm);
11165 void Vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm) {
11166 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11176 vrev64(cond, dt, rd, rm);
11178 void Vrev64(DataType dt, DRegister rd, DRegister rm) {
11179 Vrev64(al, dt, rd, rm);
11182 void Vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm) {
11183 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11193 vrev64(cond, dt, rd, rm);
11195 void Vrev64(DataType dt, QRegister rd, QRegister rm) {
11196 Vrev64(al, dt, rd, rm);
11200 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
11201 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11212 vrhadd(cond, dt, rd, rn, rm);
11214 void Vrhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
11215 Vrhadd(al, dt, rd, rn, rm);
11219 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
11220 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11231 vrhadd(cond, dt, rd, rn, rm);
11233 void Vrhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
11234 Vrhadd(al, dt, rd, rn, rm);
11237 void Vrinta(DataType dt, DRegister rd, DRegister rm) {
11238 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11243 vrinta(dt, rd, rm);
11246 void Vrinta(DataType dt, QRegister rd, QRegister rm) {
11247 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11252 vrinta(dt, rd, rm);
11255 void Vrinta(DataType dt, SRegister rd, SRegister rm) {
11256 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11261 vrinta(dt, rd, rm);
11264 void Vrintm(DataType dt, DRegister rd, DRegister rm) {
11265 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11270 vrintm(dt, rd, rm);
11273 void Vrintm(DataType dt, QRegister rd, QRegister rm) {
11274 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11279 vrintm(dt, rd, rm);
11282 void Vrintm(DataType dt, SRegister rd, SRegister rm) {
11283 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11288 vrintm(dt, rd, rm);
11291 void Vrintn(DataType dt, DRegister rd, DRegister rm) {
11292 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11297 vrintn(dt, rd, rm);
11300 void Vrintn(DataType dt, QRegister rd, QRegister rm) {
11301 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11306 vrintn(dt, rd, rm);
11309 void Vrintn(DataType dt, SRegister rd, SRegister rm) {
11310 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11315 vrintn(dt, rd, rm);
11318 void Vrintp(DataType dt, DRegister rd, DRegister rm) {
11319 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11324 vrintp(dt, rd, rm);
11327 void Vrintp(DataType dt, QRegister rd, QRegister rm) {
11328 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11333 vrintp(dt, rd, rm);
11336 void Vrintp(DataType dt, SRegister rd, SRegister rm) {
11337 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11342 vrintp(dt, rd, rm);
11345 void Vrintr(Condition cond, DataType dt, SRegister rd, SRegister rm) {
11346 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11356 vrintr(cond, dt, rd, rm);
11358 void Vrintr(DataType dt, SRegister rd, SRegister rm) {
11359 Vrintr(al, dt, rd, rm);
11362 void Vrintr(Condition cond, DataType dt, DRegister rd, DRegister rm) {
11363 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11373 vrintr(cond, dt, rd, rm);
11375 void Vrintr(DataType dt, DRegister rd, DRegister rm) {
11376 Vrintr(al, dt, rd, rm);
11379 void Vrintx(Condition cond, DataType dt, DRegister rd, DRegister rm) {
11380 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11390 vrintx(cond, dt, rd, rm);
11392 void Vrintx(DataType dt, DRegister rd, DRegister rm) {
11393 Vrintx(al, dt, rd, rm);
11396 void Vrintx(DataType dt, QRegister rd, QRegister rm) {
11397 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11402 vrintx(dt, rd, rm);
11405 void Vrintx(Condition cond, DataType dt, SRegister rd, SRegister rm) {
11406 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11416 vrintx(cond, dt, rd, rm);
11418 void Vrintx(DataType dt, SRegister rd, SRegister rm) {
11419 Vrintx(al, dt, rd, rm);
11422 void Vrintz(Condition cond, DataType dt, DRegister rd, DRegister rm) {
11423 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11433 vrintz(cond, dt, rd, rm);
11435 void Vrintz(DataType dt, DRegister rd, DRegister rm) {
11436 Vrintz(al, dt, rd, rm);
11439 void Vrintz(DataType dt, QRegister rd, QRegister rm) {
11440 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11445 vrintz(dt, rd, rm);
11448 void Vrintz(Condition cond, DataType dt, SRegister rd, SRegister rm) {
11449 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11459 vrintz(cond, dt, rd, rm);
11461 void Vrintz(DataType dt, SRegister rd, SRegister rm) {
11462 Vrintz(al, dt, rd, rm);
11466 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
11467 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11478 vrshl(cond, dt, rd, rm, rn);
11480 void Vrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) {
11481 Vrshl(al, dt, rd, rm, rn);
11485 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
11486 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11497 vrshl(cond, dt, rd, rm, rn);
11499 void Vrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) {
11500 Vrshl(al, dt, rd, rm, rn);
11505 DRegister rd,
11508 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11519 vrshr(cond, dt, rd, rm, operand);
11521 void Vrshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
11522 Vrshr(al, dt, rd, rm, operand);
11527 QRegister rd,
11530 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11541 vrshr(cond, dt, rd, rm, operand);
11543 void Vrshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
11544 Vrshr(al, dt, rd, rm, operand);
11549 DRegister rd,
11552 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11563 vrshrn(cond, dt, rd, rm, operand);
11566 DRegister rd,
11569 Vrshrn(al, dt, rd, rm, operand);
11572 void Vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm) {
11573 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11583 vrsqrte(cond, dt, rd, rm);
11585 void Vrsqrte(DataType dt, DRegister rd, DRegister rm) {
11586 Vrsqrte(al, dt, rd, rm);
11589 void Vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm) {
11590 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11600 vrsqrte(cond, dt, rd, rm);
11602 void Vrsqrte(DataType dt, QRegister rd, QRegister rm) {
11603 Vrsqrte(al, dt, rd, rm);
11607 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
11608 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11619 vrsqrts(cond, dt, rd, rn, rm);
11621 void Vrsqrts(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
11622 Vrsqrts(al, dt, rd, rn, rm);
11626 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
11627 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11638 vrsqrts(cond, dt, rd, rn, rm);
11640 void Vrsqrts(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
11641 Vrsqrts(al, dt, rd, rn, rm);
11646 DRegister rd,
11649 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11660 vrsra(cond, dt, rd, rm, operand);
11662 void Vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
11663 Vrsra(al, dt, rd, rm, operand);
11668 QRegister rd,
11671 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11682 vrsra(cond, dt, rd, rm, operand);
11684 void Vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
11685 Vrsra(al, dt, rd, rm, operand);
11689 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
11690 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11701 vrsubhn(cond, dt, rd, rn, rm);
11703 void Vrsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
11704 Vrsubhn(al, dt, rd, rn, rm);
11707 void Vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
11708 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11714 vseleq(dt, rd, rn, rm);
11717 void Vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
11718 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11724 vseleq(dt, rd, rn, rm);
11727 void Vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
11728 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11734 vselge(dt, rd, rn, rm);
11737 void Vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
11738 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11744 vselge(dt, rd, rn, rm);
11747 void Vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
11748 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11754 vselgt(dt, rd, rn, rm);
11757 void Vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
11758 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11764 vselgt(dt, rd, rn, rm);
11767 void Vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
11768 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11774 vselvs(dt, rd, rn, rm);
11777 void Vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
11778 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11784 vselvs(dt, rd, rn, rm);
11789 DRegister rd,
11792 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11803 vshl(cond, dt, rd, rm, operand);
11805 void Vshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
11806 Vshl(al, dt, rd, rm, operand);
11811 QRegister rd,
11814 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11825 vshl(cond, dt, rd, rm, operand);
11827 void Vshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
11828 Vshl(al, dt, rd, rm, operand);
11833 QRegister rd,
11836 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11847 vshll(cond, dt, rd, rm, operand);
11849 void Vshll(DataType dt, QRegister rd, DRegister rm, const DOperand& operand) {
11850 Vshll(al, dt, rd, rm, operand);
11855 DRegister rd,
11858 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11869 vshr(cond, dt, rd, rm, operand);
11871 void Vshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
11872 Vshr(al, dt, rd, rm, operand);
11877 QRegister rd,
11880 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11891 vshr(cond, dt, rd, rm, operand);
11893 void Vshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
11894 Vshr(al, dt, rd, rm, operand);
11899 DRegister rd,
11902 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11913 vshrn(cond, dt, rd, rm, operand);
11915 void Vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) {
11916 Vshrn(al, dt, rd, rm, operand);
11921 DRegister rd,
11924 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11935 vsli(cond, dt, rd, rm, operand);
11937 void Vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
11938 Vsli(al, dt, rd, rm, operand);
11943 QRegister rd,
11946 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11957 vsli(cond, dt, rd, rm, operand);
11959 void Vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
11960 Vsli(al, dt, rd, rm, operand);
11963 void Vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm) {
11964 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11974 vsqrt(cond, dt, rd, rm);
11976 void Vsqrt(DataType dt, SRegister rd, SRegister rm) { Vsqrt(al, dt, rd, rm); }
11978 void Vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm) {
11979 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
11989 vsqrt(cond, dt, rd, rm);
11991 void Vsqrt(DataType dt, DRegister rd, DRegister rm) { Vsqrt(al, dt, rd, rm); }
11995 DRegister rd,
11998 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12009 vsra(cond, dt, rd, rm, operand);
12011 void Vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
12012 Vsra(al, dt, rd, rm, operand);
12017 QRegister rd,
12020 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12031 vsra(cond, dt, rd, rm, operand);
12033 void Vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
12034 Vsra(al, dt, rd, rm, operand);
12039 DRegister rd,
12042 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12053 vsri(cond, dt, rd, rm, operand);
12055 void Vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) {
12056 Vsri(al, dt, rd, rm, operand);
12061 QRegister rd,
12064 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12075 vsri(cond, dt, rd, rm, operand);
12077 void Vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) {
12078 Vsri(al, dt, rd, rm, operand);
12391 DRegister rd,
12393 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12403 vstr(cond, dt, rd, operand);
12405 void Vstr(DataType dt, DRegister rd, const MemOperand& operand) {
12406 Vstr(al, dt, rd, operand);
12408 void Vstr(Condition cond, DRegister rd, const MemOperand& operand) {
12409 Vstr(cond, Untyped64, rd, operand);
12411 void Vstr(DRegister rd, const MemOperand& operand) {
12412 Vstr(al, Untyped64, rd, operand);
12417 SRegister rd,
12419 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12429 vstr(cond, dt, rd, operand);
12431 void Vstr(DataType dt, SRegister rd, const MemOperand& operand) {
12432 Vstr(al, dt, rd, operand);
12434 void Vstr(Condition cond, SRegister rd, const MemOperand& operand) {
12435 Vstr(cond, Untyped32, rd, operand);
12437 void Vstr(SRegister rd, const MemOperand& operand) {
12438 Vstr(al, Untyped32, rd, operand);
12442 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
12443 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12454 vsub(cond, dt, rd, rn, rm);
12456 void Vsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
12457 Vsub(al, dt, rd, rn, rm);
12461 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
12462 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12473 vsub(cond, dt, rd, rn, rm);
12475 void Vsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
12476 Vsub(al, dt, rd, rn, rm);
12480 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
12481 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12492 vsub(cond, dt, rd, rn, rm);
12494 void Vsub(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
12495 Vsub(al, dt, rd, rn, rm);
12499 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
12500 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12511 vsubhn(cond, dt, rd, rn, rm);
12513 void Vsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) {
12514 Vsubhn(al, dt, rd, rn, rm);
12518 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
12519 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12530 vsubl(cond, dt, rd, rn, rm);
12532 void Vsubl(DataType dt, QRegister rd, DRegister rn, DRegister rm) {
12533 Vsubl(al, dt, rd, rn, rm);
12537 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
12538 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12549 vsubw(cond, dt, rd, rn, rm);
12551 void Vsubw(DataType dt, QRegister rd, QRegister rn, DRegister rm) {
12552 Vsubw(al, dt, rd, rn, rm);
12555 void Vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) {
12556 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12566 vswp(cond, dt, rd, rm);
12568 void Vswp(DataType dt, DRegister rd, DRegister rm) { Vswp(al, dt, rd, rm); }
12569 void Vswp(Condition cond, DRegister rd, DRegister rm) {
12570 Vswp(cond, kDataTypeValueNone, rd, rm);
12572 void Vswp(DRegister rd, DRegister rm) {
12573 Vswp(al, kDataTypeValueNone, rd, rm);
12576 void Vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) {
12577 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12587 vswp(cond, dt, rd, rm);
12589 void Vswp(DataType dt, QRegister rd, QRegister rm) { Vswp(al, dt, rd, rm); }
12590 void Vswp(Condition cond, QRegister rd, QRegister rm) {
12591 Vswp(cond, kDataTypeValueNone, rd, rm);
12593 void Vswp(QRegister rd, QRegister rm) {
12594 Vswp(al, kDataTypeValueNone, rd, rm);
12599 DRegister rd,
12602 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12613 vtbl(cond, dt, rd, nreglist, rm);
12616 DRegister rd,
12619 Vtbl(al, dt, rd, nreglist, rm);
12624 DRegister rd,
12627 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12638 vtbx(cond, dt, rd, nreglist, rm);
12641 DRegister rd,
12644 Vtbx(al, dt, rd, nreglist, rm);
12647 void Vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm) {
12648 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12658 vtrn(cond, dt, rd, rm);
12660 void Vtrn(DataType dt, DRegister rd, DRegister rm) { Vtrn(al, dt, rd, rm); }
12662 void Vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm) {
12663 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12673 vtrn(cond, dt, rd, rm);
12675 void Vtrn(DataType dt, QRegister rd, QRegister rm) { Vtrn(al, dt, rd, rm); }
12678 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
12679 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12690 vtst(cond, dt, rd, rn, rm);
12692 void Vtst(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
12693 Vtst(al, dt, rd, rn, rm);
12697 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
12698 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12709 vtst(cond, dt, rd, rn, rm);
12711 void Vtst(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
12712 Vtst(al, dt, rd, rn, rm);
12715 void Vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm) {
12716 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12726 vuzp(cond, dt, rd, rm);
12728 void Vuzp(DataType dt, DRegister rd, DRegister rm) { Vuzp(al, dt, rd, rm); }
12730 void Vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm) {
12731 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12741 vuzp(cond, dt, rd, rm);
12743 void Vuzp(DataType dt, QRegister rd, QRegister rm) { Vuzp(al, dt, rd, rm); }
12745 void Vzip(Condition cond, DataType dt, DRegister rd, DRegister rm) {
12746 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12756 vzip(cond, dt, rd, rm);
12758 void Vzip(DataType dt, DRegister rd, DRegister rm) { Vzip(al, dt, rd, rm); }
12760 void Vzip(Condition cond, DataType dt, QRegister rd, QRegister rm) {
12761 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd));
12771 vzip(cond, dt, rd, rm);
12773 void Vzip(DataType dt, QRegister rd, QRegister rm) { Vzip(al, dt, rd, rm); }
12787 void Vabs(Condition cond, VRegister rd, VRegister rm) {
12788 VIXL_ASSERT(rd.IsS() || rd.IsD());
12789 VIXL_ASSERT(rd.GetType() == rm.GetType());
12790 if (rd.IsS()) {
12791 Vabs(cond, F32, rd.S(), rm.S());
12793 Vabs(cond, F64, rd.D(), rm.D());
12796 void Vabs(VRegister rd, VRegister rm) { Vabs(al, rd, rm); }
12797 void Vadd(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12798 VIXL_ASSERT(rd.IsS() || rd.IsD());
12799 VIXL_ASSERT(rd.GetType() == rn.GetType());
12800 VIXL_ASSERT(rd.GetType() == rm.GetType());
12801 if (rd.IsS()) {
12802 Vadd(cond, F32, rd.S(), rn.S(), rm.S());
12804 Vadd(cond, F64, rd.D(), rn.D(), rm.D());
12807 void Vadd(VRegister rd, VRegister rn, VRegister rm) { Vadd(al, rd, rn, rm); }
12808 void Vcmp(Condition cond, VRegister rd, VRegister rm) {
12809 VIXL_ASSERT(rd.IsS() || rd.IsD());
12810 VIXL_ASSERT(rd.GetType() == rm.GetType());
12811 if (rd.IsS()) {
12812 Vcmp(cond, F32, rd.S(), rm.S());
12814 Vcmp(cond, F64, rd.D(), rm.D());
12817 void Vcmp(VRegister rd, VRegister rm) { Vcmp(al, rd, rm); }
12818 void Vcmpe(Condition cond, VRegister rd, VRegister rm) {
12819 VIXL_ASSERT(rd.IsS() || rd.IsD());
12820 VIXL_ASSERT(rd.GetType() == rm.GetType());
12821 if (rd.IsS()) {
12822 Vcmpe(cond, F32, rd.S(), rm.S());
12824 Vcmpe(cond, F64, rd.D(), rm.D());
12827 void Vcmpe(VRegister rd, VRegister rm) { Vcmpe(al, rd, rm); }
12828 void Vdiv(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12829 VIXL_ASSERT(rd.IsS() || rd.IsD());
12830 VIXL_ASSERT(rd.GetType() == rn.GetType());
12831 VIXL_ASSERT(rd.GetType() == rm.GetType());
12832 if (rd.IsS()) {
12833 Vdiv(cond, F32, rd.S(), rn.S(), rm.S());
12835 Vdiv(cond, F64, rd.D(), rn.D(), rm.D());
12838 void Vdiv(VRegister rd, VRegister rn, VRegister rm) { Vdiv(al, rd, rn, rm); }
12839 void Vfma(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12840 VIXL_ASSERT(rd.IsS() || rd.IsD());
12841 VIXL_ASSERT(rd.GetType() == rn.GetType());
12842 VIXL_ASSERT(rd.GetType() == rm.GetType());
12843 if (rd.IsS()) {
12844 Vfma(cond, F32, rd.S(), rn.S(), rm.S());
12846 Vfma(cond, F64, rd.D(), rn.D(), rm.D());
12849 void Vfma(VRegister rd, VRegister rn, VRegister rm) { Vfma(al, rd, rn, rm); }
12850 void Vfms(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12851 VIXL_ASSERT(rd.IsS() || rd.IsD());
12852 VIXL_ASSERT(rd.GetType() == rn.GetType());
12853 VIXL_ASSERT(rd.GetType() == rm.GetType());
12854 if (rd.IsS()) {
12855 Vfms(cond, F32, rd.S(), rn.S(), rm.S());
12857 Vfms(cond, F64, rd.D(), rn.D(), rm.D());
12860 void Vfms(VRegister rd, VRegister rn, VRegister rm) { Vfms(al, rd, rn, rm); }
12861 void Vfnma(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12862 VIXL_ASSERT(rd.IsS() || rd.IsD());
12863 VIXL_ASSERT(rd.GetType() == rn.GetType());
12864 VIXL_ASSERT(rd.GetType() == rm.GetType());
12865 if (rd.IsS()) {
12866 Vfnma(cond, F32, rd.S(), rn.S(), rm.S());
12868 Vfnma(cond, F64, rd.D(), rn.D(), rm.D());
12871 void Vfnma(VRegister rd, VRegister rn, VRegister rm) {
12872 Vfnma(al, rd, rn, rm);
12874 void Vfnms(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12875 VIXL_ASSERT(rd.IsS() || rd.IsD());
12876 VIXL_ASSERT(rd.GetType() == rn.GetType());
12877 VIXL_ASSERT(rd.GetType() == rm.GetType());
12878 if (rd.IsS()) {
12879 Vfnms(cond, F32, rd.S(), rn.S(), rm.S());
12881 Vfnms(cond, F64, rd.D(), rn.D(), rm.D());
12884 void Vfnms(VRegister rd, VRegister rn, VRegister rm) {
12885 Vfnms(al, rd, rn, rm);
12887 void Vmaxnm(VRegister rd, VRegister rn, VRegister rm) {
12888 VIXL_ASSERT(rd.IsS() || rd.IsD());
12889 VIXL_ASSERT(rd.GetType() == rn.GetType());
12890 VIXL_ASSERT(rd.GetType() == rm.GetType());
12891 if (rd.IsS()) {
12892 Vmaxnm(F32, rd.S(), rn.S(), rm.S());
12894 Vmaxnm(F64, rd.D(), rn.D(), rm.D());
12897 void Vminnm(VRegister rd, VRegister rn, VRegister rm) {
12898 VIXL_ASSERT(rd.IsS() || rd.IsD());
12899 VIXL_ASSERT(rd.GetType() == rn.GetType());
12900 VIXL_ASSERT(rd.GetType() == rm.GetType());
12901 if (rd.IsS()) {
12902 Vminnm(F32, rd.S(), rn.S(), rm.S());
12904 Vminnm(F64, rd.D(), rn.D(), rm.D());
12907 void Vmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12908 VIXL_ASSERT(rd.IsS() || rd.IsD());
12909 VIXL_ASSERT(rd.GetType() == rn.GetType());
12910 VIXL_ASSERT(rd.GetType() == rm.GetType());
12911 if (rd.IsS()) {
12912 Vmla(cond, F32, rd.S(), rn.S(), rm.S());
12914 Vmla(cond, F64, rd.D(), rn.D(), rm.D());
12917 void Vmla(VRegister rd, VRegister rn, VRegister rm) { Vmla(al, rd, rn, rm); }
12918 void Vmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12919 VIXL_ASSERT(rd.IsS() || rd.IsD());
12920 VIXL_ASSERT(rd.GetType() == rn.GetType());
12921 VIXL_ASSERT(rd.GetType() == rm.GetType());
12922 if (rd.IsS()) {
12923 Vmls(cond, F32, rd.S(), rn.S(), rm.S());
12925 Vmls(cond, F64, rd.D(), rn.D(), rm.D());
12928 void Vmls(VRegister rd, VRegister rn, VRegister rm) { Vmls(al, rd, rn, rm); }
12929 void Vmov(Condition cond, VRegister rd, VRegister rm) {
12930 VIXL_ASSERT(rd.IsS() || rd.IsD());
12931 VIXL_ASSERT(rd.GetType() == rm.GetType());
12932 if (rd.IsS()) {
12933 Vmov(cond, F32, rd.S(), rm.S());
12935 Vmov(cond, F64, rd.D(), rm.D());
12938 void Vmov(VRegister rd, VRegister rm) { Vmov(al, rd, rm); }
12939 void Vmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12940 VIXL_ASSERT(rd.IsS() || rd.IsD());
12941 VIXL_ASSERT(rd.GetType() == rn.GetType());
12942 VIXL_ASSERT(rd.GetType() == rm.GetType());
12943 if (rd.IsS()) {
12944 Vmul(cond, F32, rd.S(), rn.S(), rm.S());
12946 Vmul(cond, F64, rd.D(), rn.D(), rm.D());
12949 void Vmul(VRegister rd, VRegister rn, VRegister rm) { Vmul(al, rd, rn, rm); }
12950 void Vneg(Condition cond, VRegister rd, VRegister rm) {
12951 VIXL_ASSERT(rd.IsS() || rd.IsD());
12952 VIXL_ASSERT(rd.GetType() == rm.GetType());
12953 if (rd.IsS()) {
12954 Vneg(cond, F32, rd.S(), rm.S());
12956 Vneg(cond, F64, rd.D(), rm.D());
12959 void Vneg(VRegister rd, VRegister rm) { Vneg(al, rd, rm); }
12960 void Vnmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12961 VIXL_ASSERT(rd.IsS() || rd.IsD());
12962 VIXL_ASSERT(rd.GetType() == rn.GetType());
12963 VIXL_ASSERT(rd.GetType() == rm.GetType());
12964 if (rd.IsS()) {
12965 Vnmla(cond, F32, rd.S(), rn.S(), rm.S());
12967 Vnmla(cond, F64, rd.D(), rn.D(), rm.D());
12970 void Vnmla(VRegister rd, VRegister rn, VRegister rm) {
12971 Vnmla(al, rd, rn, rm);
12973 void Vnmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12974 VIXL_ASSERT(rd.IsS() || rd.IsD());
12975 VIXL_ASSERT(rd.GetType() == rn.GetType());
12976 VIXL_ASSERT(rd.GetType() == rm.GetType());
12977 if (rd.IsS()) {
12978 Vnmls(cond, F32, rd.S(), rn.S(), rm.S());
12980 Vnmls(cond, F64, rd.D(), rn.D(), rm.D());
12983 void Vnmls(VRegister rd, VRegister rn, VRegister rm) {
12984 Vnmls(al, rd, rn, rm);
12986 void Vnmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
12987 VIXL_ASSERT(rd.IsS() || rd.IsD());
12988 VIXL_ASSERT(rd.GetType() == rn.GetType());
12989 VIXL_ASSERT(rd.GetType() == rm.GetType());
12990 if (rd.IsS()) {
12991 Vnmul(cond, F32, rd.S(), rn.S(), rm.S());
12993 Vnmul(cond, F64, rd.D(), rn.D(), rm.D());
12996 void Vnmul(VRegister rd, VRegister rn, VRegister rm) {
12997 Vnmul(al, rd, rn, rm);
12999 void Vrinta(VRegister rd, VRegister rm) {
13000 VIXL_ASSERT(rd.IsS() || rd.IsD());
13001 VIXL_ASSERT(rd.GetType() == rm.GetType());
13002 if (rd.IsS()) {
13003 Vrinta(F32, rd.S(), rm.S());
13005 Vrinta(F64, rd.D(), rm.D());
13008 void Vrintm(VRegister rd, VRegister rm) {
13009 VIXL_ASSERT(rd.IsS() || rd.IsD());
13010 VIXL_ASSERT(rd.GetType() == rm.GetType());
13011 if (rd.IsS()) {
13012 Vrintm(F32, rd.S(), rm.S());
13014 Vrintm(F64, rd.D(), rm.D());
13017 void Vrintn(VRegister rd, VRegister rm) {
13018 VIXL_ASSERT(rd.IsS() || rd.IsD());
13019 VIXL_ASSERT(rd.GetType() == rm.GetType());
13020 if (rd.IsS()) {
13021 Vrintn(F32, rd.S(), rm.S());
13023 Vrintn(F64, rd.D(), rm.D());
13026 void Vrintp(VRegister rd, VRegister rm) {
13027 VIXL_ASSERT(rd.IsS() || rd.IsD());
13028 VIXL_ASSERT(rd.GetType() == rm.GetType());
13029 if (rd.IsS()) {
13030 Vrintp(F32, rd.S(), rm.S());
13032 Vrintp(F64, rd.D(), rm.D());
13035 void Vrintr(Condition cond, VRegister rd, VRegister rm) {
13036 VIXL_ASSERT(rd.IsS() || rd.IsD());
13037 VIXL_ASSERT(rd.GetType() == rm.GetType());
13038 if (rd.IsS()) {
13039 Vrintr(cond, F32, rd.S(), rm.S());
13041 Vrintr(cond, F64, rd.D(), rm.D());
13044 void Vrintr(VRegister rd, VRegister rm) { Vrintr(al, rd, rm); }
13045 void Vrintx(Condition cond, VRegister rd, VRegister rm) {
13046 VIXL_ASSERT(rd.IsS() || rd.IsD());
13047 VIXL_ASSERT(rd.GetType() == rm.GetType());
13048 if (rd.IsS()) {
13049 Vrintx(cond, F32, rd.S(), rm.S());
13051 Vrintx(cond, F64, rd.D(), rm.D());
13054 void Vrintx(VRegister rd, VRegister rm) { Vrintx(al, rd, rm); }
13055 void Vrintz(Condition cond, VRegister rd, VRegister rm) {
13056 VIXL_ASSERT(rd.IsS() || rd.IsD());
13057 VIXL_ASSERT(rd.GetType() == rm.GetType());
13058 if (rd.IsS()) {
13059 Vrintz(cond, F32, rd.S(), rm.S());
13061 Vrintz(cond, F64, rd.D(), rm.D());
13064 void Vrintz(VRegister rd, VRegister rm) { Vrintz(al, rd, rm); }
13065 void Vseleq(VRegister rd, VRegister rn, VRegister rm) {
13066 VIXL_ASSERT(rd.IsS() || rd.IsD());
13067 VIXL_ASSERT(rd.GetType() == rn.GetType());
13068 VIXL_ASSERT(rd.GetType() == rm.GetType());
13069 if (rd.IsS()) {
13070 Vseleq(F32, rd.S(), rn.S(), rm.S());
13072 Vseleq(F64, rd.D(), rn.D(), rm.D());
13075 void Vselge(VRegister rd, VRegister rn, VRegister rm) {
13076 VIXL_ASSERT(rd.IsS() || rd.IsD());
13077 VIXL_ASSERT(rd.GetType() == rn.GetType());
13078 VIXL_ASSERT(rd.GetType() == rm.GetType());
13079 if (rd.IsS()) {
13080 Vselge(F32, rd.S(), rn.S(), rm.S());
13082 Vselge(F64, rd.D(), rn.D(), rm.D());
13085 void Vselgt(VRegister rd, VRegister rn, VRegister rm) {
13086 VIXL_ASSERT(rd.IsS() || rd.IsD());
13087 VIXL_ASSERT(rd.GetType() == rn.GetType());
13088 VIXL_ASSERT(rd.GetType() == rm.GetType());
13089 if (rd.IsS()) {
13090 Vselgt(F32, rd.S(), rn.S(), rm.S());
13092 Vselgt(F64, rd.D(), rn.D(), rm.D());
13095 void Vselvs(VRegister rd, VRegister rn, VRegister rm) {
13096 VIXL_ASSERT(rd.IsS() || rd.IsD());
13097 VIXL_ASSERT(rd.GetType() == rn.GetType());
13098 VIXL_ASSERT(rd.GetType() == rm.GetType());
13099 if (rd.IsS()) {
13100 Vselvs(F32, rd.S(), rn.S(), rm.S());
13102 Vselvs(F64, rd.D(), rn.D(), rm.D());
13105 void Vsqrt(Condition cond, VRegister rd, VRegister rm) {
13106 VIXL_ASSERT(rd.IsS() || rd.IsD());
13107 VIXL_ASSERT(rd.GetType() == rm.GetType());
13108 if (rd.IsS()) {
13109 Vsqrt(cond, F32, rd.S(), rm.S());
13111 Vsqrt(cond, F64, rd.D(), rm.D());
13114 void Vsqrt(VRegister rd, VRegister rm) { Vsqrt(al, rd, rm); }
13115 void Vsub(Condition cond, VRegister rd, VRegister rn, VRegister rm) {
13116 VIXL_ASSERT(rd.IsS() || rd.IsD());
13117 VIXL_ASSERT(rd.GetType() == rn.GetType());
13118 VIXL_ASSERT(rd.GetType() == rm.GetType());
13119 if (rd.IsS()) {
13120 Vsub(cond, F32, rd.S(), rn.S(), rm.S());
13122 Vsub(cond, F64, rd.D(), rn.D(), rm.D());
13125 void Vsub(VRegister rd, VRegister rn, VRegister rm) { Vsub(al, rd, rn, rm); }
13139 "void Vrinta(DataType dt, DRegister rd, DRegister rm)",
13140 void Vrinta(DataType dt1, DataType dt2, DRegister rd, DRegister rm)) {
13143 return Vrinta(dt1, rd, rm);
13146 "void Vrinta(DataType dt, QRegister rd, QRegister rm)",
13147 void Vrinta(DataType dt1, DataType dt2, QRegister rd, QRegister rm)) {
13150 return Vrinta(dt1, rd, rm);
13153 "void Vrinta(DataType dt, SRegister rd, SRegister rm)",
13154 void Vrinta(DataType dt1, DataType dt2, SRegister rd, SRegister rm)) {
13157 return Vrinta(dt1, rd, rm);
13161 "void Vrintm(DataType dt, DRegister rd, DRegister rm)",
13162 void Vrintm(DataType dt1, DataType dt2, DRegister rd, DRegister rm)) {
13165 return Vrintm(dt1, rd, rm);
13168 "void Vrintm(DataType dt, QRegister rd, QRegister rm)",
13169 void Vrintm(DataType dt1, DataType dt2, QRegister rd, QRegister rm)) {
13172 return Vrintm(dt1, rd, rm);
13175 "void Vrintm(DataType dt, SRegister rd, SRegister rm)",
13176 void Vrintm(DataType dt1, DataType dt2, SRegister rd, SRegister rm)) {
13179 return Vrintm(dt1, rd, rm);
13183 "void Vrintn(DataType dt, DRegister rd, DRegister rm)",
13184 void Vrintn(DataType dt1, DataType dt2, DRegister rd, DRegister rm)) {
13187 return Vrintn(dt1, rd, rm);
13190 "void Vrintn(DataType dt, QRegister rd, QRegister rm)",
13191 void Vrintn(DataType dt1, DataType dt2, QRegister rd, QRegister rm)) {
13194 return Vrintn(dt1, rd, rm);
13197 "void Vrintn(DataType dt, SRegister rd, SRegister rm)",
13198 void Vrintn(DataType dt1, DataType dt2, SRegister rd, SRegister rm)) {
13201 return Vrintn(dt1, rd, rm);
13205 "void Vrintp(DataType dt, DRegister rd, DRegister rm)",
13206 void Vrintp(DataType dt1, DataType dt2, DRegister rd, DRegister rm)) {
13209 return Vrintp(dt1, rd, rm);
13212 "void Vrintp(DataType dt, QRegister rd, QRegister rm)",
13213 void Vrintp(DataType dt1, DataType dt2, QRegister rd, QRegister rm)) {
13216 return Vrintp(dt1, rd, rm);
13219 "void Vrintp(DataType dt, SRegister rd, SRegister rm)",
13220 void Vrintp(DataType dt1, DataType dt2, SRegister rd, SRegister rm)) {
13223 return Vrintp(dt1, rd, rm);
13227 "void Vrintr(Condition cond, DataType dt, SRegister rd, SRegister rm)",
13231 SRegister rd,
13235 return Vrintr(cond, dt1, rd, rm);
13238 "void Vrintr(DataType dt, SRegister rd, SRegister rm)",
13239 void Vrintr(DataType dt1, DataType dt2, SRegister rd, SRegister rm)) {
13242 return Vrintr(dt1, rd, rm);
13246 "void Vrintr(Condition cond, DataType dt, DRegister rd, DRegister rm)",
13250 DRegister rd,
13254 return Vrintr(cond, dt1, rd, rm);
13257 "void Vrintr(DataType dt, DRegister rd, DRegister rm)",
13258 void Vrintr(DataType dt1, DataType dt2, DRegister rd, DRegister rm)) {
13261 return Vrintr(dt1, rd, rm);
13265 "void Vrintx(Condition cond, DataType dt, DRegister rd, DRegister rm)",
13269 DRegister rd,
13273 return Vrintx(cond, dt1, rd, rm);
13276 "void Vrintx(DataType dt, DRegister rd, DRegister rm)",
13277 void Vrintx(DataType dt1, DataType dt2, DRegister rd, DRegister rm)) {
13280 return Vrintx(dt1, rd, rm);
13284 "void Vrintx(DataType dt, QRegister rd, QRegister rm)",
13285 void Vrintx(DataType dt1, DataType dt2, QRegister rd, QRegister rm)) {
13288 return Vrintx(dt1, rd, rm);
13292 "void Vrintx(Condition cond, DataType dt, SRegister rd, SRegister rm)",
13296 SRegister rd,
13300 return Vrintx(cond, dt1, rd, rm);
13303 "void Vrintx(DataType dt, SRegister rd, SRegister rm)",
13304 void Vrintx(DataType dt1, DataType dt2, SRegister rd, SRegister rm)) {
13307 return Vrintx(dt1, rd, rm);
13311 "void Vrintz(Condition cond, DataType dt, DRegister rd, DRegister rm)",
13315 DRegister rd,
13319 return Vrintz(cond, dt1, rd, rm);
13322 "void Vrintz(DataType dt, DRegister rd, DRegister rm)",
13323 void Vrintz(DataType dt1, DataType dt2, DRegister rd, DRegister rm)) {
13326 return Vrintz(dt1, rd, rm);
13330 "void Vrintz(DataType dt, QRegister rd, QRegister rm)",
13331 void Vrintz(DataType dt1, DataType dt2, QRegister rd, QRegister rm)) {
13334 return Vrintz(dt1, rd, rm);
13338 "void Vrintz(Condition cond, DataType dt, SRegister rd, SRegister rm)",
13342 SRegister rd,
13346 return Vrintz(cond, dt1, rd, rm);
13349 "void Vrintz(DataType dt, SRegister rd, SRegister rm)",
13350 void Vrintz(DataType dt1, DataType dt2, SRegister rd, SRegister rm)) {
13353 return Vrintz(dt1, rd, rm);