Lines Matching refs:rn
680 Register rn,
696 teq(cond, rn, scratch);
699 Assembler::Delegate(type, instruction, cond, rn, operand);
707 Register rn,
746 (this->*instruction)(cond, size, rn, scratch);
755 if (!rn.IsPC()) {
757 HandleOutOfBoundsImmediate(cond, rn, imm);
760 tst(cond, rn, rn);
777 if (IsUsingA32() || !rn.IsPC()) {
782 (this->*instruction)(cond, size, rn, scratch);
788 if (!rn.IsPC()) {
793 (this->*instruction)(cond, size, rn, scratch);
798 if (IsUsingA32() || !rn.IsPC()) {
803 (this->*instruction)(cond, size, rn, scratch);
811 Assembler::Delegate(type, instruction, cond, size, rn, operand);
819 Register rn,
861 // rm (because we read them in the first instruction), but not rn.
862 if (!rd.Is(rn)) temps.Include(rd);
868 (this->*instruction)(cond, rd, rn, scratch);
875 // adc rd, rn, operand <-> rsc rd, NOT(rn), operand
880 // Try to use rd as a scratch register. We can do this if it aliases rn
887 mvn(cond, negated_rn, rn);
910 orr(cond, rd, rn, ~imm);
913 orrs(cond, rd, rn, ~imm);
931 // rm (because we read them in the first instruction), but not rn.
932 if (!rd.Is(rn)) temps.Include(rd);
942 orrs(cond, rd, rn, scratch);
946 orr(cond, rd, rn, scratch);
953 if (!rd.Is(rn)) temps.Include(rd);
958 (this->*instruction)(cond, rd, rn, scratch);
961 Assembler::Delegate(type, instruction, cond, rd, rn, operand);
993 Register rn,
997 if (!IsModifiedImmediate(high) && !rn.IsPC()) return false;
1000 // Else, if rn is PC, we want to avoid moving PC into a temporary.
1005 (rn.IsPC() ? 4 : 2) * kMaxInstructionSizeInBytes);
1006 (this->*instruction)(cond, Best, rd, rn, low);
1017 Register rn,
1057 // rm (because we read them in the first instruction), but not rn.
1058 if (!rd.Is(rn)) temps.Include(rd);
1062 (this->*instruction)(cond, size, rd, rn, scratch);
1072 orn(cond, rd, rn, ~imm);
1075 orns(cond, rd, rn, ~imm);
1085 // add rd, rn, #imm <-> sub rd, rn, - #imm
1087 // adc rd, rn, #imm <-> sbc rd, rn, NOT #imm
1126 (this->*asmcb)(cond, size, rd, rn, Operand(imm));
1131 // When rn is PC, only handle negative offsets. The correct way to handle
1137 if ((((type == kAdd) && !rn.IsPC()) || (type == kSub)) &&
1138 (IsUsingA32() || (!rd.IsPC() && !rn.IsPC()))) {
1147 if (GenerateSplitInstruction(instruction, cond, rd, rn, imm, mask)) {
1161 if (GenerateSplitInstruction(asmcb, cond, rd, rn, -imm, mask)) {
1168 if (!rd.Is(rn)) temps.Include(rd);
1169 if (rn.IsPC()) {
1201 rn = temps.Acquire();
1203 mov(cond, rn, pc);
1208 (this->*instruction)(cond, size, rd, rn, operand);
1217 (this->*instruction)(cond, size, rd, rn, scratch);
1221 Assembler::Delegate(type, instruction, cond, size, rd, rn, operand);
1227 Register rn,
1239 } else if (rn.IsLow()) {
1247 cbz(rn, &done);
1258 cbnz(rn, &done);
1267 Assembler::Delegate(type, instruction, rn, location);
1732 const Register& rn = operand.GetBaseRegister();
1748 if (!rn.Is(rd)) {
1755 add(cond, rn, rn, add_offset);
1762 MemOperand(rn, load_store_offset, PreIndex));
1771 !rd.Is(rn)) {
1781 add(cond, scratch, rn, add_offset);
1794 if (!rn.Is(rd)) {
1806 MemOperand(rn, load_store_offset, PostIndex));
1810 add(cond, rn, rn, add_offset);
1817 const Register& rn = operand.GetBaseRegister();
1825 if (rn.IsPC()) {
1841 if (!rn.Is(rd)) {
1849 add(cond, rn, rn, rm);
1851 sub(cond, rn, rn, rm);
1856 (this->*instruction)(cond, size, rd, MemOperand(rn, Offset));
1878 add(cond, scratch, rn, rm);
1880 sub(cond, scratch, rn, rm);
1891 if (!rn.Is(rd)) {
1898 (this->*instruction)(cond, size, rd, MemOperand(rn, Offset));
1903 add(cond, rn, rn, rm);
1905 sub(cond, rn, rn, rm);
1954 const Register& rn = operand.GetBaseRegister();
1972 if (!rt.Is(rn)) temps.Include(rt);
1973 if (!rt2.Is(rn)) temps.Include(rt2);
1982 add(cond, rn, rn, add_offset);
1989 MemOperand(rn, load_store_offset, PreIndex));
1997 if (!rt.Is(rn)) temps.Include(rt);
1998 if (!rt2.Is(rn)) temps.Include(rt2);
2007 add(cond, scratch, rn, add_offset);
2020 if (!rn.Is(rt) && !rn.Is(rt2)) {
2032 MemOperand(rn, load_store_offset, PostIndex));
2036 add(cond, rn, rn, add_offset);
2044 const Register& rn = operand.GetBaseRegister();
2055 add(cond, rn, rn, rm);
2057 sub(cond, rn, rn, rm);
2062 (this->*instruction)(cond, rt, rt2, MemOperand(rn, Offset));
2071 (this->*instruction)(cond, rt, rt2, MemOperand(rn, Offset));
2076 add(cond, rn, rn, rm);
2078 sub(cond, rn, rn, rm);
2086 if (!rt.Is(rn)) temps.Include(rt);
2087 if (!rt2.Is(rn)) temps.Include(rt2);
2097 add(cond, scratch, rn, rm);
2099 sub(cond, scratch, rn, rm);
2122 const Register& rn = operand.GetBaseRegister();
2127 if (rn.IsPC()) {
2140 add(cond, rn, rn, offset);
2144 (this->*instruction)(cond, dt, rd, MemOperand(rn, Offset));
2157 add(cond, scratch, rn, offset);
2174 (this->*instruction)(cond, dt, rd, MemOperand(rn, Offset));
2178 add(cond, rn, rn, offset);
2195 const Register& rn = operand.GetBaseRegister();
2200 if (rn.IsPC()) {
2213 add(cond, rn, rn, offset);
2217 (this->*instruction)(cond, dt, rd, MemOperand(rn, Offset));
2230 add(cond, scratch, rn, offset);
2247 (this->*instruction)(cond, dt, rd, MemOperand(rn, Offset));
2251 add(cond, rn, rn, offset);