Lines Matching refs:operand
190 void UseScratchRegisterScope::Exclude(const Operand& operand) {
191 if (operand.IsImmediateShiftedRegister()) {
192 Exclude(operand.GetBaseRegister());
193 } else if (operand.IsRegisterShiftedRegister()) {
194 Exclude(operand.GetBaseRegister(), operand.GetShiftRegister());
196 VIXL_ASSERT(operand.IsImmediate());
681 const Operand& operand) {
691 if ((type == kTeq) && operand.IsImmediate()) {
694 HandleOutOfBoundsImmediate(cond, scratch, operand.GetImmediate());
699 Assembler::Delegate(type, instruction, cond, rn, operand);
708 const Operand& operand) {
715 if (IsUsingT32() && operand.IsRegisterShiftedRegister()) {
718 switch (operand.GetShift().GetType()) {
729 // A RegisterShiftedRegister operand cannot have a shift of type RRX.
744 operand.GetBaseRegister(),
745 operand.GetShiftRegister());
750 if (operand.IsImmediate()) {
751 uint32_t imm = operand.GetImmediate();
811 Assembler::Delegate(type, instruction, cond, size, rn, operand);
820 const Operand& operand) {
834 if (IsUsingT32() && operand.IsRegisterShiftedRegister()) {
836 switch (operand.GetShift().GetType()) {
847 // A RegisterShiftedRegister operand cannot have a shift of type RRX.
858 Register rm = operand.GetBaseRegister();
859 Register rs = operand.GetShiftRegister();
875 // adc rd, rn, operand <-> rsc rd, NOT(rn), operand
878 VIXL_ASSERT(!operand.IsRegisterShiftedRegister());
883 temps.Exclude(operand);
891 adc(cond, rd, negated_rn, operand);
897 adcs(cond, rd, negated_rn, operand);
901 if (operand.IsImmediate()) {
905 int32_t imm = operand.GetSignedImmediate();
938 mvn(cond, scratch, operand);
950 if (operand.IsImmediate()) {
955 int32_t imm = operand.GetSignedImmediate();
961 Assembler::Delegate(type, instruction, cond, rd, rn, operand);
1018 const Operand& operand) {
1030 if (IsUsingT32() && operand.IsRegisterShiftedRegister()) {
1032 switch (operand.GetShift().GetType()) {
1043 // A RegisterShiftedRegister operand cannot have a shift of type RRX.
1054 Register rm = operand.GetBaseRegister();
1055 Register rs = operand.GetShiftRegister();
1066 if (operand.IsImmediate()) {
1067 int32_t imm = operand.GetSignedImmediate();
1208 (this->*instruction)(cond, size, rd, rn, operand);
1216 mov(cond, scratch, operand.GetImmediate());
1221 Assembler::Delegate(type, instruction, cond, size, rd, rn, operand);
1340 const SOperand& operand) {
1343 if (operand.IsImmediate() && dt.Is(F32)) {
1344 const NeonImmediate& neon_imm = operand.GetNeonImmediate();
1362 Assembler::Delegate(type, instruction, cond, dt, rd, operand);
1371 const DOperand& operand) {
1374 if (operand.IsImmediate()) {
1375 const NeonImmediate& neon_imm = operand.GetNeonImmediate();
1508 Assembler::Delegate(type, instruction, cond, dt, rd, operand);
1517 const QOperand& operand) {
1520 if (operand.IsImmediate()) {
1521 const NeonImmediate& neon_imm = operand.GetNeonImmediate();
1653 Assembler::Delegate(type, instruction, cond, dt, rd, operand);
1725 const MemOperand& operand) {
1731 if (operand.IsImmediate()) {
1732 const Register& rn = operand.GetBaseRegister();
1733 AddrMode addrmode = operand.GetAddrMode();
1734 int32_t offset = operand.GetOffsetImmediate();
1816 } else if (operand.IsPlainRegister()) {
1817 const Register& rn = operand.GetBaseRegister();
1818 AddrMode addrmode = operand.GetAddrMode();
1819 const Register& rm = operand.GetOffsetRegister();
1848 if (operand.GetSign().IsPlus()) {
1877 if (operand.GetSign().IsPlus()) {
1902 if (operand.GetSign().IsPlus()) {
1913 Assembler::Delegate(type, instruction, cond, size, rd, operand);
1922 const MemOperand& operand) {
1953 if (operand.IsImmediate()) {
1954 const Register& rn = operand.GetBaseRegister();
1955 AddrMode addrmode = operand.GetAddrMode();
1956 int32_t offset = operand.GetOffsetImmediate();
2043 if (operand.IsPlainRegister()) {
2044 const Register& rn = operand.GetBaseRegister();
2045 const Register& rm = operand.GetOffsetRegister();
2046 AddrMode addrmode = operand.GetAddrMode();
2054 if (operand.GetSign().IsPlus()) {
2075 if (operand.GetSign().IsPlus()) {
2096 if (operand.GetSign().IsPlus()) {
2110 Assembler::Delegate(type, instruction, cond, rt, rt2, operand);
2119 const MemOperand& operand) {
2121 if (operand.IsImmediate()) {
2122 const Register& rn = operand.GetBaseRegister();
2123 AddrMode addrmode = operand.GetAddrMode();
2124 int32_t offset = operand.GetOffsetImmediate();
2125 VIXL_ASSERT(((offset > 0) && operand.GetSign().IsPlus()) ||
2126 ((offset < 0) && operand.GetSign().IsMinus()) || (offset == 0));
2183 Assembler::Delegate(type, instruction, cond, dt, rd, operand);
2192 const MemOperand& operand) {
2194 if (operand.IsImmediate()) {
2195 const Register& rn = operand.GetBaseRegister();
2196 AddrMode addrmode = operand.GetAddrMode();
2197 int32_t offset = operand.GetOffsetImmediate();
2198 VIXL_ASSERT(((offset > 0) && operand.GetSign().IsPlus()) ||
2199 ((offset < 0) && operand.GetSign().IsMinus()) || (offset == 0));
2256 Assembler::Delegate(type, instruction, cond, dt, rd, operand);
2264 const Operand& operand) {
2267 if (operand.IsImmediate()) {
2272 mov(cond, scratch, operand);
2278 Assembler::Delegate(type, instruction, cond, spec_reg, operand);