Lines Matching refs:lane
226 SRegister GetLane(uint32_t lane) const {
228 VIXL_ASSERT(lane < lane_count);
230 return SRegister(GetCode() * lane_count + lane);
329 DRegisterLane(DRegister reg, uint32_t lane)
330 : DRegister(reg.GetCode()), lane_(lane) {}
331 DRegisterLane(uint32_t code, uint32_t lane) : DRegister(code), lane_(lane) {}
347 int* lane) {
352 *lane = value >> 3;
355 *lane = value >> 4;
359 inline std::ostream& operator<<(std::ostream& os, const DRegisterLane lane) {
360 os << "d" << lane.GetCode() << "[";
361 if (lane.GetLane() == static_cast<uint32_t>(-1)) return os << "??]";
362 return os << lane.GetLane() << "]";
371 DRegister GetDLane(uint32_t lane) const {
373 VIXL_ASSERT(lane < lane_count);
374 return DRegister(GetCode() * lane_count + lane);
378 SRegister GetSLane(uint32_t lane) const {
380 VIXL_ASSERT(lane < lane_count);
382 return SRegister(GetCode() * lane_count + lane);
714 NeonRegisterList(DRegister reg, int lane)
718 lane_(lane),
739 int lane)
743 lane_(lane) {
744 VIXL_ASSERT((lane >= 0) && (lane < 8));