Lines Matching refs:rn
1926 Register rn,
1936 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
1937 EmitT32_32(0xf1400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
1949 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
1960 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
1973 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
1975 EmitT32_32(0xeb400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
1986 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
1999 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2002 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2008 Delegate(kAdc, &Assembler::adc, cond, size, rd, rn, operand);
2014 Register rn,
2024 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
2025 EmitT32_32(0xf1500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2037 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
2048 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
2061 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2063 EmitT32_32(0xeb500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2074 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2087 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2090 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2096 Delegate(kAdcs, &Assembler::adcs, cond, size, rd, rn, operand);
2102 Register rn,
2111 if (!size.IsWide() && rd.IsLow() && rn.Is(pc) && (imm <= 1020) &&
2119 if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
2121 EmitT32_16(0x1c00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6));
2126 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
2133 if (!size.IsWide() && rd.IsLow() && rn.Is(sp) && (imm <= 1020) &&
2141 if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && (imm <= 508) &&
2149 if (!size.IsNarrow() && rn.Is(pc) && (imm <= 4095) &&
2157 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(sp) &&
2158 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
2159 EmitT32_32(0xf1000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2167 if (!size.IsNarrow() && (imm <= 4095) && ((rn.GetCode() & 0xd) != 0xd) &&
2169 EmitT32_32(0xf2000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2175 if (!size.IsNarrow() && rn.Is(sp) && immediate_t32.IsValid() &&
2185 if (!size.IsNarrow() && rn.Is(sp) && (imm <= 4095) &&
2195 if (rn.Is(pc) && immediate_a32.IsValid() && cond.IsNotNever()) {
2202 ((rn.GetCode() & 0xd) != 0xd)) {
2204 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
2209 if (rn.Is(sp) && immediate_a32.IsValid() && cond.IsNotNever()) {
2221 if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
2223 EmitT32_16(0x1800 | rd.GetCode() | (rn.GetCode() << 3) |
2229 if (!size.IsWide() && rd.Is(rn) && !rm.Is(sp) &&
2239 if (!size.IsWide() && rd.Is(rm) && rn.Is(sp) &&
2248 if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && !rm.Is(sp)) {
2259 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(sp) &&
2260 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2262 EmitT32_32(0xeb000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2269 if (!size.IsNarrow() && rn.Is(sp) && shift.IsValidAmount(amount) &&
2280 if (shift.IsValidAmount(amount) && cond.IsNotNever() && !rn.Is(sp)) {
2283 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2288 if (rn.Is(sp) && shift.IsValidAmount(amount) && cond.IsNotNever()) {
2304 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2307 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2313 Delegate(kAdd, &Assembler::add, cond, size, rd, rn, operand);
2351 Register rn,
2360 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
2362 EmitT32_16(0x1c00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6));
2367 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
2374 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(sp) &&
2375 !rd.Is(pc) && (!rn.IsPC() || AllowUnpredictable())) {
2376 EmitT32_32(0xf1100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2384 if (!size.IsNarrow() && rn.Is(sp) && immediate_t32.IsValid() &&
2396 if (immediate_a32.IsValid() && cond.IsNotNever() && !rn.Is(sp)) {
2398 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
2403 if (rn.Is(sp) && immediate_a32.IsValid() && cond.IsNotNever()) {
2415 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
2417 EmitT32_16(0x1800 | rd.GetCode() | (rn.GetCode() << 3) |
2428 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(sp) &&
2429 !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2431 EmitT32_32(0xeb100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2438 if (!size.IsNarrow() && rn.Is(sp) && shift.IsValidAmount(amount) &&
2449 if (shift.IsValidAmount(amount) && cond.IsNotNever() && !rn.Is(sp)) {
2452 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2457 if (rn.Is(sp) && shift.IsValidAmount(amount) && cond.IsNotNever()) {
2473 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2476 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2482 Delegate(kAdds, &Assembler::adds, cond, size, rd, rn, operand);
2504 Register rn,
2512 if (rn.Is(pc) && (imm <= 4095) && (!rd.IsPC() || AllowUnpredictable())) {
2519 if ((imm <= 4095) && ((rn.GetCode() & 0xd) != 0xd) &&
2521 EmitT32_32(0xf2000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2527 if (rn.Is(sp) && (imm <= 4095) && (!rd.IsPC() || AllowUnpredictable())) {
2535 Delegate(kAddw, &Assembler::addw, cond, rd, rn, operand);
2700 Register rn,
2710 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
2711 EmitT32_32(0xf0000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2723 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
2734 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
2747 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2749 EmitT32_32(0xea000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2760 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2773 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2776 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2782 Delegate(kAnd, &Assembler::and_, cond, size, rd, rn, operand);
2788 Register rn,
2798 (!rn.IsPC() || AllowUnpredictable())) {
2799 EmitT32_32(0xf0100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2811 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
2822 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
2835 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2837 EmitT32_32(0xea100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
2848 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2861 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2864 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2870 Delegate(kAnds, &Assembler::ands, cond, size, rd, rn, operand);
3222 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
3227 if ((lsb <= 31) && !rn.Is(pc) &&
3231 EmitT32_32(0xf3600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
3238 if ((lsb <= 31) && cond.IsNotNever() && !rn.Is(pc) &&
3243 rn.GetCode() | (lsb << 7) | (msb << 16));
3247 Delegate(kBfi, &Assembler::bfi, cond, rd, rn, lsb, width);
3253 Register rn,
3263 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
3264 EmitT32_32(0xf0200000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
3276 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
3287 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
3300 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3302 EmitT32_32(0xea200000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
3313 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3326 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
3329 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3335 Delegate(kBic, &Assembler::bic, cond, size, rd, rn, operand);
3341 Register rn,
3351 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
3352 EmitT32_32(0xf0300000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
3364 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
3375 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
3388 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3390 EmitT32_32(0xea300000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
3401 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3414 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
3417 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3423 Delegate(kBics, &Assembler::bics, cond, size, rd, rn, operand);
3684 void Assembler::cbnz(Register rn, Location* location) {
3694 if (rn.IsLow() && ((location->IsBound() && (offset >= 0) &&
3710 EmitT32_16(Link(0xb900 | rn.GetCode(), location, immop, &kT16CbzInfo));
3715 Delegate(kCbnz, &Assembler::cbnz, rn, location);
3718 bool Assembler::cbnz_info(Register rn,
3725 if (rn.IsLow()) {
3733 void Assembler::cbz(Register rn, Location* location) {
3743 if (rn.IsLow() && ((location->IsBound() && (offset >= 0) &&
3759 EmitT32_16(Link(0xb100 | rn.GetCode(), location, immop, &kT16CbzInfo));
3764 Delegate(kCbz, &Assembler::cbz, rn, location);
3767 bool Assembler::cbz_info(Register rn,
3774 if (rn.IsLow()) {
3825 Register rn,
3835 (!rn.IsPC() || AllowUnpredictable())) {
3836 EmitT32_32(0xf1100f00U | (rn.GetCode() << 16) |
3848 (rn.GetCode() << 16) | immediate_a32.GetEncodingValue());
3858 if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {
3859 EmitT32_16(0x42c0 | rn.GetCode() | (rm.GetCode() << 3));
3870 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3872 EmitT32_32(0xeb100f00U | (rn.GetCode() << 16) | rm.GetCode() |
3883 (rn.GetCode() << 16) | rm.GetCode() |
3896 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
3898 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |
3904 Delegate(kCmn, &Assembler::cmn, cond, size, rn, operand);
3909 Register rn,
3918 if (!size.IsWide() && rn.IsLow() && (imm <= 255)) {
3919 EmitT32_16(0x2800 | (rn.GetCode() << 8) | imm);
3925 (!rn.IsPC() || AllowUnpredictable())) {
3926 EmitT32_32(0xf1b00f00U | (rn.GetCode() << 16) |
3938 (rn.GetCode() << 16) | immediate_a32.GetEncodingValue());
3948 if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {
3949 EmitT32_16(0x4280 | rn.GetCode() | (rm.GetCode() << 3));
3955 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3956 EmitT32_16(0x4500 | (rn.GetCode() & 0x7) |
3957 ((rn.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));
3968 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3970 EmitT32_32(0xebb00f00U | (rn.GetCode() << 16) | rm.GetCode() |
3981 (rn.GetCode() << 16) | rm.GetCode() |
3994 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
3996 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |
4002 Delegate(kCmp, &Assembler::cmp, cond, size, rn, operand);
4005 void Assembler::crc32b(Condition cond, Register rd, Register rn, Register rm) {
4010 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4012 EmitT32_32(0xfac0f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4020 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4022 (rn.GetCode() << 16) | rm.GetCode());
4026 Delegate(kCrc32b, &Assembler::crc32b, cond, rd, rn, rm);
4029 void Assembler::crc32cb(Condition cond, Register rd, Register rn, Register rm) {
4034 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4036 EmitT32_32(0xfad0f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4044 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4046 (rn.GetCode() << 16) | rm.GetCode());
4050 Delegate(kCrc32cb, &Assembler::crc32cb, cond, rd, rn, rm);
4053 void Assembler::crc32ch(Condition cond, Register rd, Register rn, Register rm) {
4058 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4060 EmitT32_32(0xfad0f090U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4068 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4070 (rn.GetCode() << 16) | rm.GetCode());
4074 Delegate(kCrc32ch, &Assembler::crc32ch, cond, rd, rn, rm);
4077 void Assembler::crc32cw(Condition cond, Register rd, Register rn, Register rm) {
4082 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4084 EmitT32_32(0xfad0f0a0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4092 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4094 (rn.GetCode() << 16) | rm.GetCode());
4098 Delegate(kCrc32cw, &Assembler::crc32cw, cond, rd, rn, rm);
4101 void Assembler::crc32h(Condition cond, Register rd, Register rn, Register rm) {
4106 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4108 EmitT32_32(0xfac0f090U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4116 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4118 (rn.GetCode() << 16) | rm.GetCode());
4122 Delegate(kCrc32h, &Assembler::crc32h, cond, rd, rn, rm);
4125 void Assembler::crc32w(Condition cond, Register rd, Register rn, Register rm) {
4130 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4132 EmitT32_32(0xfac0f0a0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4140 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4142 (rn.GetCode() << 16) | rm.GetCode());
4146 Delegate(kCrc32w, &Assembler::crc32w, cond, rd, rn, rm);
4188 Register rn,
4198 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4199 EmitT32_32(0xf0800000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4211 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
4222 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
4235 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4237 EmitT32_32(0xea800000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4248 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
4261 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
4264 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
4270 Delegate(kEor, &Assembler::eor, cond, size, rd, rn, operand);
4276 Register rn,
4286 (!rn.IsPC() || AllowUnpredictable())) {
4287 EmitT32_32(0xf0900000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4299 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
4310 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
4323 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4325 EmitT32_32(0xea900000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
4336 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
4349 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
4352 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
4358 Delegate(kEors, &Assembler::eors, cond, size, rd, rn, operand);
4362 Register rn,
4371 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) ||
4375 EmitT32_32(0xed300b01U | (rn.GetCode() << 16) | dreg.Encode(22, 12) |
4384 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) ||
4388 EmitA32(0x0d300b01U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4393 Delegate(kFldmdbx, &Assembler::fldmdbx, cond, rn, write_back, dreglist);
4397 Register rn,
4405 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) ||
4409 EmitT32_32(0xec900b01U | (rn.GetCode() << 16) |
4419 (!rn.IsPC() || !write_back.DoesWriteBack())) ||
4423 EmitA32(0x0c900b01U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4429 Delegate(kFldmiax, &Assembler::fldmiax, cond, rn, write_back, dreglist);
4433 Register rn,
4442 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) ||
4446 EmitT32_32(0xed200b01U | (rn.GetCode() << 16) | dreg.Encode(22, 12) |
4455 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) ||
4459 EmitA32(0x0d200b01U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4464 Delegate(kFstmdbx, &Assembler::fstmdbx, cond, rn, write_back, dreglist);
4468 Register rn,
4476 (dreglist.GetLastDRegister().GetCode() < 16) && !rn.IsPC()) ||
4480 EmitT32_32(0xec800b01U | (rn.GetCode() << 16) |
4490 (!rn.IsPC() || !write_back.DoesWriteBack())) ||
4494 EmitA32(0x0c800b01U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4500 Delegate(kFstmiax, &Assembler::fstmiax, cond, rn, write_back, dreglist);
4587 Register rn = operand.GetBaseRegister();
4591 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4592 EmitT32_32(0xe8d00fafU | (rt.GetCode() << 12) | (rn.GetCode() << 16));
4599 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4601 (rt.GetCode() << 12) | (rn.GetCode() << 16));
4613 Register rn = operand.GetBaseRegister();
4617 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4618 EmitT32_32(0xe8d00f8fU | (rt.GetCode() << 12) | (rn.GetCode() << 16));
4625 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4627 (rt.GetCode() << 12) | (rn.GetCode() << 16));
4639 Register rn = operand.GetBaseRegister();
4643 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4644 EmitT32_32(0xe8d00fefU | (rt.GetCode() << 12) | (rn.GetCode() << 16));
4651 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4653 (rt.GetCode() << 12) | (rn.GetCode() << 16));
4665 Register rn = operand.GetBaseRegister();
4669 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4670 EmitT32_32(0xe8d00fcfU | (rt.GetCode() << 12) | (rn.GetCode() << 16));
4677 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4679 (rt.GetCode() << 12) | (rn.GetCode() << 16));
4694 Register rn = operand.GetBaseRegister();
4698 ((!rt.IsPC() && !rt2.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4700 (rn.GetCode() << 16));
4708 ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rn.IsPC()) ||
4711 (rt.GetCode() << 12) | (rn.GetCode() << 16));
4723 Register rn = operand.GetBaseRegister();
4727 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4728 EmitT32_32(0xe8d00fdfU | (rt.GetCode() << 12) | (rn.GetCode() << 16));
4735 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4737 (rt.GetCode() << 12) | (rn.GetCode() << 16));
4749 Register rn = operand.GetBaseRegister();
4753 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4754 EmitT32_32(0xe8d00f9fU | (rt.GetCode() << 12) | (rn.GetCode() << 16));
4761 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
4763 (rt.GetCode() << 12) | (rn.GetCode() << 16));
4773 Register rn,
4780 if (!size.IsWide() && rn.IsLow() &&
4781 (((registers.GetList() & (1 << rn.GetCode())) == 0) ==
4784 EmitT32_16(0xc800 | (rn.GetCode() << 8) |
4790 if (!size.IsWide() && rn.Is(sp) && write_back.DoesWriteBack() &&
4799 (!rn.IsPC() || AllowUnpredictable())) {
4800 EmitT32_32(0xe8900000U | (rn.GetCode() << 16) |
4810 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
4811 EmitA32(0x08900000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4817 Delegate(kLdm, &Assembler::ldm, cond, size, rn, write_back, registers);
4821 Register rn,
4828 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
4829 EmitA32(0x08100000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4835 Delegate(kLdmda, &Assembler::ldmda, cond, rn, write_back, registers);
4839 Register rn,
4847 (!rn.IsPC() || AllowUnpredictable())) {
4848 EmitT32_32(0xe9100000U | (rn.GetCode() << 16) |
4858 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
4859 EmitA32(0x09100000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4865 Delegate(kLdmdb, &Assembler::ldmdb, cond, rn, write_back, registers);
4869 Register rn,
4877 (!rn.IsPC() || AllowUnpredictable())) {
4878 EmitT32_32(0xe9100000U | (rn.GetCode() << 16) |
4888 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
4889 EmitA32(0x09100000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4895 Delegate(kLdmea, &Assembler::ldmea, cond, rn, write_back, registers);
4899 Register rn,
4906 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
4907 EmitA32(0x09900000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4913 Delegate(kLdmed, &Assembler::ldmed, cond, rn, write_back, registers);
4917 Register rn,
4924 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
4925 EmitA32(0x08100000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4931 Delegate(kLdmfa, &Assembler::ldmfa, cond, rn, write_back, registers);
4936 Register rn,
4943 if (!size.IsWide() && rn.IsLow() &&
4944 (((registers.GetList() & (1 << rn.GetCode())) == 0) ==
4947 EmitT32_16(0xc800 | (rn.GetCode() << 8) |
4954 (!rn.IsPC() || AllowUnpredictable())) {
4955 EmitT32_32(0xe8900000U | (rn.GetCode() << 16) |
4965 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
4966 EmitA32(0x08900000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4972 Delegate(kLdmfd, &Assembler::ldmfd, cond, size, rn, write_back, registers);
4976 Register rn,
4983 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
4984 EmitA32(0x09900000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
4990 Delegate(kLdmib, &Assembler::ldmib, cond, rn, write_back, registers);
5000 Register rn = operand.GetBaseRegister();
5004 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) &&
5007 EmitT32_16(0x6800 | rt.GetCode() | (rn.GetCode() << 3) |
5014 ((offset % 4) == 0) && rn.Is(sp) && operand.IsOffset()) {
5022 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
5025 EmitT32_32(0xf8d00000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5032 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
5035 EmitT32_32(0xf8500c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5042 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
5047 EmitT32_32(0xf8500900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5054 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
5059 EmitT32_32(0xf8500d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5066 rn.Is(pc) && operand.IsOffset() &&
5078 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf)) {
5082 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
5088 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf)) {
5092 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
5098 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf)) {
5102 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
5107 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) &&
5118 Register rn = operand.GetBaseRegister();
5123 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
5125 EmitT32_16(0x5800 | rt.GetCode() | (rn.GetCode() << 3) |
5133 Register rn = operand.GetBaseRegister();
5141 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
5144 EmitT32_32(0xf8500000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5157 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5168 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5179 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5318 Register rn = operand.GetBaseRegister();
5322 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) &&
5324 EmitT32_16(0x7800 | rt.GetCode() | (rn.GetCode() << 3) |
5331 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
5332 EmitT32_32(0xf8900000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5339 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
5340 EmitT32_32(0xf8100c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5347 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
5350 EmitT32_32(0xf8100900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5357 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
5360 EmitT32_32(0xf8100d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5367 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) {
5377 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
5382 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
5388 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
5393 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
5399 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
5404 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
5409 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) &&
5421 Register rn = operand.GetBaseRegister();
5426 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
5428 EmitT32_16(0x5c00 | rt.GetCode() | (rn.GetCode() << 3) |
5436 Register rn = operand.GetBaseRegister();
5444 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) &&
5446 EmitT32_32(0xf8100000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5459 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5471 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5482 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5586 Register rn = operand.GetBaseRegister();
5591 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
5596 (rn.GetCode() << 16) | offset_ | (sign << 23));
5602 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
5607 (rn.GetCode() << 16) | offset_ | (sign << 23));
5613 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
5618 (rn.GetCode() << 16) | offset_ | (sign << 23));
5623 if ((offset >= -255) && (offset <= 255) && rn.Is(pc) &&
5637 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
5643 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
5650 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
5656 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
5663 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
5669 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
5675 (offset >= -255) && (offset <= 255) && rn.Is(pc) &&
5689 Register rn = operand.GetBaseRegister();
5700 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5711 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5722 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5833 Register rn = operand.GetBaseRegister();
5839 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
5841 EmitT32_32(0xe8500f00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5849 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
5851 (rt.GetCode() << 12) | (rn.GetCode() << 16));
5863 Register rn = operand.GetBaseRegister();
5867 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
5868 EmitT32_32(0xe8d00f4fU | (rt.GetCode() << 12) | (rn.GetCode() << 16));
5875 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
5877 (rt.GetCode() << 12) | (rn.GetCode() << 16));
5892 Register rn = operand.GetBaseRegister();
5896 ((!rt.IsPC() && !rt2.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
5898 (rn.GetCode() << 16));
5906 ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rn.IsPC()) ||
5909 (rt.GetCode() << 12) | (rn.GetCode() << 16));
5921 Register rn = operand.GetBaseRegister();
5925 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
5926 EmitT32_32(0xe8d00f5fU | (rt.GetCode() << 12) | (rn.GetCode() << 16));
5933 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
5935 (rt.GetCode() << 12) | (rn.GetCode() << 16));
5950 Register rn = operand.GetBaseRegister();
5954 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) &&
5957 EmitT32_16(0x8800 | rt.GetCode() | (rn.GetCode() << 3) |
5964 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
5965 EmitT32_32(0xf8b00000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5972 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
5973 EmitT32_32(0xf8300c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5980 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
5983 EmitT32_32(0xf8300900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
5990 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
5993 EmitT32_32(0xf8300d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6000 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) {
6010 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
6015 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
6021 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
6026 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
6032 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
6037 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
6042 if ((offset >= -255) && (offset <= 255) && rn.Is(pc) &&
6055 Register rn = operand.GetBaseRegister();
6060 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
6062 EmitT32_16(0x5a00 | rt.GetCode() | (rn.GetCode() << 3) |
6073 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6082 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6091 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6098 Register rn = operand.GetBaseRegister();
6106 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) &&
6108 EmitT32_32(0xf8300000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6214 Register rn = operand.GetBaseRegister();
6219 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
6220 EmitT32_32(0xf9900000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6227 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
6228 EmitT32_32(0xf9100c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6235 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
6238 EmitT32_32(0xf9100900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6245 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
6248 EmitT32_32(0xf9100d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6255 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) {
6265 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
6270 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
6276 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
6281 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
6287 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
6292 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
6297 if ((offset >= -255) && (offset <= 255) && rn.Is(pc) &&
6310 Register rn = operand.GetBaseRegister();
6315 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
6317 EmitT32_16(0x5600 | rt.GetCode() | (rn.GetCode() << 3) |
6328 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6337 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6346 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6353 Register rn = operand.GetBaseRegister();
6361 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) &&
6363 EmitT32_32(0xf9100000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6469 Register rn = operand.GetBaseRegister();
6474 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
6475 EmitT32_32(0xf9b00000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6482 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
6483 EmitT32_32(0xf9300c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6490 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
6493 EmitT32_32(0xf9300900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6500 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
6503 EmitT32_32(0xf9300d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6510 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) {
6520 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
6525 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
6531 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
6536 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
6542 cond.IsNotNever() && ((rn.GetCode() & 0xf) != 0xf) &&
6547 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
6552 if ((offset >= -255) && (offset <= 255) && rn.Is(pc) &&
6565 Register rn = operand.GetBaseRegister();
6570 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
6572 EmitT32_16(0x5e00 | rt.GetCode() | (rn.GetCode() << 3) |
6583 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6592 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6601 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6608 Register rn = operand.GetBaseRegister();
6616 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) &&
6618 EmitT32_32(0xf9300000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
6986 Condition cond, Register rd, Register rn, Register rm, Register ra) {
6992 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6993 EmitT32_32(0xfb000000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7001 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
7004 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
7008 Delegate(kMla, &Assembler::mla, cond, rd, rn, rm, ra);
7012 Condition cond, Register rd, Register rn, Register rm, Register ra) {
7018 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
7021 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
7025 Delegate(kMlas, &Assembler::mlas, cond, rd, rn, rm, ra);
7029 Condition cond, Register rd, Register rn, Register rm, Register ra) {
7034 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
7036 EmitT32_32(0xfb000010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7044 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
7047 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
7051 Delegate(kMls, &Assembler::mls, cond, rd, rn, rm, ra);
7434 Register rn = operand.GetBaseRegister();
7437 if ((!rn.IsPC() || AllowUnpredictable())) {
7439 ((spec_reg.GetReg() & 0x10) << 16) | (rn.GetCode() << 16));
7445 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
7448 ((spec_reg.GetReg() & 0x10) << 18) | rn.GetCode());
7457 Condition cond, EncodingSize size, Register rd, Register rn, Register rm) {
7462 if (InITBlock() && !size.IsWide() && rd.Is(rm) && rn.IsLow() &&
7464 EmitT32_16(0x4340 | rd.GetCode() | (rn.GetCode() << 3));
7470 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7471 EmitT32_32(0xfb00f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7479 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7481 rn.GetCode() | (rm.GetCode() << 8));
7485 Delegate(kMul, &Assembler::mul, cond, size, rd, rn, rm);
7488 void Assembler::muls(Condition cond, Register rd, Register rn, Register rm) {
7493 if (OutsideITBlock() && rd.Is(rm) && rn.IsLow() && rm.IsLow()) {
7494 EmitT32_16(0x4340 | rd.GetCode() | (rn.GetCode() << 3));
7501 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7503 rn.GetCode() | (rm.GetCode() << 8));
7507 Delegate(kMuls, &Assembler::muls, cond, rd, rn, rm);
7706 Register rn,
7715 if (immediate_t32.IsValid() && !rn.Is(pc) &&
7717 EmitT32_32(0xf0600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7732 if (shift.IsValidAmount(amount) && !rn.Is(pc) &&
7735 EmitT32_32(0xea600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7743 Delegate(kOrn, &Assembler::orn, cond, rd, rn, operand);
7748 Register rn,
7757 if (immediate_t32.IsValid() && !rn.Is(pc) &&
7759 EmitT32_32(0xf0700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7774 if (shift.IsValidAmount(amount) && !rn.Is(pc) &&
7777 EmitT32_32(0xea700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7785 Delegate(kOrns, &Assembler::orns, cond, rd, rn, operand);
7791 Register rn,
7800 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(pc) &&
7802 EmitT32_32(0xf0400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7814 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
7825 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
7837 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(pc) &&
7840 EmitT32_32(0xea400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7851 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7864 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
7867 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7873 Delegate(kOrr, &Assembler::orr, cond, size, rd, rn, operand);
7879 Register rn,
7888 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(pc) &&
7890 EmitT32_32(0xf0500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7902 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
7913 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
7925 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(pc) &&
7928 EmitT32_32(0xea500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7939 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7952 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
7955 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7961 Delegate(kOrrs, &Assembler::orrs, cond, size, rd, rn, operand);
7966 Register rn,
7977 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7978 EmitT32_32(0xeac00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
7987 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7989 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7995 Delegate(kPkhbt, &Assembler::pkhbt, cond, rd, rn, operand);
8000 Register rn,
8011 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8013 EmitT32_32(0xeac00020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8023 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8026 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
8032 Delegate(kPkhtb, &Assembler::pkhtb, cond, rd, rn, operand);
8120 Register rn = operand.GetBaseRegister();
8124 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) &&
8134 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) &&
8146 Register rn = operand.GetBaseRegister();
8151 ((rn.GetCode() & 0xf) != 0xf)) {
8152 EmitT32_32(0xf890f000U | (rn.GetCode() << 16) | (offset & 0xfff));
8158 ((rn.GetCode() & 0xf) != 0xf)) {
8159 EmitT32_32(0xf810fc00U | (rn.GetCode() << 16) | (-offset & 0xff));
8166 ((rn.GetCode() & 0xf) != 0xf)) {
8170 EmitA32(0xf550f000U | (rn.GetCode() << 16) | offset_ | (sign << 23));
8177 Register rn = operand.GetBaseRegister();
8185 ((rn.GetCode() & 0xf) != 0xf) &&
8187 EmitT32_32(0xf810f000U | (rn.GetCode() << 16) | rm.GetCode() |
8199 EmitA32(0xf750f000U | (rn.GetCode() << 16) | rm.GetCode() |
8209 EmitA32(0xf750f060U | (rn.GetCode() << 16) | rm.GetCode() |
8223 Register rn = operand.GetBaseRegister();
8228 ((rn.GetCode() & 0xf) != 0xf)) {
8229 EmitT32_32(0xf8b0f000U | (rn.GetCode() << 16) | (offset & 0xfff));
8235 ((rn.GetCode() & 0xf) != 0xf)) {
8236 EmitT32_32(0xf830fc00U | (rn.GetCode() << 16) | (-offset & 0xff));
8243 ((rn.GetCode() & 0xf) != 0xf)) {
8247 EmitA32(0xf510f000U | (rn.GetCode() << 16) | offset_ | (sign << 23));
8254 Register rn = operand.GetBaseRegister();
8262 ((rn.GetCode() & 0xf) != 0xf) &&
8264 EmitT32_32(0xf830f000U | (rn.GetCode() << 16) | rm.GetCode() |
8276 EmitA32(0xf710f000U | (rn.GetCode() << 16) | rm.GetCode() |
8286 EmitA32(0xf710f060U | (rn.GetCode() << 16) | rm.GetCode() |
8300 Register rn = operand.GetBaseRegister();
8305 ((rn.GetCode() & 0xf) != 0xf)) {
8306 EmitT32_32(0xf990f000U | (rn.GetCode() << 16) | (offset & 0xfff));
8312 ((rn.GetCode() & 0xf) != 0xf)) {
8313 EmitT32_32(0xf910fc00U | (rn.GetCode() << 16) | (-offset & 0xff));
8320 ((rn.GetCode() & 0xf) != 0xf)) {
8324 EmitA32(0xf450f000U | (rn.GetCode() << 16) | offset_ | (sign << 23));
8331 Register rn = operand.GetBaseRegister();
8335 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) &&
8345 if ((offset >= -4095) && (offset <= 4095) && rn.Is(pc) &&
8357 Register rn = operand.GetBaseRegister();
8365 ((rn.GetCode() & 0xf) != 0xf) &&
8367 EmitT32_32(0xf910f000U | (rn.GetCode() << 16) | rm.GetCode() |
8378 EmitA32(0xf650f060U | (rn.GetCode() << 16) | rm.GetCode() |
8389 EmitA32(0xf650f000U | (rn.GetCode() << 16) | rm.GetCode() |
8611 void Assembler::qadd(Condition cond, Register rd, Register rm, Register rn) {
8616 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8618 (rn.GetCode() << 16));
8625 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8627 rm.GetCode() | (rn.GetCode() << 16));
8631 Delegate(kQadd, &Assembler::qadd, cond, rd, rm, rn);
8634 void Assembler::qadd16(Condition cond, Register rd, Register rn, Register rm) {
8639 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8640 EmitT32_32(0xfa90f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8648 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8650 (rn.GetCode() << 16) | rm.GetCode());
8654 Delegate(kQadd16, &Assembler::qadd16, cond, rd, rn, rm);
8657 void Assembler::qadd8(Condition cond, Register rd, Register rn, Register rm) {
8662 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8663 EmitT32_32(0xfa80f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8671 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8673 (rn.GetCode() << 16) | rm.GetCode());
8677 Delegate(kQadd8, &Assembler::qadd8, cond, rd, rn, rm);
8680 void Assembler::qasx(Condition cond, Register rd, Register rn, Register rm) {
8685 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8686 EmitT32_32(0xfaa0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8694 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8696 (rn.GetCode() << 16) | rm.GetCode());
8700 Delegate(kQasx, &Assembler::qasx, cond, rd, rn, rm);
8703 void Assembler::qdadd(Condition cond, Register rd, Register rm, Register rn) {
8708 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8710 (rn.GetCode() << 16));
8717 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8719 rm.GetCode() | (rn.GetCode() << 16));
8723 Delegate(kQdadd, &Assembler::qdadd, cond, rd, rm, rn);
8726 void Assembler::qdsub(Condition cond, Register rd, Register rm, Register rn) {
8731 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8733 (rn.GetCode() << 16));
8740 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8742 rm.GetCode() | (rn.GetCode() << 16));
8746 Delegate(kQdsub, &Assembler::qdsub, cond, rd, rm, rn);
8749 void Assembler::qsax(Condition cond, Register rd, Register rn, Register rm) {
8754 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8755 EmitT32_32(0xfae0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8763 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8765 (rn.GetCode() << 16) | rm.GetCode());
8769 Delegate(kQsax, &Assembler::qsax, cond, rd, rn, rm);
8772 void Assembler::qsub(Condition cond, Register rd, Register rm, Register rn) {
8777 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8779 (rn.GetCode() << 16));
8786 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8788 rm.GetCode() | (rn.GetCode() << 16));
8792 Delegate(kQsub, &Assembler::qsub, cond, rd, rm, rn);
8795 void Assembler::qsub16(Condition cond, Register rd, Register rn, Register rm) {
8800 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8801 EmitT32_32(0xfad0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8809 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8811 (rn.GetCode() << 16) | rm.GetCode());
8815 Delegate(kQsub16, &Assembler::qsub16, cond, rd, rn, rm);
8818 void Assembler::qsub8(Condition cond, Register rd, Register rn, Register rm) {
8823 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8824 EmitT32_32(0xfac0f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
8832 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8834 (rn.GetCode() << 16) | rm.GetCode());
8838 Delegate(kQsub8, &Assembler::qsub8, cond, rd, rn, rm);
9124 Register rn,
9133 if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
9135 EmitT32_16(0x4240 | rd.GetCode() | (rn.GetCode() << 3));
9141 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
9142 EmitT32_32(0xf1c00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9154 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9167 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9169 EmitT32_32(0xebc00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9180 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9193 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9196 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9202 Delegate(kRsb, &Assembler::rsb, cond, size, rd, rn, operand);
9208 Register rn,
9217 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
9219 EmitT32_16(0x4240 | rd.GetCode() | (rn.GetCode() << 3));
9225 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
9226 EmitT32_32(0xf1d00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9238 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9251 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9253 EmitT32_32(0xebd00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9264 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9277 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9280 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9286 Delegate(kRsbs, &Assembler::rsbs, cond, size, rd, rn, operand);
9291 Register rn,
9302 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9317 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9330 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9333 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9339 Delegate(kRsc, &Assembler::rsc, cond, rd, rn, operand);
9344 Register rn,
9355 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9370 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9383 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9386 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9392 Delegate(kRscs, &Assembler::rscs, cond, rd, rn, operand);
9395 void Assembler::sadd16(Condition cond, Register rd, Register rn, Register rm) {
9400 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9401 EmitT32_32(0xfa90f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9409 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9411 (rn.GetCode() << 16) | rm.GetCode());
9415 Delegate(kSadd16, &Assembler::sadd16, cond, rd, rn, rm);
9418 void Assembler::sadd8(Condition cond, Register rd, Register rn, Register rm) {
9423 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9424 EmitT32_32(0xfa80f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9432 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9434 (rn.GetCode() << 16) | rm.GetCode());
9438 Delegate(kSadd8, &Assembler::sadd8, cond, rd, rn, rm);
9441 void Assembler::sasx(Condition cond, Register rd, Register rn, Register rm) {
9446 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9447 EmitT32_32(0xfaa0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9455 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9457 (rn.GetCode() << 16) | rm.GetCode());
9461 Delegate(kSasx, &Assembler::sasx, cond, rd, rn, rm);
9467 Register rn,
9477 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
9478 EmitT32_32(0xf1600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9490 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9501 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
9514 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9516 EmitT32_32(0xeb600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9527 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9540 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9543 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9549 Delegate(kSbc, &Assembler::sbc, cond, size, rd, rn, operand);
9555 Register rn,
9565 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
9566 EmitT32_32(0xf1700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9578 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
9589 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
9602 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9604 EmitT32_32(0xeb700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9615 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9628 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9631 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9637 Delegate(kSbcs, &Assembler::sbcs, cond, size, rd, rn, operand);
9641 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
9647 (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) ||
9650 EmitT32_32(0xf3400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9658 (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) ||
9662 rn.GetCode() | (lsb << 7) | (widthm1 << 16));
9666 Delegate(kSbfx, &Assembler::sbfx, cond, rd, rn, lsb, width);
9669 void Assembler::sdiv(Condition cond, Register rd, Register rn, Register rm) {
9674 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9675 EmitT32_32(0xfb90f0f0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9683 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9685 rn.GetCode() | (rm.GetCode() << 8));
9689 Delegate(kSdiv, &Assembler::sdiv, cond, rd, rn, rm);
9692 void Assembler::sel(Condition cond, Register rd, Register rn, Register rm) {
9697 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9698 EmitT32_32(0xfaa0f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9706 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9708 (rn.GetCode() << 16) | rm.GetCode());
9712 Delegate(kSel, &Assembler::sel, cond, rd, rn, rm);
9715 void Assembler::shadd16(Condition cond, Register rd, Register rn, Register rm) {
9720 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9721 EmitT32_32(0xfa90f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9729 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9731 (rn.GetCode() << 16) | rm.GetCode());
9735 Delegate(kShadd16, &Assembler::shadd16, cond, rd, rn, rm);
9738 void Assembler::shadd8(Condition cond, Register rd, Register rn, Register rm) {
9743 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9744 EmitT32_32(0xfa80f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9752 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9754 (rn.GetCode() << 16) | rm.GetCode());
9758 Delegate(kShadd8, &Assembler::shadd8, cond, rd, rn, rm);
9761 void Assembler::shasx(Condition cond, Register rd, Register rn, Register rm) {
9766 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9767 EmitT32_32(0xfaa0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9775 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9777 (rn.GetCode() << 16) | rm.GetCode());
9781 Delegate(kShasx, &Assembler::shasx, cond, rd, rn, rm);
9784 void Assembler::shsax(Condition cond, Register rd, Register rn, Register rm) {
9789 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9790 EmitT32_32(0xfae0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9798 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9800 (rn.GetCode() << 16) | rm.GetCode());
9804 Delegate(kShsax, &Assembler::shsax, cond, rd, rn, rm);
9807 void Assembler::shsub16(Condition cond, Register rd, Register rn, Register rm) {
9812 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9813 EmitT32_32(0xfad0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9821 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9823 (rn.GetCode() << 16) | rm.GetCode());
9827 Delegate(kShsub16, &Assembler::shsub16, cond, rd, rn, rm);
9830 void Assembler::shsub8(Condition cond, Register rd, Register rn, Register rm) {
9835 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9836 EmitT32_32(0xfac0f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9844 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9846 (rn.GetCode() << 16) | rm.GetCode());
9850 Delegate(kShsub8, &Assembler::shsub8, cond, rd, rn, rm);
9854 Condition cond, Register rd, Register rn, Register rm, Register ra) {
9860 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9861 EmitT32_32(0xfb100000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9869 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
9872 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
9876 Delegate(kSmlabb, &Assembler::smlabb, cond, rd, rn, rm, ra);
9880 Condition cond, Register rd, Register rn, Register rm, Register ra) {
9886 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9887 EmitT32_32(0xfb100010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9895 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
9898 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
9902 Delegate(kSmlabt, &Assembler::smlabt, cond, rd, rn, rm, ra);
9906 Condition cond, Register rd, Register rn, Register rm, Register ra) {
9912 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9913 EmitT32_32(0xfb200000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9921 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9923 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
9927 Delegate(kSmlad, &Assembler::smlad, cond, rd, rn, rm, ra);
9931 Condition cond, Register rd, Register rn, Register rm, Register ra) {
9937 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9938 EmitT32_32(0xfb200010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
9946 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9948 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
9952 Delegate(kSmladx, &Assembler::smladx, cond, rd, rn, rm, ra);
9956 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
9961 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
9964 (rn.GetCode() << 16) | rm.GetCode());
9971 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
9974 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
9979 Delegate(kSmlal, &Assembler::smlal, cond, rdlo, rdhi, rn, rm);
9983 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
9988 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
9991 (rn.GetCode() << 16) | rm.GetCode());
9998 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10001 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
10006 Delegate(kSmlalbb, &Assembler::smlalbb, cond, rdlo, rdhi, rn, rm);
10010 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10015 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10018 (rn.GetCode() << 16) | rm.GetCode());
10025 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10028 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
10033 Delegate(kSmlalbt, &Assembler::smlalbt, cond, rdlo, rdhi, rn, rm);
10037 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10042 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10045 (rn.GetCode() << 16) | rm.GetCode());
10052 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10055 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
10060 Delegate(kSmlald, &Assembler::smlald, cond, rdlo, rdhi, rn, rm);
10064 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10069 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10072 (rn.GetCode() << 16) | rm.GetCode());
10079 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10082 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
10087 Delegate(kSmlaldx, &Assembler::smlaldx, cond, rdlo, rdhi, rn, rm);
10091 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10097 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10100 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
10105 Delegate(kSmlals, &Assembler::smlals, cond, rdlo, rdhi, rn, rm);
10109 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10114 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10117 (rn.GetCode() << 16) | rm.GetCode());
10124 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10127 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
10132 Delegate(kSmlaltb, &Assembler::smlaltb, cond, rdlo, rdhi, rn, rm);
10136 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10141 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10144 (rn.GetCode() << 16) | rm.GetCode());
10151 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10154 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
10159 Delegate(kSmlaltt, &Assembler::smlaltt, cond, rdlo, rdhi, rn, rm);
10163 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10169 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10170 EmitT32_32(0xfb100020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10178 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10181 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10185 Delegate(kSmlatb, &Assembler::smlatb, cond, rd, rn, rm, ra);
10189 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10195 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10196 EmitT32_32(0xfb100030U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10204 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10207 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10211 Delegate(kSmlatt, &Assembler::smlatt, cond, rd, rn, rm, ra);
10215 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10221 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10222 EmitT32_32(0xfb300000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10230 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10233 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10237 Delegate(kSmlawb, &Assembler::smlawb, cond, rd, rn, rm, ra);
10241 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10247 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10248 EmitT32_32(0xfb300010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10256 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10259 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10263 Delegate(kSmlawt, &Assembler::smlawt, cond, rd, rn, rm, ra);
10267 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10273 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10274 EmitT32_32(0xfb400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10282 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10284 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10288 Delegate(kSmlsd, &Assembler::smlsd, cond, rd, rn, rm, ra);
10292 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10298 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10299 EmitT32_32(0xfb400010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10307 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10309 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10313 Delegate(kSmlsdx, &Assembler::smlsdx, cond, rd, rn, rm, ra);
10317 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10322 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10325 (rn.GetCode() << 16) | rm.GetCode());
10332 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10335 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
10340 Delegate(kSmlsld, &Assembler::smlsld, cond, rdlo, rdhi, rn, rm);
10344 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10349 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10352 (rn.GetCode() << 16) | rm.GetCode());
10359 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10362 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
10367 Delegate(kSmlsldx, &Assembler::smlsldx, cond, rdlo, rdhi, rn, rm);
10371 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10377 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10378 EmitT32_32(0xfb500000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10386 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10388 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10392 Delegate(kSmmla, &Assembler::smmla, cond, rd, rn, rm, ra);
10396 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10402 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10403 EmitT32_32(0xfb500010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10411 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10413 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10417 Delegate(kSmmlar, &Assembler::smmlar, cond, rd, rn, rm, ra);
10421 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10426 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10428 EmitT32_32(0xfb600000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10436 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10439 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10443 Delegate(kSmmls, &Assembler::smmls, cond, rd, rn, rm, ra);
10447 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10452 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10454 EmitT32_32(0xfb600010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10462 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10465 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10469 Delegate(kSmmlsr, &Assembler::smmlsr, cond, rd, rn, rm, ra);
10472 void Assembler::smmul(Condition cond, Register rd, Register rn, Register rm) {
10477 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10478 EmitT32_32(0xfb50f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10486 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10488 rn.GetCode() | (rm.GetCode() << 8));
10492 Delegate(kSmmul, &Assembler::smmul, cond, rd, rn, rm);
10495 void Assembler::smmulr(Condition cond, Register rd, Register rn, Register rm) {
10500 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10501 EmitT32_32(0xfb50f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10509 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10511 rn.GetCode() | (rm.GetCode() << 8));
10515 Delegate(kSmmulr, &Assembler::smmulr, cond, rd, rn, rm);
10518 void Assembler::smuad(Condition cond, Register rd, Register rn, Register rm) {
10523 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10524 EmitT32_32(0xfb20f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10532 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10534 rn.GetCode() | (rm.GetCode() << 8));
10538 Delegate(kSmuad, &Assembler::smuad, cond, rd, rn, rm);
10541 void Assembler::smuadx(Condition cond, Register rd, Register rn, Register rm) {
10546 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10547 EmitT32_32(0xfb20f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10555 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10557 rn.GetCode() | (rm.GetCode() << 8));
10561 Delegate(kSmuadx, &Assembler::smuadx, cond, rd, rn, rm);
10564 void Assembler::smulbb(Condition cond, Register rd, Register rn, Register rm) {
10569 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10570 EmitT32_32(0xfb10f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10578 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10580 rn.GetCode() | (rm.GetCode() << 8));
10584 Delegate(kSmulbb, &Assembler::smulbb, cond, rd, rn, rm);
10587 void Assembler::smulbt(Condition cond, Register rd, Register rn, Register rm) {
10592 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10593 EmitT32_32(0xfb10f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10601 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10603 rn.GetCode() | (rm.GetCode() << 8));
10607 Delegate(kSmulbt, &Assembler::smulbt, cond, rd, rn, rm);
10611 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10616 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10619 (rn.GetCode() << 16) | rm.GetCode());
10626 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10629 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
10634 Delegate(kSmull, &Assembler::smull, cond, rdlo, rdhi, rn, rm);
10638 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10644 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10647 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
10652 Delegate(kSmulls, &Assembler::smulls, cond, rdlo, rdhi, rn, rm);
10655 void Assembler::smultb(Condition cond, Register rd, Register rn, Register rm) {
10660 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10661 EmitT32_32(0xfb10f020U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10669 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10671 rn.GetCode() | (rm.GetCode() << 8));
10675 Delegate(kSmultb, &Assembler::smultb, cond, rd, rn, rm);
10678 void Assembler::smultt(Condition cond, Register rd, Register rn, Register rm) {
10683 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10684 EmitT32_32(0xfb10f030U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10692 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10694 rn.GetCode() | (rm.GetCode() << 8));
10698 Delegate(kSmultt, &Assembler::smultt, cond, rd, rn, rm);
10701 void Assembler::smulwb(Condition cond, Register rd, Register rn, Register rm) {
10706 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10707 EmitT32_32(0xfb30f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10715 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10717 rn.GetCode() | (rm.GetCode() << 8));
10721 Delegate(kSmulwb, &Assembler::smulwb, cond, rd, rn, rm);
10724 void Assembler::smulwt(Condition cond, Register rd, Register rn, Register rm) {
10729 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10730 EmitT32_32(0xfb30f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10738 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10740 rn.GetCode() | (rm.GetCode() << 8));
10744 Delegate(kSmulwt, &Assembler::smulwt, cond, rd, rn, rm);
10747 void Assembler::smusd(Condition cond, Register rd, Register rn, Register rm) {
10752 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10753 EmitT32_32(0xfb40f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10761 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10763 rn.GetCode() | (rm.GetCode() << 8));
10767 Delegate(kSmusd, &Assembler::smusd, cond, rd, rn, rm);
10770 void Assembler::smusdx(Condition cond, Register rd, Register rn, Register rm) {
10775 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10776 EmitT32_32(0xfb40f010U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10784 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10786 rn.GetCode() | (rm.GetCode() << 8));
10790 Delegate(kSmusdx, &Assembler::smusdx, cond, rd, rn, rm);
10800 Register rn = operand.GetBaseRegister();
10807 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10810 (rn.GetCode() << 16) | ((amount & 0x3) << 6) |
10817 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10820 (rn.GetCode() << 16) | ((amount & 0x3) << 6) |
10829 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10833 (rd.GetCode() << 12) | (imm_ << 16) | rn.GetCode() |
10840 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10843 (rd.GetCode() << 12) | (imm_ << 16) | rn.GetCode() |
10852 void Assembler::ssat16(Condition cond, Register rd, uint32_t imm, Register rn) {
10858 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10861 (rn.GetCode() << 16));
10868 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10871 (imm_ << 16) | rn.GetCode());
10875 Delegate(kSsat16, &Assembler::ssat16, cond, rd, imm, rn);
10878 void Assembler::ssax(Condition cond, Register rd, Register rn, Register rm) {
10883 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10884 EmitT32_32(0xfae0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10892 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10894 (rn.GetCode() << 16) | rm.GetCode());
10898 Delegate(kSsax, &Assembler::ssax, cond, rd, rn, rm);
10901 void Assembler::ssub16(Condition cond, Register rd, Register rn, Register rm) {
10906 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10907 EmitT32_32(0xfad0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10915 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10917 (rn.GetCode() << 16) | rm.GetCode());
10921 Delegate(kSsub16, &Assembler::ssub16, cond, rd, rn, rm);
10924 void Assembler::ssub8(Condition cond, Register rd, Register rn, Register rm) {
10929 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10930 EmitT32_32(0xfac0f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
10938 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10940 (rn.GetCode() << 16) | rm.GetCode());
10944 Delegate(kSsub8, &Assembler::ssub8, cond, rd, rn, rm);
10951 Register rn = operand.GetBaseRegister();
10955 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10956 EmitT32_32(0xe8c00fafU | (rt.GetCode() << 12) | (rn.GetCode() << 16));
10963 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10965 (rn.GetCode() << 16));
10977 Register rn = operand.GetBaseRegister();
10981 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10982 EmitT32_32(0xe8c00f8fU | (rt.GetCode() << 12) | (rn.GetCode() << 16));
10989 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
10991 (rn.GetCode() << 16));
11006 Register rn = operand.GetBaseRegister();
11010 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11012 (rn.GetCode() << 16));
11019 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11021 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11036 Register rn = operand.GetBaseRegister();
11040 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11042 (rn.GetCode() << 16));
11049 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11051 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11067 Register rn = operand.GetBaseRegister();
11071 ((!rd.IsPC() && !rt.IsPC() && !rt2.IsPC() && !rn.IsPC()) ||
11074 (rt2.GetCode() << 8) | (rn.GetCode() << 16));
11083 !rn.IsPC()) ||
11086 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11101 Register rn = operand.GetBaseRegister();
11105 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11107 (rn.GetCode() << 16));
11114 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11116 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11128 Register rn = operand.GetBaseRegister();
11132 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11133 EmitT32_32(0xe8c00f9fU | (rt.GetCode() << 12) | (rn.GetCode() << 16));
11140 ((!rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11142 (rn.GetCode() << 16));
11152 Register rn,
11159 if (!size.IsWide() && rn.IsLow() && write_back.DoesWriteBack() &&
11161 EmitT32_16(0xc000 | (rn.GetCode() << 8) |
11168 (!rn.IsPC() || AllowUnpredictable())) {
11169 EmitT32_32(0xe8800000U | (rn.GetCode() << 16) |
11178 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
11179 EmitA32(0x08800000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
11185 Delegate(kStm, &Assembler::stm, cond, size, rn, write_back, registers);
11189 Register rn,
11196 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
11197 EmitA32(0x08000000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
11203 Delegate(kStmda, &Assembler::stmda, cond, rn, write_back, registers);
11208 Register rn,
11215 if (!size.IsWide() && rn.Is(sp) && write_back.DoesWriteBack() &&
11224 (!rn.IsPC() || AllowUnpredictable())) {
11225 EmitT32_32(0xe9000000U | (rn.GetCode() << 16) |
11234 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
11235 EmitA32(0x09000000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
11241 Delegate(kStmdb, &Assembler::stmdb, cond, size, rn, write_back, registers);
11246 Register rn,
11253 if (!size.IsWide() && rn.IsLow() && write_back.DoesWriteBack() &&
11255 EmitT32_16(0xc000 | (rn.GetCode() << 8) |
11262 (!rn.IsPC() || AllowUnpredictable())) {
11263 EmitT32_32(0xe8800000U | (rn.GetCode() << 16) |
11272 (!rn.IsPC() || AllowUnpredictable())) {
11273 EmitT32_32(0xe8800000U | (rn.GetCode() << 16) |
11282 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
11283 EmitA32(0x08800000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
11289 Delegate(kStmea, &Assembler::stmea, cond, size, rn, write_back, registers);
11293 Register rn,
11300 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
11301 EmitA32(0x08000000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
11307 Delegate(kStmed, &Assembler::stmed, cond, rn, write_back, registers);
11311 Register rn,
11318 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
11319 EmitA32(0x09800000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
11325 Delegate(kStmfa, &Assembler::stmfa, cond, rn, write_back, registers);
11329 Register rn,
11337 (!rn.IsPC() || AllowUnpredictable())) {
11338 EmitT32_32(0xe9000000U | (rn.GetCode() << 16) |
11347 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
11348 EmitA32(0x09000000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
11354 Delegate(kStmfd, &Assembler::stmfd, cond, rn, write_back, registers);
11358 Register rn,
11365 if (cond.IsNotNever() && (!rn.IsPC() || AllowUnpredictable())) {
11366 EmitA32(0x09800000U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
11372 Delegate(kStmib, &Assembler::stmib, cond, rn, write_back, registers);
11382 Register rn = operand.GetBaseRegister();
11386 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) &&
11389 EmitT32_16(0x6000 | rt.GetCode() | (rn.GetCode() << 3) |
11396 ((offset % 4) == 0) && rn.Is(sp) && operand.IsOffset()) {
11404 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11406 EmitT32_32(0xf8c00000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11413 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11415 EmitT32_32(0xf8400c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11422 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11426 EmitT32_32(0xf8400900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11433 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11437 EmitT32_32(0xf8400d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11449 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
11459 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
11469 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
11476 Register rn = operand.GetBaseRegister();
11481 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
11483 EmitT32_16(0x5000 | rt.GetCode() | (rn.GetCode() << 3) |
11491 Register rn = operand.GetBaseRegister();
11499 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11501 EmitT32_32(0xf8400000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11514 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11525 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11536 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11552 Register rn = operand.GetBaseRegister();
11556 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) &&
11558 EmitT32_16(0x7000 | rt.GetCode() | (rn.GetCode() << 3) |
11565 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11567 EmitT32_32(0xf8800000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11574 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11576 EmitT32_32(0xf8000c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11583 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11587 EmitT32_32(0xf8000900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11594 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11598 EmitT32_32(0xf8000d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11610 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
11620 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
11630 (rt.GetCode() << 12) | (rn.GetCode() << 16) | offset_ |
11637 Register rn = operand.GetBaseRegister();
11642 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
11644 EmitT32_16(0x5400 | rt.GetCode() | (rn.GetCode() << 3) |
11652 Register rn = operand.GetBaseRegister();
11660 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11662 EmitT32_32(0xf8000000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11675 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11687 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11698 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11714 Register rn = operand.GetBaseRegister();
11719 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11720 ((!rn.IsPC() && !rt.IsPC() && !rt2.IsPC()) || AllowUnpredictable())) {
11724 (rn.GetCode() << 16) | offset_ | (sign << 23));
11730 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11731 ((!rn.IsPC() && !rt.IsPC() && !rt2.IsPC()) || AllowUnpredictable())) {
11735 (rn.GetCode() << 16) | offset_ | (sign << 23));
11741 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11742 ((!rn.IsPC() && !rt.IsPC() && !rt2.IsPC()) || AllowUnpredictable())) {
11746 (rn.GetCode() << 16) | offset_ | (sign << 23));
11759 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
11771 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
11783 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
11790 Register rn = operand.GetBaseRegister();
11801 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11812 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11823 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11839 Register rn = operand.GetBaseRegister();
11845 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11848 (rn.GetCode() << 16) | (offset_ & 0xff));
11855 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11857 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11872 Register rn = operand.GetBaseRegister();
11876 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11878 (rn.GetCode() << 16));
11885 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11887 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11903 Register rn = operand.GetBaseRegister();
11907 ((!rd.IsPC() && !rt.IsPC() && !rt2.IsPC() && !rn.IsPC()) ||
11910 (rt2.GetCode() << 8) | (rn.GetCode() << 16));
11919 !rn.IsPC()) ||
11922 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11937 Register rn = operand.GetBaseRegister();
11941 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11943 (rn.GetCode() << 16));
11950 ((!rd.IsPC() && !rt.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
11952 (rd.GetCode() << 12) | rt.GetCode() | (rn.GetCode() << 16));
11967 Register rn = operand.GetBaseRegister();
11971 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && (offset >= 0) &&
11974 EmitT32_16(0x8000 | rt.GetCode() | (rn.GetCode() << 3) |
11981 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11983 EmitT32_32(0xf8a00000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11990 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11992 EmitT32_32(0xf8200c00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
11999 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
12003 EmitT32_32(0xf8200900U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
12010 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
12014 EmitT32_32(0xf8200d00U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
12026 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
12036 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
12046 (rt.GetCode() << 12) | (rn.GetCode() << 16) | (offset_ & 0xf) |
12053 Register rn = operand.GetBaseRegister();
12058 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
12060 EmitT32_16(0x5200 | rt.GetCode() | (rn.GetCode() << 3) |
12071 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12080 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12089 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12096 Register rn = operand.GetBaseRegister();
12104 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
12106 EmitT32_32(0xf8200000U | (rt.GetCode() << 12) | (rn.GetCode() << 16) |
12119 Register rn,
12128 if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
12130 EmitT32_16(0x1e00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6));
12135 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
12142 if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && (imm <= 508) &&
12150 if (!size.IsNarrow() && rn.Is(pc) && (imm <= 4095) &&
12158 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(sp) &&
12159 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
12160 EmitT32_32(0xf1a00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12168 if (!size.IsNarrow() && (imm <= 4095) && ((rn.GetCode() & 0xd) != 0xd) &&
12170 EmitT32_32(0xf2a00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12176 if (!size.IsNarrow() && rn.Is(sp) && immediate_t32.IsValid() &&
12186 if (!size.IsNarrow() && rn.Is(sp) && (imm <= 4095) &&
12196 if (rn.Is(pc) && immediate_a32.IsValid() && cond.IsNotNever()) {
12203 ((rn.GetCode() & 0xd) != 0xd)) {
12205 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
12210 if (rn.Is(sp) && immediate_a32.IsValid() && cond.IsNotNever()) {
12222 if (InITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
12224 EmitT32_16(0x1a00 | rd.GetCode() | (rn.GetCode() << 3) |
12230 if (rn.Is(sp) && ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12241 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(sp) &&
12242 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12244 EmitT32_32(0xeba00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12251 if (!size.IsNarrow() && rn.Is(sp) && shift.IsValidAmount(amount) &&
12262 if (shift.IsValidAmount(amount) && cond.IsNotNever() && !rn.Is(sp)) {
12265 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12270 if (rn.Is(sp) && shift.IsValidAmount(amount) && cond.IsNotNever()) {
12286 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
12289 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12295 Delegate(kSub, &Assembler::sub, cond, size, rd, rn, operand);
12318 Register rn,
12327 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
12329 EmitT32_16(0x1e00 | rd.GetCode() | (rn.GetCode() << 3) | (imm << 6));
12334 if (OutsideITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() &&
12341 if (!size.IsNarrow() && immediate_t32.IsValid() && !rn.Is(sp) &&
12342 !rd.Is(pc) && (!rn.IsPC() || AllowUnpredictable())) {
12343 EmitT32_32(0xf1b00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12351 if (!size.IsNarrow() && rd.Is(pc) && rn.Is(lr) && (imm <= 255) &&
12358 if (!size.IsNarrow() && rn.Is(sp) && immediate_t32.IsValid() &&
12370 if (immediate_a32.IsValid() && cond.IsNotNever() && !rn.Is(sp)) {
12372 (rd.GetCode() << 12) | (rn.GetCode() << 16) |
12377 if (rn.Is(sp) && immediate_a32.IsValid() && cond.IsNotNever()) {
12389 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rn.IsLow() &&
12391 EmitT32_16(0x1a00 | rd.GetCode() | (rn.GetCode() << 3) |
12402 if (!size.IsNarrow() && shift.IsValidAmount(amount) && !rn.Is(sp) &&
12403 !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12405 EmitT32_32(0xebb00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12412 if (!size.IsNarrow() && rn.Is(sp) && shift.IsValidAmount(amount) &&
12423 if (shift.IsValidAmount(amount) && cond.IsNotNever() && !rn.Is(sp)) {
12426 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12431 if (rn.Is(sp) && shift.IsValidAmount(amount) && cond.IsNotNever()) {
12447 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
12450 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12456 Delegate(kSubs, &Assembler::subs, cond, size, rd, rn, operand);
12478 Register rn,
12486 if ((imm <= 4095) && ((rn.GetCode() & 0xd) != 0xd) &&
12488 EmitT32_32(0xf2a00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12494 if (rn.Is(sp) && (imm <= 4095) && (!rd.IsPC() || AllowUnpredictable())) {
12502 Delegate(kSubw, &Assembler::subw, cond, rd, rn, operand);
12527 Register rn,
12538 ((amount % 8) == 0) && !rn.Is(pc) &&
12541 EmitT32_32(0xfa40f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12549 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) &&
12553 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12559 Delegate(kSxtab, &Assembler::sxtab, cond, rd, rn, operand);
12564 Register rn,
12575 ((amount % 8) == 0) && !rn.Is(pc) &&
12578 EmitT32_32(0xfa20f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12586 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) &&
12590 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12596 Delegate(kSxtab16, &Assembler::sxtab16, cond, rd, rn, operand);
12601 Register rn,
12612 ((amount % 8) == 0) && !rn.Is(pc) &&
12615 EmitT32_32(0xfa00f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12623 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) &&
12627 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12633 Delegate(kSxtah, &Assembler::sxtah, cond, rd, rn, operand);
12761 void Assembler::tbb(Condition cond, Register rn, Register rm) {
12768 EmitT32_32(0xe8d0f000U | (rn.GetCode() << 16) | rm.GetCode());
12773 Delegate(kTbb, &Assembler::tbb, cond, rn, rm);
12776 void Assembler::tbh(Condition cond, Register rn, Register rm) {
12783 EmitT32_32(0xe8d0f010U | (rn.GetCode() << 16) | rm.GetCode());
12788 Delegate(kTbh, &Assembler::tbh, cond, rn, rm);
12791 void Assembler::teq(Condition cond, Register rn, const Operand& operand) {
12799 if (immediate_t32.IsValid() && (!rn.IsPC() || AllowUnpredictable())) {
12800 EmitT32_32(0xf0900f00U | (rn.GetCode() << 16) |
12812 (rn.GetCode() << 16) | immediate_a32.GetEncodingValue());
12824 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12826 EmitT32_32(0xea900f00U | (rn.GetCode() << 16) | rm.GetCode() |
12837 (rn.GetCode() << 16) | rm.GetCode() |
12850 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
12852 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |
12858 Delegate(kTeq, &Assembler::teq, cond, rn, operand);
12863 Register rn,
12873 (!rn.IsPC() || AllowUnpredictable())) {
12874 EmitT32_32(0xf0100f00U | (rn.GetCode() << 16) |
12886 (rn.GetCode() << 16) | immediate_a32.GetEncodingValue());
12896 if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {
12897 EmitT32_16(0x4200 | rn.GetCode() | (rm.GetCode() << 3));
12908 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12910 EmitT32_32(0xea100f00U | (rn.GetCode() << 16) | rm.GetCode() |
12921 (rn.GetCode() << 16) | rm.GetCode() |
12934 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
12936 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |
12942 Delegate(kTst, &Assembler::tst, cond, size, rn, operand);
12945 void Assembler::uadd16(Condition cond, Register rd, Register rn, Register rm) {
12950 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12951 EmitT32_32(0xfa90f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12959 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12961 (rn.GetCode() << 16) | rm.GetCode());
12965 Delegate(kUadd16, &Assembler::uadd16, cond, rd, rn, rm);
12968 void Assembler::uadd8(Condition cond, Register rd, Register rn, Register rm) {
12973 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12974 EmitT32_32(0xfa80f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
12982 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12984 (rn.GetCode() << 16) | rm.GetCode());
12988 Delegate(kUadd8, &Assembler::uadd8, cond, rd, rn, rm);
12991 void Assembler::uasx(Condition cond, Register rd, Register rn, Register rm) {
12996 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12997 EmitT32_32(0xfaa0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13005 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13007 (rn.GetCode() << 16) | rm.GetCode());
13011 Delegate(kUasx, &Assembler::uasx, cond, rd, rn, rm);
13015 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) {
13021 (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) ||
13024 EmitT32_32(0xf3c00000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13032 (((width >= 1) && (width <= 32 - lsb) && !rd.IsPC() && !rn.IsPC()) ||
13036 rn.GetCode() | (lsb << 7) | (widthm1 << 16));
13040 Delegate(kUbfx, &Assembler::ubfx, cond, rd, rn, lsb, width);
13075 void Assembler::udiv(Condition cond, Register rd, Register rn, Register rm) {
13080 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13081 EmitT32_32(0xfbb0f0f0U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13089 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13091 rn.GetCode() | (rm.GetCode() << 8));
13095 Delegate(kUdiv, &Assembler::udiv, cond, rd, rn, rm);
13098 void Assembler::uhadd16(Condition cond, Register rd, Register rn, Register rm) {
13103 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13104 EmitT32_32(0xfa90f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13112 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13114 (rn.GetCode() << 16) | rm.GetCode());
13118 Delegate(kUhadd16, &Assembler::uhadd16, cond, rd, rn, rm);
13121 void Assembler::uhadd8(Condition cond, Register rd, Register rn, Register rm) {
13126 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13127 EmitT32_32(0xfa80f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13135 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13137 (rn.GetCode() << 16) | rm.GetCode());
13141 Delegate(kUhadd8, &Assembler::uhadd8, cond, rd, rn, rm);
13144 void Assembler::uhasx(Condition cond, Register rd, Register rn, Register rm) {
13149 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13150 EmitT32_32(0xfaa0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13158 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13160 (rn.GetCode() << 16) | rm.GetCode());
13164 Delegate(kUhasx, &Assembler::uhasx, cond, rd, rn, rm);
13167 void Assembler::uhsax(Condition cond, Register rd, Register rn, Register rm) {
13172 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13173 EmitT32_32(0xfae0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13181 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13183 (rn.GetCode() << 16) | rm.GetCode());
13187 Delegate(kUhsax, &Assembler::uhsax, cond, rd, rn, rm);
13190 void Assembler::uhsub16(Condition cond, Register rd, Register rn, Register rm) {
13195 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13196 EmitT32_32(0xfad0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13204 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13206 (rn.GetCode() << 16) | rm.GetCode());
13210 Delegate(kUhsub16, &Assembler::uhsub16, cond, rd, rn, rm);
13213 void Assembler::uhsub8(Condition cond, Register rd, Register rn, Register rm) {
13218 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13219 EmitT32_32(0xfac0f060U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13227 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13229 (rn.GetCode() << 16) | rm.GetCode());
13233 Delegate(kUhsub8, &Assembler::uhsub8, cond, rd, rn, rm);
13237 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
13242 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13245 (rn.GetCode() << 16) | rm.GetCode());
13252 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13255 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
13260 Delegate(kUmaal, &Assembler::umaal, cond, rdlo, rdhi, rn, rm);
13264 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
13269 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13272 (rn.GetCode() << 16) | rm.GetCode());
13279 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13282 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
13287 Delegate(kUmlal, &Assembler::umlal, cond, rdlo, rdhi, rn, rm);
13291 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
13297 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13300 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
13305 Delegate(kUmlals, &Assembler::umlals, cond, rdlo, rdhi, rn, rm);
13309 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
13314 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13317 (rn.GetCode() << 16) | rm.GetCode());
13324 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13327 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
13332 Delegate(kUmull, &Assembler::umull, cond, rdlo, rdhi, rn, rm);
13336 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
13342 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13345 (rdlo.GetCode() << 12) | (rdhi.GetCode() << 16) | rn.GetCode() |
13350 Delegate(kUmulls, &Assembler::umulls, cond, rdlo, rdhi, rn, rm);
13353 void Assembler::uqadd16(Condition cond, Register rd, Register rn, Register rm) {
13358 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13359 EmitT32_32(0xfa90f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13367 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13369 (rn.GetCode() << 16) | rm.GetCode());
13373 Delegate(kUqadd16, &Assembler::uqadd16, cond, rd, rn, rm);
13376 void Assembler::uqadd8(Condition cond, Register rd, Register rn, Register rm) {
13381 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13382 EmitT32_32(0xfa80f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13390 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13392 (rn.GetCode() << 16) | rm.GetCode());
13396 Delegate(kUqadd8, &Assembler::uqadd8, cond, rd, rn, rm);
13399 void Assembler::uqasx(Condition cond, Register rd, Register rn, Register rm) {
13404 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13405 EmitT32_32(0xfaa0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13413 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13415 (rn.GetCode() << 16) | rm.GetCode());
13419 Delegate(kUqasx, &Assembler::uqasx, cond, rd, rn, rm);
13422 void Assembler::uqsax(Condition cond, Register rd, Register rn, Register rm) {
13427 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13428 EmitT32_32(0xfae0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13436 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13438 (rn.GetCode() << 16) | rm.GetCode());
13442 Delegate(kUqsax, &Assembler::uqsax, cond, rd, rn, rm);
13445 void Assembler::uqsub16(Condition cond, Register rd, Register rn, Register rm) {
13450 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13451 EmitT32_32(0xfad0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13459 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13461 (rn.GetCode() << 16) | rm.GetCode());
13465 Delegate(kUqsub16, &Assembler::uqsub16, cond, rd, rn, rm);
13468 void Assembler::uqsub8(Condition cond, Register rd, Register rn, Register rm) {
13473 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13474 EmitT32_32(0xfac0f050U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13482 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13484 (rn.GetCode() << 16) | rm.GetCode());
13488 Delegate(kUqsub8, &Assembler::uqsub8, cond, rd, rn, rm);
13491 void Assembler::usad8(Condition cond, Register rd, Register rn, Register rm) {
13496 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13497 EmitT32_32(0xfb70f000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13505 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13507 rn.GetCode() | (rm.GetCode() << 8));
13511 Delegate(kUsad8, &Assembler::usad8, cond, rd, rn, rm);
13515 Condition cond, Register rd, Register rn, Register rm, Register ra) {
13521 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13522 EmitT32_32(0xfb700000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13530 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13532 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
13536 Delegate(kUsada8, &Assembler::usada8, cond, rd, rn, rm, ra);
13546 Register rn = operand.GetBaseRegister();
13552 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13554 (rn.GetCode() << 16) | ((amount & 0x3) << 6) |
13561 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13563 (rn.GetCode() << 16) | ((amount & 0x3) << 6) |
13572 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13575 (rd.GetCode() << 12) | (imm << 16) | rn.GetCode() |
13581 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13583 (rd.GetCode() << 12) | (imm << 16) | rn.GetCode() |
13592 void Assembler::usat16(Condition cond, Register rd, uint32_t imm, Register rn) {
13597 if ((imm <= 15) && ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13599 (rn.GetCode() << 16));
13606 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) {
13608 (imm << 16) | rn.GetCode());
13612 Delegate(kUsat16, &Assembler::usat16, cond, rd, imm, rn);
13615 void Assembler::usax(Condition cond, Register rd, Register rn, Register rm) {
13620 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13621 EmitT32_32(0xfae0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13629 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13631 (rn.GetCode() << 16) | rm.GetCode());
13635 Delegate(kUsax, &Assembler::usax, cond, rd, rn, rm);
13638 void Assembler::usub16(Condition cond, Register rd, Register rn, Register rm) {
13643 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13644 EmitT32_32(0xfad0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13652 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13654 (rn.GetCode() << 16) | rm.GetCode());
13658 Delegate(kUsub16, &Assembler::usub16, cond, rd, rn, rm);
13661 void Assembler::usub8(Condition cond, Register rd, Register rn, Register rm) {
13666 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13667 EmitT32_32(0xfac0f040U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13675 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13677 (rn.GetCode() << 16) | rm.GetCode());
13681 Delegate(kUsub8, &Assembler::usub8, cond, rd, rn, rm);
13686 Register rn,
13697 ((amount % 8) == 0) && !rn.Is(pc) &&
13700 EmitT32_32(0xfa50f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13708 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) &&
13712 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
13718 Delegate(kUxtab, &Assembler::uxtab, cond, rd, rn, operand);
13723 Register rn,
13734 ((amount % 8) == 0) && !rn.Is(pc) &&
13737 EmitT32_32(0xfa30f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13745 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) &&
13749 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
13755 Delegate(kUxtab16, &Assembler::uxtab16, cond, rd, rn, operand);
13760 Register rn,
13771 ((amount % 8) == 0) && !rn.Is(pc) &&
13774 EmitT32_32(0xfa10f080U | (rd.GetCode() << 8) | (rn.GetCode() << 16) |
13782 ((amount % 8) == 0) && cond.IsNotNever() && !rn.Is(pc) &&
13786 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
13792 Delegate(kUxtah, &Assembler::uxtah, cond, rd, rn, operand);
13921 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
13931 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13942 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13947 Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm);
13951 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
13961 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13972 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13977 Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm);
13981 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
13991 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14002 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14007 Delegate(kVabal, &Assembler::vabal, cond, dt, rd, rn, rm);
14011 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14019 EmitT32_32(0xff200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14030 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14039 EmitA32(0xf3200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14049 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14054 Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm);
14058 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14066 EmitT32_32(0xff200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14077 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14086 EmitA32(0xf3200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14096 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14101 Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm);
14105 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
14115 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14126 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14131 Delegate(kVabdl, &Assembler::vabdl, cond, dt, rd, rn, rm);
14226 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14233 EmitT32_32(0xff000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14243 EmitA32(0xf3000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14249 Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm);
14253 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14260 EmitT32_32(0xff000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14270 EmitA32(0xf3000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14276 Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm);
14280 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14287 EmitT32_32(0xff200e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14297 EmitA32(0xf3200e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14303 Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm);
14307 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14314 EmitT32_32(0xff200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14324 EmitA32(0xf3200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14330 Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm);
14334 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14341 EmitT32_32(0xff000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14351 EmitA32(0xf3000e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14357 Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm);
14361 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14368 EmitT32_32(0xff000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14378 EmitA32(0xf3000e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14384 Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm);
14388 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14395 EmitT32_32(0xff200e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14405 EmitA32(0xf3200e10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14411 Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm);
14415 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14422 EmitT32_32(0xff200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14432 EmitA32(0xf3200e50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14438 Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm);
14442 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14450 EmitT32_32(0xef000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14458 EmitT32_32(0xee300b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14467 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14476 EmitA32(0xf2000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14484 rn.Encode(7, 16) | rm.Encode(5, 0));
14491 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14496 Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);
14500 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14508 EmitT32_32(0xef000d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14518 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14527 EmitA32(0xf2000d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14536 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14541 Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);
14545 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
14551 EmitT32_32(0xee300a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14560 rn.Encode(7, 16) | rm.Encode(5, 0));
14564 Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);
14568 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
14577 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14587 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14592 Delegate(kVaddhn, &Assembler::vaddhn, cond, dt, rd, rn, rm);
14596 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
14606 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14617 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14622 Delegate(kVaddl, &Assembler::vaddl, cond, dt, rd, rn, rm);
14626 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
14636 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14647 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14652 Delegate(kVaddw, &Assembler::vaddw, cond, dt, rd, rn, rm);
14658 DRegister rn,
14666 if (encoded_dt.IsValid() && rd.Is(rn)) {
14679 if (encoded_dt.IsValid() && rd.Is(rn)) {
14696 EmitT32_32(0xef000110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14704 EmitA32(0xf2000110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14710 Delegate(kVand, &Assembler::vand, cond, dt, rd, rn, operand);
14716 QRegister rn,
14724 if (encoded_dt.IsValid() && rd.Is(rn)) {
14737 if (encoded_dt.IsValid() && rd.Is(rn)) {
14754 EmitT32_32(0xef000150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14762 EmitA32(0xf2000150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14768 Delegate(kVand, &Assembler::vand, cond, dt, rd, rn, operand);
14774 DRegister rn,
14782 if (encoded_dt.IsValid() && rd.Is(rn)) {
14795 if (encoded_dt.IsValid() && rd.Is(rn)) {
14812 EmitT32_32(0xef100110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14820 EmitA32(0xf2100110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14826 Delegate(kVbic, &Assembler::vbic, cond, dt, rd, rn, operand);
14832 QRegister rn,
14840 if (encoded_dt.IsValid() && rd.Is(rn)) {
14853 if (encoded_dt.IsValid() && rd.Is(rn)) {
14870 EmitT32_32(0xef100150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14878 EmitA32(0xf2100150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14884 Delegate(kVbic, &Assembler::vbic, cond, dt, rd, rn, operand);
14888 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14895 EmitT32_32(0xff300110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14903 EmitA32(0xf3300110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14908 Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm);
14912 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14919 EmitT32_32(0xff300150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14927 EmitA32(0xf3300150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14932 Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm);
14936 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14943 EmitT32_32(0xff200110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14951 EmitA32(0xf3200110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14956 Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm);
14960 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14967 EmitT32_32(0xff200150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14975 EmitA32(0xf3200150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14980 Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm);
14984 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14991 EmitT32_32(0xff100110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
14999 EmitA32(0xf3100110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15004 Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm);
15008 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15015 EmitT32_32(0xff100150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15023 EmitA32(0xf3100150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15028 Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm);
15112 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15122 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15131 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15141 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15149 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15154 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);
15158 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15168 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15177 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15187 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15195 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15200 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);
15284 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15294 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15302 EmitT32_32(0xff000e00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15314 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15321 EmitA32(0xf3000e00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15327 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm);
15331 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15341 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15349 EmitT32_32(0xff000e40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15361 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15368 EmitA32(0xf3000e40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15374 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm);
15458 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15468 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15476 EmitT32_32(0xff200e00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15488 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15495 EmitA32(0xf3200e00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15501 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm);
15505 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15515 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15523 EmitT32_32(0xff200e40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15535 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15542 EmitA32(0xf3200e40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
15548 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm);
15632 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15642 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15650 EmitT32_32(0xff000e00U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15662 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15669 EmitA32(0xf3000e00U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15675 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);
15679 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15689 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15697 EmitT32_32(0xff000e40U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15709 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15716 EmitA32(0xf3000e40U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15722 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);
15860 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15870 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15878 EmitT32_32(0xff200e00U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15890 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15897 EmitA32(0xf3200e00U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15903 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm);
15907 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15917 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15925 EmitT32_32(0xff200e40U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15937 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15944 EmitA32(0xf3200e40U | rd.Encode(22, 12) | rn.Encode(5, 0) |
15950 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm);
17280 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17286 EmitT32_32(0xee800a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17295 rn.Encode(7, 16) | rm.Encode(5, 0));
17299 Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm);
17303 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17309 EmitT32_32(0xee800b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17318 rn.Encode(7, 16) | rm.Encode(5, 0));
17322 Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm);
17448 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17455 EmitT32_32(0xff000110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17463 EmitA32(0xf3000110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17468 Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm);
17472 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17479 EmitT32_32(0xff000150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17487 EmitA32(0xf3000150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17492 Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm);
17498 DRegister rn,
17510 EmitT32_32(0xefb00000U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17521 EmitT32_32(0xefb00000U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17531 EmitA32(0xf2b00000U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17541 EmitA32(0xf2b00000U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17549 Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);
17555 QRegister rn,
17567 EmitT32_32(0xefb00040U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17578 EmitT32_32(0xefb00040U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17588 EmitA32(0xf2b00040U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17598 EmitA32(0xf2b00040U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17606 Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);
17610 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17617 EmitT32_32(0xef000c10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17625 EmitT32_32(0xeea00b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17634 EmitA32(0xf2000c10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17642 rn.Encode(7, 16) | rm.Encode(5, 0));
17646 Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);
17650 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17657 EmitT32_32(0xef000c50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17667 EmitA32(0xf2000c50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17673 Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);
17677 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17683 EmitT32_32(0xeea00a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17692 rn.Encode(7, 16) | rm.Encode(5, 0));
17696 Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);
17700 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17707 EmitT32_32(0xef200c10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17715 EmitT32_32(0xeea00b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17724 EmitA32(0xf2200c10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17732 rn.Encode(7, 16) | rm.Encode(5, 0));
17736 Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);
17740 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17747 EmitT32_32(0xef200c50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17757 EmitA32(0xf2200c50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17763 Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);
17767 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17773 EmitT32_32(0xeea00a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17782 rn.Encode(7, 16) | rm.Encode(5, 0));
17786 Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);
17790 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17796 EmitT32_32(0xee900a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17805 rn.Encode(7, 16) | rm.Encode(5, 0));
17809 Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm);
17813 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17819 EmitT32_32(0xee900b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17828 rn.Encode(7, 16) | rm.Encode(5, 0));
17832 Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm);
17836 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17842 EmitT32_32(0xee900a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17851 rn.Encode(7, 16) | rm.Encode(5, 0));
17855 Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm);
17859 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17865 EmitT32_32(0xee900b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
17874 rn.Encode(7, 16) | rm.Encode(5, 0));
17878 Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm);
17882 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17892 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17903 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17908 Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm);
17912 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17922 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17933 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17938 Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm);
17942 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17952 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17963 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17968 Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm);
17972 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17982 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17993 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17998 Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm);
18008 Register rn = operand.GetBaseRegister();
18020 (!rn.IsPC() || AllowUnpredictable())) {
18043 (rn.GetCode() << 16));
18052 (!rn.IsPC() || AllowUnpredictable())) {
18075 (rn.GetCode() << 16));
18084 (!rn.IsPC() || AllowUnpredictable())) {
18091 (rn.GetCode() << 16));
18100 (!rn.IsPC() || AllowUnpredictable())) {
18107 (rn.GetCode() << 16));
18115 encoded_align_3.IsValid() && (!rn.IsPC() || AllowUnpredictable())) {
18120 first.Encode(22, 12) | (rn.GetCode() << 16));
18128 encoded_align_3.IsValid() && (!rn.IsPC() || AllowUnpredictable())) {
18133 first.Encode(22, 12) | (rn.GetCode() << 16));
18143 (!rn.IsPC() || AllowUnpredictable())) {
18166 (rn.GetCode() << 16));
18174 (!rn.IsPC() || AllowUnpredictable())) {
18197 (rn.GetCode() << 16));
18205 (!rn.IsPC() || AllowUnpredictable())) {
18212 (rn.GetCode() << 16));
18220 (!rn.IsPC() || AllowUnpredictable())) {
18227 (rn.GetCode() << 16));
18234 encoded_align_3.IsValid() && (!rn.IsPC() || AllowUnpredictable())) {
18239 first.Encode(22, 12) | (rn.GetCode() << 16));
18246 encoded_align_3.IsValid() && (!rn.IsPC() || AllowUnpredictable())) {
18251 first.Encode(22, 12) | (rn.GetCode() << 16));
18258 Register rn = operand.GetBaseRegister();
18270 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18293 (rn.GetCode() << 16) | rm.GetCode());
18301 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18308 (rn.GetCode() << 16) | rm.GetCode());
18316 (!rn.IsPC() || AllowUnpredictable())) {
18321 first.Encode(22, 12) | (rn.GetCode() << 16) |
18331 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18354 (rn.GetCode() << 16) | rm.GetCode());
18361 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18368 (rn.GetCode() << 16) | rm.GetCode());
18375 (!rn.IsPC() || AllowUnpredictable())) {
18380 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
18396 Register rn = operand.GetBaseRegister();
18409 (!rn.IsPC() || AllowUnpredictable())) {
18425 (rn.GetCode() << 16));
18436 (!rn.IsPC() || AllowUnpredictable())) {
18452 (rn.GetCode() << 16));
18462 (!rn.IsPC() || AllowUnpredictable())) {
18469 (rn.GetCode() << 16));
18479 (!rn.IsPC() || AllowUnpredictable())) {
18486 (rn.GetCode() << 16));
18496 (!rn.IsPC() || AllowUnpredictable())) {
18501 first.Encode(22, 12) | (rn.GetCode() << 16));
18511 (!rn.IsPC() || AllowUnpredictable())) {
18516 first.Encode(22, 12) | (rn.GetCode() << 16));
18528 (!rn.IsPC() || AllowUnpredictable())) {
18544 (rn.GetCode() << 16));
18554 (!rn.IsPC() || AllowUnpredictable())) {
18570 (rn.GetCode() << 16));
18579 (!rn.IsPC() || AllowUnpredictable())) {
18586 (rn.GetCode() << 16));
18595 (!rn.IsPC() || AllowUnpredictable())) {
18602 (rn.GetCode() << 16));
18611 (!rn.IsPC() || AllowUnpredictable())) {
18616 first.Encode(22, 12) | (rn.GetCode() << 16));
18625 (!rn.IsPC() || AllowUnpredictable())) {
18630 first.Encode(22, 12) | (rn.GetCode() << 16));
18637 Register rn = operand.GetBaseRegister();
18650 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18666 (rn.GetCode() << 16) | rm.GetCode());
18675 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18682 (rn.GetCode() << 16) | rm.GetCode());
18691 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18696 first.Encode(22, 12) | (rn.GetCode() << 16) |
18708 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18724 (rn.GetCode() << 16) | rm.GetCode());
18732 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18739 (rn.GetCode() << 16) | rm.GetCode());
18747 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18752 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
18768 Register rn = operand.GetBaseRegister();
18778 (!rn.IsPC() || AllowUnpredictable())) {
18785 (rn.GetCode() << 16));
18795 (!rn.IsPC() || AllowUnpredictable())) {
18802 (rn.GetCode() << 16));
18813 (!rn.IsPC() || AllowUnpredictable())) {
18820 (rn.GetCode() << 16));
18829 (!rn.IsPC() || AllowUnpredictable())) {
18836 (rn.GetCode() << 16));
18843 Register rn = operand.GetBaseRegister();
18853 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18860 (rn.GetCode() << 16) | rm.GetCode());
18870 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18877 (rn.GetCode() << 16) | rm.GetCode());
18893 Register rn = operand.GetBaseRegister();
18901 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
18907 (rn.GetCode() << 16));
18916 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
18922 (rn.GetCode() << 16));
18931 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
18936 first.Encode(22, 12) | (rn.GetCode() << 16));
18945 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
18950 first.Encode(22, 12) | (rn.GetCode() << 16));
18960 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
18966 (rn.GetCode() << 16));
18974 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
18980 (rn.GetCode() << 16));
18988 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
18993 first.Encode(22, 12) | (rn.GetCode() << 16));
19001 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
19006 first.Encode(22, 12) | (rn.GetCode() << 16));
19013 Register rn = operand.GetBaseRegister();
19024 (!rn.IsPC() || AllowUnpredictable())) {
19030 (rn.GetCode() << 16) | rm.GetCode());
19040 (!rn.IsPC() || AllowUnpredictable())) {
19045 first.Encode(22, 12) | (rn.GetCode() << 16) |
19057 (!rn.IsPC() || AllowUnpredictable())) {
19063 (rn.GetCode() << 16) | rm.GetCode());
19072 (!rn.IsPC() || AllowUnpredictable())) {
19077 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
19093 Register rn = operand.GetBaseRegister();
19106 (!rn.IsPC() || AllowUnpredictable())) {
19113 (rn.GetCode() << 16));
19123 (!rn.IsPC() || AllowUnpredictable())) {
19130 (rn.GetCode() << 16));
19140 (!rn.IsPC() || AllowUnpredictable())) {
19147 (rn.GetCode() << 16));
19157 (!rn.IsPC() || AllowUnpredictable())) {
19164 (rn.GetCode() << 16));
19174 (!rn.IsPC() || AllowUnpredictable())) {
19179 first.Encode(22, 12) | (rn.GetCode() << 16));
19189 (!rn.IsPC() || AllowUnpredictable())) {
19194 first.Encode(22, 12) | (rn.GetCode() << 16));
19205 (!rn.IsPC() || AllowUnpredictable())) {
19212 (rn.GetCode() << 16));
19221 (!rn.IsPC() || AllowUnpredictable())) {
19228 (rn.GetCode() << 16));
19237 (!rn.IsPC() || AllowUnpredictable())) {
19244 (rn.GetCode() << 16));
19253 (!rn.IsPC() || AllowUnpredictable())) {
19260 (rn.GetCode() << 16));
19269 (!rn.IsPC() || AllowUnpredictable())) {
19274 first.Encode(22, 12) | (rn.GetCode() << 16));
19283 (!rn.IsPC() || AllowUnpredictable())) {
19288 first.Encode(22, 12) | (rn.GetCode() << 16));
19295 Register rn = operand.GetBaseRegister();
19308 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19315 (rn.GetCode() << 16) | rm.GetCode());
19324 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19331 (rn.GetCode() << 16) | rm.GetCode());
19340 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19345 first.Encode(22, 12) | (rn.GetCode() << 16) |
19356 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19363 (rn.GetCode() << 16) | rm.GetCode());
19371 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19378 (rn.GetCode() << 16) | rm.GetCode());
19386 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19391 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
19402 Register rn,
19410 if ((((dreglist.GetLength() <= 16) && !rn.IsPC()) ||
19414 EmitT32_32(0xec900b00U | (rn.GetCode() << 16) |
19423 (!rn.IsPC() || !write_back.DoesWriteBack())) ||
19427 EmitA32(0x0c900b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
19433 Delegate(kVldm, &Assembler::vldm, cond, dt, rn, write_back, dreglist);
19438 Register rn,
19446 if ((!rn.IsPC() || AllowUnpredictable())) {
19449 EmitT32_32(0xec900a00U | (rn.GetCode() << 16) |
19458 ((!rn.IsPC() || !write_back.DoesWriteBack()) || AllowUnpredictable())) {
19461 EmitA32(0x0c900a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
19467 Delegate(kVldm, &Assembler::vldm, cond, dt, rn, write_back, sreglist);
19472 Register rn,
19481 (((dreglist.GetLength() <= 16) && !rn.IsPC()) ||
19485 EmitT32_32(0xed300b00U | (rn.GetCode() << 16) | dreg.Encode(22, 12) |
19493 (((dreglist.GetLength() <= 16) && !rn.IsPC()) ||
19497 EmitA32(0x0d300b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
19502 Delegate(kVldmdb, &Assembler::vldmdb, cond, dt, rn, write_back, dreglist);
19507 Register rn,
19515 if (write_back.DoesWriteBack() && (!rn.IsPC() || AllowUnpredictable())) {
19518 EmitT32_32(0xed300a00U | (rn.GetCode() << 16) | sreg.Encode(22, 12) |
19526 (!rn.IsPC() || AllowUnpredictable())) {
19529 EmitA32(0x0d300a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
19534 Delegate(kVldmdb, &Assembler::vldmdb, cond, dt, rn, write_back, sreglist);
19539 Register rn,
19547 if ((((dreglist.GetLength() <= 16) && !rn.IsPC()) ||
19551 EmitT32_32(0xec900b00U | (rn.GetCode() << 16) |
19560 (!rn.IsPC() || !write_back.DoesWriteBack())) ||
19564 EmitA32(0x0c900b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
19570 Delegate(kVldmia, &Assembler::vldmia, cond, dt, rn, write_back, dreglist);
19575 Register rn,
19583 if ((!rn.IsPC() || AllowUnpredictable())) {
19586 EmitT32_32(0xec900a00U | (rn.GetCode() << 16) |
19595 ((!rn.IsPC() || !write_back.DoesWriteBack()) || AllowUnpredictable())) {
19598 EmitA32(0x0c900a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
19604 Delegate(kVldmia, &Assembler::vldmia, cond, dt, rn, write_back, sreglist);
19712 Register rn = operand.GetBaseRegister();
19717 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset()) {
19727 ((rn.GetCode() & 0xf) != 0xf)) {
19730 EmitT32_32(0xed100b00U | rd.Encode(22, 12) | (rn.GetCode() << 16) |
19738 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset() &&
19749 ((rn.GetCode() & 0xf) != 0xf)) {
19753 (rn.GetCode() << 16) | offset_ | (sign << 23));
19866 Register rn = operand.GetBaseRegister();
19871 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset()) {
19881 ((rn.GetCode() & 0xf) != 0xf)) {
19884 EmitT32_32(0xed100a00U | rd.Encode(22, 12) | (rn.GetCode() << 16) |
19892 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset() &&
19903 ((rn.GetCode() & 0xf) != 0xf)) {
19907 (rn.GetCode() << 16) | offset_ | (sign << 23));
19916 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
19924 EmitT32_32(0xef000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
19935 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
19944 EmitA32(0xf2000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
19954 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
19959 Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm);
19963 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
19971 EmitT32_32(0xef000f40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
19982 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
19991 EmitA32(0xf2000f40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20001 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20006 Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm);
20009 void Assembler::vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20015 EmitT32_32(0xff000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20022 EmitT32_32(0xfe800b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20030 EmitA32(0xf3000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20036 EmitA32(0xfe800b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20041 Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);
20044 void Assembler::vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20050 EmitT32_32(0xff000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20058 EmitA32(0xf3000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20063 Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);
20066 void Assembler::vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20072 EmitT32_32(0xfe800a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20080 EmitA32(0xfe800a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20085 Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);
20089 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20097 EmitT32_32(0xef200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20108 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20117 EmitA32(0xf2200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20127 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20132 Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm);
20136 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20144 EmitT32_32(0xef200f40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20155 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20164 EmitA32(0xf2200f40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20174 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20179 Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm);
20182 void Assembler::vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20188 EmitT32_32(0xff200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20195 EmitT32_32(0xfe800b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20203 EmitA32(0xf3200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20209 EmitA32(0xfe800b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20214 Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);
20217 void Assembler::vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20223 EmitT32_32(0xff200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20231 EmitA32(0xf3200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20236 Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);
20239 void Assembler::vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20245 EmitT32_32(0xfe800a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20253 EmitA32(0xfe800a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20258 Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);
20262 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
20275 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20289 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20294 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20298 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
20311 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20325 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20330 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20334 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20342 EmitT32_32(0xef000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20350 EmitT32_32(0xee000b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20359 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20368 EmitA32(0xf2000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20376 rn.Encode(7, 16) | rm.Encode(5, 0));
20383 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20388 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20392 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20400 EmitT32_32(0xef000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20410 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20419 EmitA32(0xf2000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20428 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20433 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20437 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20443 EmitT32_32(0xee000a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20452 rn.Encode(7, 16) | rm.Encode(5, 0));
20456 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20460 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
20473 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20487 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20492 Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm);
20496 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
20506 rn.Encode(7, 16) | rm.Encode(5, 0));
20517 rn.Encode(7, 16) | rm.Encode(5, 0));
20522 Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm);
20526 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
20539 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20553 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20558 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20562 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
20575 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20589 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20594 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20598 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20606 EmitT32_32(0xef200d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20614 EmitT32_32(0xee000b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20623 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20632 EmitA32(0xf2200d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20640 rn.Encode(7, 16) | rm.Encode(5, 0));
20647 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20652 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20656 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20664 EmitT32_32(0xef200d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20674 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20683 EmitA32(0xf2200d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20692 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20697 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20701 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20707 EmitT32_32(0xee000a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
20716 rn.Encode(7, 16) | rm.Encode(5, 0));
20720 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20724 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
20737 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20751 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20756 Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm);
20760 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
20770 rn.Encode(7, 16) | rm.Encode(5, 0));
20781 rn.Encode(7, 16) | rm.Encode(5, 0));
20786 Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm);
20789 void Assembler::vmov(Condition cond, Register rt, SRegister rn) {
20795 EmitT32_32(0xee100a10U | (rt.GetCode() << 12) | rn.Encode(7, 16));
20803 rn.Encode(7, 16));
20807 Delegate(kVmov, &Assembler::vmov, cond, rt, rn);
20810 void Assembler::vmov(Condition cond, SRegister rn, Register rt) {
20816 EmitT32_32(0xee000a10U | rn.Encode(7, 16) | (rt.GetCode() << 12));
20823 EmitA32(0x0e000a10U | (cond.GetCondition() << 28) | rn.Encode(7, 16) |
20828 Delegate(kVmov, &Assembler::vmov, cond, rn, rt);
21167 DRegisterLane rn) {
21170 Dt_U_opc1_opc2_1 encoded_dt(dt, rn);
21177 (rt.GetCode() << 12) | rn.Encode(7, 16));
21189 (rt.GetCode() << 12) | rn.Encode(7, 16));
21193 Delegate(kVmov, &Assembler::vmov, cond, dt, rt, rn);
21298 DRegister rn,
21317 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21336 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21342 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, dm, index);
21348 QRegister rn,
21367 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21386 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21392 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, dm, index);
21396 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21404 EmitT32_32(0xff000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21412 EmitT32_32(0xee200b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21422 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21431 EmitA32(0xf3000d10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21439 rn.Encode(7, 16) | rm.Encode(5, 0));
21447 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21452 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);
21456 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
21464 EmitT32_32(0xff000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21475 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21484 EmitA32(0xf3000d50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21494 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21499 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);
21503 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21509 EmitT32_32(0xee200a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21518 rn.Encode(7, 16) | rm.Encode(5, 0));
21522 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);
21528 DRegister rn,
21548 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21568 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
21574 Delegate(kVmull, &Assembler::vmull, cond, dt, rd, rn, dm, index);
21578 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
21589 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21601 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21606 Delegate(kVmull, &Assembler::vmull, cond, dt, rd, rn, rm);
21811 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21817 EmitT32_32(0xee100a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21826 rn.Encode(7, 16) | rm.Encode(5, 0));
21830 Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm);
21834 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21840 EmitT32_32(0xee100b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21849 rn.Encode(7, 16) | rm.Encode(5, 0));
21853 Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm);
21857 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21863 EmitT32_32(0xee100a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21872 rn.Encode(7, 16) | rm.Encode(5, 0));
21876 Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm);
21880 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21886 EmitT32_32(0xee100b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21895 rn.Encode(7, 16) | rm.Encode(5, 0));
21899 Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm);
21903 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21909 EmitT32_32(0xee200a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21918 rn.Encode(7, 16) | rm.Encode(5, 0));
21922 Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm);
21926 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21932 EmitT32_32(0xee200b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21941 rn.Encode(7, 16) | rm.Encode(5, 0));
21945 Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm);
21951 DRegister rn,
21959 if (encoded_dt.IsValid() && rd.Is(rn)) {
21972 if (encoded_dt.IsValid() && rd.Is(rn)) {
21989 EmitT32_32(0xef300110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
21997 EmitA32(0xf2300110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22003 Delegate(kVorn, &Assembler::vorn, cond, dt, rd, rn, operand);
22009 QRegister rn,
22017 if (encoded_dt.IsValid() && rd.Is(rn)) {
22030 if (encoded_dt.IsValid() && rd.Is(rn)) {
22047 EmitT32_32(0xef300150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22055 EmitA32(0xf2300150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22061 Delegate(kVorn, &Assembler::vorn, cond, dt, rd, rn, operand);
22067 DRegister rn,
22077 EmitT32_32(0xef200110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22085 EmitA32(0xf2200110U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22095 if (encoded_dt.IsValid() && rd.Is(rn)) {
22108 if (encoded_dt.IsValid() && rd.Is(rn)) {
22119 Delegate(kVorr, &Assembler::vorr, cond, dt, rd, rn, operand);
22125 QRegister rn,
22135 EmitT32_32(0xef200150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22143 EmitA32(0xf2200150U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22153 if (encoded_dt.IsValid() && rd.Is(rn)) {
22166 if (encoded_dt.IsValid() && rd.Is(rn)) {
22177 Delegate(kVorr, &Assembler::vorr, cond, dt, rd, rn, operand);
22245 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22253 EmitT32_32(0xff000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22263 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22272 EmitA32(0xf3000d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22281 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22286 Delegate(kVpadd, &Assembler::vpadd, cond, dt, rd, rn, rm);
22354 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22362 EmitT32_32(0xff000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22373 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22382 EmitA32(0xf3000f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22392 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22397 Delegate(kVpmax, &Assembler::vpmax, cond, dt, rd, rn, rm);
22401 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22409 EmitT32_32(0xff200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22420 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22429 EmitA32(0xf3200f00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
22439 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22444 Delegate(kVpmin, &Assembler::vpmin, cond, dt, rd, rn, rm);
22604 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22614 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22625 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22630 Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm);
22634 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
22644 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22655 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22660 Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm);
22664 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
22673 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22683 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22688 Delegate(kVqdmlal, &Assembler::vqdmlal, cond, dt, rd, rn, rm);
22694 DRegister rn,
22713 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
22732 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
22738 Delegate(kVqdmlal, &Assembler::vqdmlal, cond, dt, rd, rn, dm, index);
22742 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
22751 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22761 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22766 Delegate(kVqdmlsl, &Assembler::vqdmlsl, cond, dt, rd, rn, rm);
22772 DRegister rn,
22791 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
22810 rd.Encode(22, 12) | rn.Encode(7, 16) | (mvm & 0xf) |
22816 Delegate(kVqdmlsl, &Assembler::vqdmlsl, cond, dt, rd, rn, dm, index);
22820 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22829 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22839 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22844 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22848 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
22857 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22867 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22872 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22876 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
22889 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22903 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22908 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22912 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
22925 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22939 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22944 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22948 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
22957 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22967 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22972 Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);
22976 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
22989 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23003 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23008 Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);
23128 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
23137 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23147 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23152 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23156 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
23165 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23175 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23180 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23184 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
23197 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23211 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23216 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23220 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
23233 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23247 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23252 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23256 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
23266 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23277 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23282 Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn);
23286 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
23296 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23307 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23312 Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn);
23444 DRegister rn = operand.GetRegister();
23453 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23464 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23513 QRegister rn = operand.GetRegister();
23522 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23533 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23780 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
23790 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23801 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23806 Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);
23810 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
23820 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23831 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23836 Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);
23840 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
23849 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23859 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23864 Delegate(kVraddhn, &Assembler::vraddhn, cond, dt, rd, rn, rm);
23932 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
23939 EmitT32_32(0xef000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
23949 EmitA32(0xf2000f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
23955 Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm);
23959 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
23966 EmitT32_32(0xef000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
23976 EmitA32(0xf2000f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
23982 Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm);
24166 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
24176 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24187 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24192 Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm);
24196 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
24206 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24217 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24222 Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm);
24752 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
24762 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24773 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24778 Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn);
24782 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
24792 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24803 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24808 Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn);
25052 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25059 EmitT32_32(0xef200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25069 EmitA32(0xf2200f10U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25075 Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm);
25079 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
25086 EmitT32_32(0xef200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25096 EmitA32(0xf2200f50U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25102 Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm);
25190 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
25199 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
25209 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
25214 Delegate(kVrsubhn, &Assembler::vrsubhn, cond, dt, rd, rn, rm);
25217 void Assembler::vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25223 EmitT32_32(0xfe000b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25231 EmitA32(0xfe000b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25236 Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm);
25239 void Assembler::vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25245 EmitT32_32(0xfe000a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25253 EmitA32(0xfe000a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25258 Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm);
25261 void Assembler::vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25267 EmitT32_32(0xfe200b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25275 EmitA32(0xfe200b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25280 Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm);
25283 void Assembler::vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25289 EmitT32_32(0xfe200a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25297 EmitA32(0xfe200a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25302 Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm);
25305 void Assembler::vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25311 EmitT32_32(0xfe300b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25319 EmitA32(0xfe300b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25324 Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm);
25327 void Assembler::vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25333 EmitT32_32(0xfe300a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25341 EmitA32(0xfe300a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25346 Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm);
25349 void Assembler::vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25355 EmitT32_32(0xfe100b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25363 EmitA32(0xfe100b00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25368 Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm);
25371 void Assembler::vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25377 EmitT32_32(0xfe100a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25385 EmitA32(0xfe100a00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
25390 Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm);
25433 DRegister rn = operand.GetRegister();
25442 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
25453 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
25502 QRegister rn = operand.GetRegister();
25511 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
25522 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
26066 Register rn = operand.GetBaseRegister();
26077 (!rn.IsPC() || AllowUnpredictable())) {
26100 (rn.GetCode() << 16));
26109 (!rn.IsPC() || AllowUnpredictable())) {
26132 (rn.GetCode() << 16));
26140 encoded_align_2.IsValid() && (!rn.IsPC() || AllowUnpredictable())) {
26145 first.Encode(22, 12) | (rn.GetCode() << 16));
26153 encoded_align_2.IsValid() && (!rn.IsPC() || AllowUnpredictable())) {
26158 first.Encode(22, 12) | (rn.GetCode() << 16));
26168 (!rn.IsPC() || AllowUnpredictable())) {
26191 (rn.GetCode() << 16));
26199 (!rn.IsPC() || AllowUnpredictable())) {
26222 (rn.GetCode() << 16));
26229 encoded_align_2.IsValid() && (!rn.IsPC() || AllowUnpredictable())) {
26234 first.Encode(22, 12) | (rn.GetCode() << 16));
26241 encoded_align_2.IsValid() && (!rn.IsPC() || AllowUnpredictable())) {
26246 first.Encode(22, 12) | (rn.GetCode() << 16));
26253 Register rn = operand.GetBaseRegister();
26264 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26287 (rn.GetCode() << 16) | rm.GetCode());
26295 (!rn.IsPC() || AllowUnpredictable())) {
26300 first.Encode(22, 12) | (rn.GetCode() << 16) |
26310 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26333 (rn.GetCode() << 16) | rm.GetCode());
26340 (!rn.IsPC() || AllowUnpredictable())) {
26345 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
26361 Register rn = operand.GetBaseRegister();
26373 (!rn.IsPC() || AllowUnpredictable())) {
26389 (rn.GetCode() << 16));
26400 (!rn.IsPC() || AllowUnpredictable())) {
26416 (rn.GetCode() << 16));
26426 (!rn.IsPC() || AllowUnpredictable())) {
26431 first.Encode(22, 12) | (rn.GetCode() << 16));
26441 (!rn.IsPC() || AllowUnpredictable())) {
26446 first.Encode(22, 12) | (rn.GetCode() << 16));
26458 (!rn.IsPC() || AllowUnpredictable())) {
26474 (rn.GetCode() << 16));
26484 (!rn.IsPC() || AllowUnpredictable())) {
26500 (rn.GetCode() << 16));
26509 (!rn.IsPC() || AllowUnpredictable())) {
26514 first.Encode(22, 12) | (rn.GetCode() << 16));
26523 (!rn.IsPC() || AllowUnpredictable())) {
26528 first.Encode(22, 12) | (rn.GetCode() << 16));
26535 Register rn = operand.GetBaseRegister();
26547 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26563 (rn.GetCode() << 16) | rm.GetCode());
26572 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26577 first.Encode(22, 12) | (rn.GetCode() << 16) |
26589 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26605 (rn.GetCode() << 16) | rm.GetCode());
26613 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26618 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
26634 Register rn = operand.GetBaseRegister();
26644 (!rn.IsPC() || AllowUnpredictable())) {
26651 (rn.GetCode() << 16));
26661 (!rn.IsPC() || AllowUnpredictable())) {
26668 (rn.GetCode() << 16));
26679 (!rn.IsPC() || AllowUnpredictable())) {
26686 (rn.GetCode() << 16));
26695 (!rn.IsPC() || AllowUnpredictable())) {
26702 (rn.GetCode() << 16));
26709 Register rn = operand.GetBaseRegister();
26719 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26726 (rn.GetCode() << 16) | rm.GetCode());
26736 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26743 (rn.GetCode() << 16) | rm.GetCode());
26759 Register rn = operand.GetBaseRegister();
26767 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
26772 first.Encode(22, 12) | (rn.GetCode() << 16));
26781 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
26786 first.Encode(22, 12) | (rn.GetCode() << 16));
26796 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
26801 first.Encode(22, 12) | (rn.GetCode() << 16));
26809 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
26814 first.Encode(22, 12) | (rn.GetCode() << 16));
26821 Register rn = operand.GetBaseRegister();
26832 (!rn.IsPC() || AllowUnpredictable())) {
26837 first.Encode(22, 12) | (rn.GetCode() << 16) |
26849 (!rn.IsPC() || AllowUnpredictable())) {
26854 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
26870 Register rn = operand.GetBaseRegister();
26881 (!rn.IsPC() || AllowUnpredictable())) {
26888 (rn.GetCode() << 16));
26898 (!rn.IsPC() || AllowUnpredictable())) {
26905 (rn.GetCode() << 16));
26915 (!rn.IsPC() || AllowUnpredictable())) {
26920 first.Encode(22, 12) | (rn.GetCode() << 16));
26930 (!rn.IsPC() || AllowUnpredictable())) {
26935 first.Encode(22, 12) | (rn.GetCode() << 16));
26946 (!rn.IsPC() || AllowUnpredictable())) {
26953 (rn.GetCode() << 16));
26962 (!rn.IsPC() || AllowUnpredictable())) {
26969 (rn.GetCode() << 16));
26978 (!rn.IsPC() || AllowUnpredictable())) {
26983 first.Encode(22, 12) | (rn.GetCode() << 16));
26992 (!rn.IsPC() || AllowUnpredictable())) {
26997 first.Encode(22, 12) | (rn.GetCode() << 16));
27004 Register rn = operand.GetBaseRegister();
27015 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
27022 (rn.GetCode() << 16) | rm.GetCode());
27031 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
27036 first.Encode(22, 12) | (rn.GetCode() << 16) |
27047 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
27054 (rn.GetCode() << 16) | rm.GetCode());
27062 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
27067 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
27078 Register rn,
27086 if ((((dreglist.GetLength() <= 16) && !rn.IsPC()) ||
27090 EmitT32_32(0xec800b00U | (rn.GetCode() << 16) |
27099 (!rn.IsPC() || !write_back.DoesWriteBack())) ||
27103 EmitA32(0x0c800b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
27109 Delegate(kVstm, &Assembler::vstm, cond, dt, rn, write_back, dreglist);
27114 Register rn,
27122 if ((!rn.IsPC() || AllowUnpredictable())) {
27125 EmitT32_32(0xec800a00U | (rn.GetCode() << 16) |
27134 ((!rn.IsPC() || !write_back.DoesWriteBack()) || AllowUnpredictable())) {
27137 EmitA32(0x0c800a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
27143 Delegate(kVstm, &Assembler::vstm, cond, dt, rn, write_back, sreglist);
27148 Register rn,
27157 (((dreglist.GetLength() <= 16) && !rn.IsPC()) ||
27161 EmitT32_32(0xed200b00U | (rn.GetCode() << 16) | dreg.Encode(22, 12) |
27169 (((dreglist.GetLength() <= 16) && !rn.IsPC()) ||
27173 EmitA32(0x0d200b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
27178 Delegate(kVstmdb, &Assembler::vstmdb, cond, dt, rn, write_back, dreglist);
27183 Register rn,
27191 if (write_back.DoesWriteBack() && (!rn.IsPC() || AllowUnpredictable())) {
27194 EmitT32_32(0xed200a00U | (rn.GetCode() << 16) | sreg.Encode(22, 12) |
27202 (!rn.IsPC() || AllowUnpredictable())) {
27205 EmitA32(0x0d200a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
27210 Delegate(kVstmdb, &Assembler::vstmdb, cond, dt, rn, write_back, sreglist);
27215 Register rn,
27223 if ((((dreglist.GetLength() <= 16) && !rn.IsPC()) ||
27227 EmitT32_32(0xec800b00U | (rn.GetCode() << 16) |
27236 (!rn.IsPC() || !write_back.DoesWriteBack())) ||
27240 EmitA32(0x0c800b00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
27246 Delegate(kVstmia, &Assembler::vstmia, cond, dt, rn, write_back, dreglist);
27251 Register rn,
27259 if ((!rn.IsPC() || AllowUnpredictable())) {
27262 EmitT32_32(0xec800a00U | (rn.GetCode() << 16) |
27271 ((!rn.IsPC() || !write_back.DoesWriteBack()) || AllowUnpredictable())) {
27274 EmitA32(0x0c800a00U | (cond.GetCondition() << 28) | (rn.GetCode() << 16) |
27280 Delegate(kVstmia, &Assembler::vstmia, cond, dt, rn, write_back, sreglist);
27290 Register rn = operand.GetBaseRegister();
27296 (!rn.IsPC() || AllowUnpredictable())) {
27299 EmitT32_32(0xed000b00U | rd.Encode(22, 12) | (rn.GetCode() << 16) |
27311 (rn.GetCode() << 16) | offset_ | (sign << 23));
27326 Register rn = operand.GetBaseRegister();
27332 (!rn.IsPC() || AllowUnpredictable())) {
27335 EmitT32_32(0xed000a00U | rd.Encode(22, 12) | (rn.GetCode() << 16) |
27347 (rn.GetCode() << 16) | offset_ | (sign << 23));
27356 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
27364 EmitT32_32(0xef200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27372 EmitT32_32(0xee300b40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27381 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27390 EmitA32(0xf2200d00U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27398 rn.Encode(7, 16) | rm.Encode(5, 0));
27405 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27410 Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);
27414 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
27422 EmitT32_32(0xef200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27432 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27441 EmitA32(0xf2200d40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27450 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27455 Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);
27459 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
27465 EmitT32_32(0xee300a40U | rd.Encode(22, 12) | rn.Encode(7, 16) |
27474 rn.Encode(7, 16) | rm.Encode(5, 0));
27478 Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);
27482 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
27491 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27501 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27506 Delegate(kVsubhn, &Assembler::vsubhn, cond, dt, rd, rn, rm);
27510 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
27520 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27531 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27536 Delegate(kVsubl, &Assembler::vsubl, cond, dt, rd, rn, rm);
27540 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
27550 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27561 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27566 Delegate(kVsubw, &Assembler::vsubw, cond, dt, rd, rn, rm);
27738 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
27747 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27757 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27762 Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm);
27766 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
27775 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27785 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27790 Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm);