Lines Matching refs:rm
1956 Register rm = operand.GetBaseRegister();
1961 rm.IsLow()) {
1962 EmitT32_16(0x4140 | rd.GetCode() | (rm.GetCode() << 3));
1973 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
1976 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
1986 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
1993 Register rm = operand.GetBaseRegister();
1999 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2002 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2044 Register rm = operand.GetBaseRegister();
2049 rm.IsLow()) {
2050 EmitT32_16(0x4140 | rd.GetCode() | (rm.GetCode() << 3));
2061 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2064 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
2074 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2081 Register rm = operand.GetBaseRegister();
2087 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2090 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2217 Register rm = operand.GetBaseRegister();
2222 rm.IsLow()) {
2224 (rm.GetCode() << 6));
2229 if (!size.IsWide() && rd.Is(rn) && !rm.Is(sp) &&
2231 (!rd.IsPC() || !rm.IsPC())) ||
2234 ((rd.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));
2239 if (!size.IsWide() && rd.Is(rm) && rn.Is(sp) &&
2248 if (!size.IsWide() && rd.Is(sp) && rn.Is(sp) && !rm.Is(sp)) {
2249 EmitT32_16(0x4485 | (rm.GetCode() << 3));
2260 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2263 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
2270 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2272 EmitT32_32(0xeb0d0000U | (rd.GetCode() << 8) | rm.GetCode() |
2283 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2291 (rd.GetCode() << 12) | rm.GetCode() |
2298 Register rm = operand.GetBaseRegister();
2304 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2307 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2331 Register rm = operand.GetBaseRegister();
2334 if (InITBlock() && !rm.Is(sp) &&
2336 (!rd.IsPC() || !rm.IsPC())) ||
2339 (rm.GetCode() << 3));
2411 Register rm = operand.GetBaseRegister();
2416 rm.IsLow()) {
2418 (rm.GetCode() << 6));
2429 !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2432 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
2439 !rd.Is(pc) && (!rm.IsPC() || AllowUnpredictable())) {
2441 EmitT32_32(0xeb1d0000U | (rd.GetCode() << 8) | rm.GetCode() |
2452 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2460 (rd.GetCode() << 12) | rm.GetCode() |
2467 Register rm = operand.GetBaseRegister();
2473 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2476 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2730 Register rm = operand.GetBaseRegister();
2735 rm.IsLow()) {
2736 EmitT32_16(0x4000 | rd.GetCode() | (rm.GetCode() << 3));
2747 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2750 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
2760 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2767 Register rm = operand.GetBaseRegister();
2773 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2776 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2818 Register rm = operand.GetBaseRegister();
2823 rm.IsLow()) {
2824 EmitT32_16(0x4000 | rd.GetCode() | (rm.GetCode() << 3));
2835 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2838 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
2848 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2855 Register rm = operand.GetBaseRegister();
2861 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
2864 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
2876 Register rm,
2884 if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&
2887 EmitT32_16(0x1000 | rd.GetCode() | (rm.GetCode() << 3) |
2894 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2896 EmitT32_32(0xea4f0020U | (rd.GetCode() << 8) | rm.GetCode() |
2906 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));
2915 if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
2923 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
2924 EmitT32_32(0xfa40f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
2932 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
2934 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
2939 Delegate(kAsr, &Assembler::asr, cond, size, rd, rm, operand);
2945 Register rm,
2953 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&
2956 EmitT32_16(0x1000 | rd.GetCode() | (rm.GetCode() << 3) |
2963 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
2965 EmitT32_32(0xea5f0020U | (rd.GetCode() << 8) | rm.GetCode() |
2975 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));
2984 if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
2992 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
2993 EmitT32_32(0xfa50f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
3001 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
3003 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
3008 Delegate(kAsrs, &Assembler::asrs, cond, size, rd, rm, operand);
3283 Register rm = operand.GetBaseRegister();
3288 rm.IsLow()) {
3289 EmitT32_16(0x4380 | rd.GetCode() | (rm.GetCode() << 3));
3300 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3303 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
3313 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3320 Register rm = operand.GetBaseRegister();
3326 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
3329 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3371 Register rm = operand.GetBaseRegister();
3376 rm.IsLow()) {
3377 EmitT32_16(0x4380 | rd.GetCode() | (rm.GetCode() << 3));
3388 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3391 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
3401 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3408 Register rm = operand.GetBaseRegister();
3414 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
3417 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
3622 void Assembler::blx(Condition cond, Register rm) {
3627 if (((!rm.IsPC() && OutsideITBlockAndAlOrLast(cond)) ||
3629 EmitT32_16(0x4780 | (rm.GetCode() << 3));
3635 if (cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {
3636 EmitA32(0x012fff30U | (cond.GetCondition() << 28) | rm.GetCode());
3640 Delegate(kBlx, &Assembler::blx, cond, rm);
3643 void Assembler::bx(Condition cond, Register rm) {
3649 EmitT32_16(0x4700 | (rm.GetCode() << 3));
3656 EmitA32(0x012fff10U | (cond.GetCondition() << 28) | rm.GetCode());
3660 Delegate(kBx, &Assembler::bx, cond, rm);
3663 void Assembler::bxj(Condition cond, Register rm) {
3668 if (((!rm.IsPC() && OutsideITBlockAndAlOrLast(cond)) ||
3670 EmitT32_32(0xf3c08f00U | (rm.GetCode() << 16));
3676 if (cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {
3677 EmitA32(0x012fff20U | (cond.GetCondition() << 28) | rm.GetCode());
3681 Delegate(kBxj, &Assembler::bxj, cond, rm);
3800 void Assembler::clz(Condition cond, Register rd, Register rm) {
3805 if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3806 EmitT32_32(0xfab0f080U | (rd.GetCode() << 8) | rm.GetCode() |
3807 (rm.GetCode() << 16));
3814 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3816 rm.GetCode());
3820 Delegate(kClz, &Assembler::clz, cond, rd, rm);
3854 Register rm = operand.GetBaseRegister();
3858 if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {
3859 EmitT32_16(0x42c0 | rn.GetCode() | (rm.GetCode() << 3));
3870 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3872 EmitT32_32(0xeb100f00U | (rn.GetCode() << 16) | rm.GetCode() |
3883 (rn.GetCode() << 16) | rm.GetCode() |
3890 Register rm = operand.GetBaseRegister();
3896 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
3898 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |
3944 Register rm = operand.GetBaseRegister();
3948 if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {
3949 EmitT32_16(0x4280 | rn.GetCode() | (rm.GetCode() << 3));
3955 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3957 ((rn.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));
3968 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
3970 EmitT32_32(0xebb00f00U | (rn.GetCode() << 16) | rm.GetCode() |
3981 (rn.GetCode() << 16) | rm.GetCode() |
3988 Register rm = operand.GetBaseRegister();
3994 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
3996 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |
4005 void Assembler::crc32b(Condition cond, Register rd, Register rn, Register rm) {
4010 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4013 rm.GetCode());
4020 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4022 (rn.GetCode() << 16) | rm.GetCode());
4026 Delegate(kCrc32b, &Assembler::crc32b, cond, rd, rn, rm);
4029 void Assembler::crc32cb(Condition cond, Register rd, Register rn, Register rm) {
4034 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4037 rm.GetCode());
4044 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4046 (rn.GetCode() << 16) | rm.GetCode());
4050 Delegate(kCrc32cb, &Assembler::crc32cb, cond, rd, rn, rm);
4053 void Assembler::crc32ch(Condition cond, Register rd, Register rn, Register rm) {
4058 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4061 rm.GetCode());
4068 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4070 (rn.GetCode() << 16) | rm.GetCode());
4074 Delegate(kCrc32ch, &Assembler::crc32ch, cond, rd, rn, rm);
4077 void Assembler::crc32cw(Condition cond, Register rd, Register rn, Register rm) {
4082 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4085 rm.GetCode());
4092 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4094 (rn.GetCode() << 16) | rm.GetCode());
4098 Delegate(kCrc32cw, &Assembler::crc32cw, cond, rd, rn, rm);
4101 void Assembler::crc32h(Condition cond, Register rd, Register rn, Register rm) {
4106 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4109 rm.GetCode());
4116 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4118 (rn.GetCode() << 16) | rm.GetCode());
4122 Delegate(kCrc32h, &Assembler::crc32h, cond, rd, rn, rm);
4125 void Assembler::crc32w(Condition cond, Register rd, Register rn, Register rm) {
4130 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && OutsideITBlock()) ||
4133 rm.GetCode());
4140 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4142 (rn.GetCode() << 16) | rm.GetCode());
4146 Delegate(kCrc32w, &Assembler::crc32w, cond, rd, rn, rm);
4218 Register rm = operand.GetBaseRegister();
4223 rm.IsLow()) {
4224 EmitT32_16(0x4040 | rd.GetCode() | (rm.GetCode() << 3));
4235 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4238 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
4248 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
4255 Register rm = operand.GetBaseRegister();
4261 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
4264 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
4306 Register rm = operand.GetBaseRegister();
4311 rm.IsLow()) {
4312 EmitT32_16(0x4040 | rd.GetCode() | (rm.GetCode() << 3));
4323 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
4326 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
4336 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
4343 Register rm = operand.GetBaseRegister();
4349 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
4352 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5120 Register rm = operand.GetOffsetRegister();
5123 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
5126 (rm.GetCode() << 6));
5135 Register rm = operand.GetOffsetRegister();
5142 ((!rm.IsPC() && (!rt.IsPC() || OutsideITBlockAndAlOrLast(cond))) ||
5145 rm.GetCode() | (amount << 4));
5152 (!rm.IsPC() || AllowUnpredictable())) {
5157 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5163 cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {
5168 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5174 (!rm.IsPC() || AllowUnpredictable())) {
5179 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5423 Register rm = operand.GetOffsetRegister();
5426 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
5429 (rm.GetCode() << 6));
5438 Register rm = operand.GetOffsetRegister();
5445 (!rm.IsPC() || AllowUnpredictable())) {
5447 rm.GetCode() | (amount << 4));
5454 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
5459 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5466 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
5471 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5477 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
5482 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5691 Register rm = operand.GetOffsetRegister();
5696 ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||
5700 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5707 ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||
5711 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
5718 ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||
5722 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6057 Register rm = operand.GetOffsetRegister();
6060 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
6063 (rm.GetCode() << 6));
6070 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6073 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6079 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6082 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6088 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6091 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6100 Register rm = operand.GetOffsetRegister();
6107 (!rm.IsPC() || AllowUnpredictable())) {
6109 rm.GetCode() | (amount << 4));
6312 Register rm = operand.GetOffsetRegister();
6315 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
6318 (rm.GetCode() << 6));
6325 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6328 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6334 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6337 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6343 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6346 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6355 Register rm = operand.GetOffsetRegister();
6362 (!rm.IsPC() || AllowUnpredictable())) {
6364 rm.GetCode() | (amount << 4));
6567 Register rm = operand.GetOffsetRegister();
6570 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
6573 (rm.GetCode() << 6));
6580 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6583 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6589 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6592 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6598 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6601 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
6610 Register rm = operand.GetOffsetRegister();
6617 (!rm.IsPC() || AllowUnpredictable())) {
6619 rm.GetCode() | (amount << 4));
6720 Register rm,
6728 if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&
6730 EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) | (imm << 6));
6736 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6737 EmitT32_32(0xea4f0000U | (rd.GetCode() << 8) | rm.GetCode() |
6746 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));
6755 if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
6763 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6764 EmitT32_32(0xfa00f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
6772 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6774 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
6779 Delegate(kLsl, &Assembler::lsl, cond, size, rd, rm, operand);
6785 Register rm,
6793 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&
6795 EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) | (imm << 6));
6801 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6802 EmitT32_32(0xea5f0000U | (rd.GetCode() << 8) | rm.GetCode() |
6811 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));
6820 if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
6828 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6829 EmitT32_32(0xfa10f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
6837 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6839 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
6844 Delegate(kLsls, &Assembler::lsls, cond, size, rd, rm, operand);
6850 Register rm,
6858 if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&
6861 EmitT32_16(0x0800 | rd.GetCode() | (rm.GetCode() << 3) |
6868 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6870 EmitT32_32(0xea4f0010U | (rd.GetCode() << 8) | rm.GetCode() |
6880 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));
6889 if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
6897 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6898 EmitT32_32(0xfa20f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
6906 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6908 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
6913 Delegate(kLsr, &Assembler::lsr, cond, size, rd, rm, operand);
6919 Register rm,
6927 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow() &&
6930 EmitT32_16(0x0800 | rd.GetCode() | (rm.GetCode() << 3) |
6937 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6939 EmitT32_32(0xea5f0010U | (rd.GetCode() << 8) | rm.GetCode() |
6949 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 7));
6958 if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
6966 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6967 EmitT32_32(0xfa30f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
6975 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
6977 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
6982 Delegate(kLsrs, &Assembler::lsrs, cond, size, rd, rm, operand);
6986 Condition cond, Register rd, Register rn, Register rm, Register ra) {
6992 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
6994 rm.GetCode() | (ra.GetCode() << 12));
7001 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
7004 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
7008 Delegate(kMla, &Assembler::mla, cond, rd, rn, rm, ra);
7012 Condition cond, Register rd, Register rn, Register rm, Register ra) {
7018 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
7021 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
7025 Delegate(kMlas, &Assembler::mlas, cond, rd, rn, rm, ra);
7029 Condition cond, Register rd, Register rn, Register rm, Register ra) {
7034 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
7037 rm.GetCode() | (ra.GetCode() << 12));
7044 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
7047 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
7051 Delegate(kMls, &Assembler::mls, cond, rd, rn, rm, ra);
7061 Register rm = operand.GetBaseRegister();
7069 ((rd.GetCode() & 0x8) << 4) | (rm.GetCode() << 3));
7080 shift.IsValidAmount(amount) && rm.IsLow() &&
7084 EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) |
7091 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7093 EmitT32_32(0xea4f0000U | (rd.GetCode() << 8) | rm.GetCode() |
7104 (rd.GetCode() << 12) | rm.GetCode() |
7111 Register rm = operand.GetBaseRegister();
7116 if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7123 if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7130 if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7137 if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7145 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7146 EmitT32_32(0xfa00f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
7154 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7156 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |
7218 Register rm = operand.GetBaseRegister();
7224 shift.IsValidAmount(amount) && rm.IsLow() &&
7227 EmitT32_16(0x0000 | rd.GetCode() | (rm.GetCode() << 3) |
7234 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7236 EmitT32_32(0xea5f0000U | (rd.GetCode() << 8) | rm.GetCode() |
7248 (rd.GetCode() << 12) | rm.GetCode() |
7255 Register rm = operand.GetBaseRegister();
7260 if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7267 if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7274 if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7281 if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
7289 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7290 EmitT32_32(0xfa10f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
7298 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7300 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |
7457 Condition cond, EncodingSize size, Register rd, Register rn, Register rm) {
7462 if (InITBlock() && !size.IsWide() && rd.Is(rm) && rn.IsLow() &&
7463 rm.IsLow()) {
7470 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7472 rm.GetCode());
7479 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7481 rn.GetCode() | (rm.GetCode() << 8));
7485 Delegate(kMul, &Assembler::mul, cond, size, rd, rn, rm);
7488 void Assembler::muls(Condition cond, Register rd, Register rn, Register rm) {
7493 if (OutsideITBlock() && rd.Is(rm) && rn.IsLow() && rm.IsLow()) {
7501 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7503 rn.GetCode() | (rm.GetCode() << 8));
7507 Delegate(kMuls, &Assembler::muls, cond, rd, rn, rm);
7541 Register rm = operand.GetBaseRegister();
7545 if (InITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow()) {
7546 EmitT32_16(0x43c0 | rd.GetCode() | (rm.GetCode() << 3));
7557 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7559 EmitT32_32(0xea6f0000U | (rd.GetCode() << 8) | rm.GetCode() |
7570 (rd.GetCode() << 12) | rm.GetCode() |
7577 Register rm = operand.GetBaseRegister();
7583 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7585 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |
7625 Register rm = operand.GetBaseRegister();
7629 if (OutsideITBlock() && !size.IsWide() && rd.IsLow() && rm.IsLow()) {
7630 EmitT32_16(0x43c0 | rd.GetCode() | (rm.GetCode() << 3));
7641 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7643 EmitT32_32(0xea7f0000U | (rd.GetCode() << 8) | rm.GetCode() |
7654 (rd.GetCode() << 12) | rm.GetCode() |
7661 Register rm = operand.GetBaseRegister();
7667 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
7669 (rd.GetCode() << 12) | rm.GetCode() | (shift.GetType() << 5) |
7727 Register rm = operand.GetBaseRegister();
7733 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7736 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
7769 Register rm = operand.GetBaseRegister();
7775 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7778 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
7821 Register rm = operand.GetBaseRegister();
7826 rm.IsLow()) {
7827 EmitT32_16(0x4300 | rd.GetCode() | (rm.GetCode() << 3));
7838 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7841 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
7851 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7858 Register rm = operand.GetBaseRegister();
7864 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
7867 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7909 Register rm = operand.GetBaseRegister();
7914 rm.IsLow()) {
7915 EmitT32_16(0x4300 | rd.GetCode() | (rm.GetCode() << 3));
7926 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7929 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
7939 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7946 Register rm = operand.GetBaseRegister();
7952 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
7955 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
7971 Register rm = operand.GetBaseRegister();
7977 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7979 rm.GetCode() | ((amount & 0x3) << 6) |
7987 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
7989 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
8005 Register rm = operand.GetBaseRegister();
8011 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8014 rm.GetCode() | ((amount_ & 0x3) << 6) |
8023 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8026 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
8179 Register rm = operand.GetOffsetRegister();
8186 (!rm.IsPC() || AllowUnpredictable())) {
8187 EmitT32_32(0xf810f000U | (rn.GetCode() << 16) | rm.GetCode() |
8195 (!rm.IsPC() || AllowUnpredictable())) {
8199 EmitA32(0xf750f000U | (rn.GetCode() << 16) | rm.GetCode() |
8206 (!rm.IsPC() || AllowUnpredictable())) {
8209 EmitA32(0xf750f060U | (rn.GetCode() << 16) | rm.GetCode() |
8256 Register rm = operand.GetOffsetRegister();
8263 (!rm.IsPC() || AllowUnpredictable())) {
8264 EmitT32_32(0xf830f000U | (rn.GetCode() << 16) | rm.GetCode() |
8272 (!rm.IsPC() || AllowUnpredictable())) {
8276 EmitA32(0xf710f000U | (rn.GetCode() << 16) | rm.GetCode() |
8283 (!rm.IsPC() || AllowUnpredictable())) {
8286 EmitA32(0xf710f060U | (rn.GetCode() << 16) | rm.GetCode() |
8359 Register rm = operand.GetOffsetRegister();
8366 (!rm.IsPC() || AllowUnpredictable())) {
8367 EmitT32_32(0xf910f000U | (rn.GetCode() << 16) | rm.GetCode() |
8375 (!rm.IsPC() || AllowUnpredictable())) {
8378 EmitA32(0xf650f060U | (rn.GetCode() << 16) | rm.GetCode() |
8385 (!rm.IsPC() || AllowUnpredictable())) {
8389 EmitA32(0xf650f000U | (rn.GetCode() << 16) | rm.GetCode() |
8611 void Assembler::qadd(Condition cond, Register rd, Register rm, Register rn) {
8616 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8617 EmitT32_32(0xfa80f080U | (rd.GetCode() << 8) | rm.GetCode() |
8625 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8627 rm.GetCode() | (rn.GetCode() << 16));
8631 Delegate(kQadd, &Assembler::qadd, cond, rd, rm, rn);
8634 void Assembler::qadd16(Condition cond, Register rd, Register rn, Register rm) {
8639 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8641 rm.GetCode());
8648 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8650 (rn.GetCode() << 16) | rm.GetCode());
8654 Delegate(kQadd16, &Assembler::qadd16, cond, rd, rn, rm);
8657 void Assembler::qadd8(Condition cond, Register rd, Register rn, Register rm) {
8662 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8664 rm.GetCode());
8671 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8673 (rn.GetCode() << 16) | rm.GetCode());
8677 Delegate(kQadd8, &Assembler::qadd8, cond, rd, rn, rm);
8680 void Assembler::qasx(Condition cond, Register rd, Register rn, Register rm) {
8685 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8687 rm.GetCode());
8694 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8696 (rn.GetCode() << 16) | rm.GetCode());
8700 Delegate(kQasx, &Assembler::qasx, cond, rd, rn, rm);
8703 void Assembler::qdadd(Condition cond, Register rd, Register rm, Register rn) {
8708 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8709 EmitT32_32(0xfa80f090U | (rd.GetCode() << 8) | rm.GetCode() |
8717 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8719 rm.GetCode() | (rn.GetCode() << 16));
8723 Delegate(kQdadd, &Assembler::qdadd, cond, rd, rm, rn);
8726 void Assembler::qdsub(Condition cond, Register rd, Register rm, Register rn) {
8731 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8732 EmitT32_32(0xfa80f0b0U | (rd.GetCode() << 8) | rm.GetCode() |
8740 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8742 rm.GetCode() | (rn.GetCode() << 16));
8746 Delegate(kQdsub, &Assembler::qdsub, cond, rd, rm, rn);
8749 void Assembler::qsax(Condition cond, Register rd, Register rn, Register rm) {
8754 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8756 rm.GetCode());
8763 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8765 (rn.GetCode() << 16) | rm.GetCode());
8769 Delegate(kQsax, &Assembler::qsax, cond, rd, rn, rm);
8772 void Assembler::qsub(Condition cond, Register rd, Register rm, Register rn) {
8777 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8778 EmitT32_32(0xfa80f0a0U | (rd.GetCode() << 8) | rm.GetCode() |
8786 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8788 rm.GetCode() | (rn.GetCode() << 16));
8792 Delegate(kQsub, &Assembler::qsub, cond, rd, rm, rn);
8795 void Assembler::qsub16(Condition cond, Register rd, Register rn, Register rm) {
8800 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8802 rm.GetCode());
8809 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8811 (rn.GetCode() << 16) | rm.GetCode());
8815 Delegate(kQsub16, &Assembler::qsub16, cond, rd, rn, rm);
8818 void Assembler::qsub8(Condition cond, Register rd, Register rn, Register rm) {
8823 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8825 rm.GetCode());
8832 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8834 (rn.GetCode() << 16) | rm.GetCode());
8838 Delegate(kQsub8, &Assembler::qsub8, cond, rd, rn, rm);
8841 void Assembler::rbit(Condition cond, Register rd, Register rm) {
8846 if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8847 EmitT32_32(0xfa90f0a0U | (rd.GetCode() << 8) | rm.GetCode() |
8848 (rm.GetCode() << 16));
8855 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8857 rm.GetCode());
8861 Delegate(kRbit, &Assembler::rbit, cond, rd, rm);
8867 Register rm) {
8872 if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
8873 EmitT32_16(0xba00 | rd.GetCode() | (rm.GetCode() << 3));
8879 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8880 EmitT32_32(0xfa90f080U | (rd.GetCode() << 8) | rm.GetCode() |
8881 (rm.GetCode() << 16));
8888 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8890 rm.GetCode());
8894 Delegate(kRev, &Assembler::rev, cond, size, rd, rm);
8900 Register rm) {
8905 if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
8906 EmitT32_16(0xba40 | rd.GetCode() | (rm.GetCode() << 3));
8912 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8913 EmitT32_32(0xfa90f090U | (rd.GetCode() << 8) | rm.GetCode() |
8914 (rm.GetCode() << 16));
8921 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8923 rm.GetCode());
8927 Delegate(kRev16, &Assembler::rev16, cond, size, rd, rm);
8933 Register rm) {
8938 if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
8939 EmitT32_16(0xbac0 | rd.GetCode() | (rm.GetCode() << 3));
8945 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8946 EmitT32_32(0xfa90f0b0U | (rd.GetCode() << 8) | rm.GetCode() |
8947 (rm.GetCode() << 16));
8954 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8956 rm.GetCode());
8960 Delegate(kRevsh, &Assembler::revsh, cond, size, rd, rm);
8966 Register rm,
8975 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
8976 EmitT32_32(0xea4f0030U | (rd.GetCode() << 8) | rm.GetCode() |
8985 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));
8994 if (InITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
9002 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
9003 EmitT32_32(0xfa60f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
9011 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
9013 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
9018 Delegate(kRor, &Assembler::ror, cond, size, rd, rm, operand);
9024 Register rm,
9033 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9034 EmitT32_32(0xea5f0030U | (rd.GetCode() << 8) | rm.GetCode() |
9043 (rd.GetCode() << 12) | rm.GetCode() | (imm << 7));
9052 if (OutsideITBlock() && !size.IsWide() && rd.Is(rm) && rm.IsLow() &&
9060 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
9061 EmitT32_32(0xfa70f000U | (rd.GetCode() << 8) | (rm.GetCode() << 16) |
9069 ((!rd.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
9071 (rd.GetCode() << 12) | rm.GetCode() | (rs.GetCode() << 8));
9076 Delegate(kRors, &Assembler::rors, cond, size, rd, rm, operand);
9079 void Assembler::rrx(Condition cond, Register rd, Register rm) {
9084 if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9085 EmitT32_32(0xea4f0030U | (rd.GetCode() << 8) | rm.GetCode());
9093 rm.GetCode());
9097 Delegate(kRrx, &Assembler::rrx, cond, rd, rm);
9100 void Assembler::rrxs(Condition cond, Register rd, Register rm) {
9105 if (((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9106 EmitT32_32(0xea5f0030U | (rd.GetCode() << 8) | rm.GetCode());
9114 rm.GetCode());
9118 Delegate(kRrxs, &Assembler::rrxs, cond, rd, rm);
9161 Register rm = operand.GetBaseRegister();
9167 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9170 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
9180 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9187 Register rm = operand.GetBaseRegister();
9193 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9196 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9245 Register rm = operand.GetBaseRegister();
9251 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9254 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
9264 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9271 Register rm = operand.GetBaseRegister();
9277 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9280 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9309 Register rm = operand.GetBaseRegister();
9317 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9324 Register rm = operand.GetBaseRegister();
9330 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9333 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9362 Register rm = operand.GetBaseRegister();
9370 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9377 Register rm = operand.GetBaseRegister();
9383 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9386 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9395 void Assembler::sadd16(Condition cond, Register rd, Register rn, Register rm) {
9400 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9402 rm.GetCode());
9409 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9411 (rn.GetCode() << 16) | rm.GetCode());
9415 Delegate(kSadd16, &Assembler::sadd16, cond, rd, rn, rm);
9418 void Assembler::sadd8(Condition cond, Register rd, Register rn, Register rm) {
9423 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9425 rm.GetCode());
9432 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9434 (rn.GetCode() << 16) | rm.GetCode());
9438 Delegate(kSadd8, &Assembler::sadd8, cond, rd, rn, rm);
9441 void Assembler::sasx(Condition cond, Register rd, Register rn, Register rm) {
9446 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9448 rm.GetCode());
9455 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9457 (rn.GetCode() << 16) | rm.GetCode());
9461 Delegate(kSasx, &Assembler::sasx, cond, rd, rn, rm);
9497 Register rm = operand.GetBaseRegister();
9502 rm.IsLow()) {
9503 EmitT32_16(0x4180 | rd.GetCode() | (rm.GetCode() << 3));
9514 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9517 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
9527 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9534 Register rm = operand.GetBaseRegister();
9540 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9543 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9585 Register rm = operand.GetBaseRegister();
9590 rm.IsLow()) {
9591 EmitT32_16(0x4180 | rd.GetCode() | (rm.GetCode() << 3));
9602 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9605 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
9615 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9622 Register rm = operand.GetBaseRegister();
9628 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
9631 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
9669 void Assembler::sdiv(Condition cond, Register rd, Register rn, Register rm) {
9674 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9676 rm.GetCode());
9683 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9685 rn.GetCode() | (rm.GetCode() << 8));
9689 Delegate(kSdiv, &Assembler::sdiv, cond, rd, rn, rm);
9692 void Assembler::sel(Condition cond, Register rd, Register rn, Register rm) {
9697 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9699 rm.GetCode());
9706 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9708 (rn.GetCode() << 16) | rm.GetCode());
9712 Delegate(kSel, &Assembler::sel, cond, rd, rn, rm);
9715 void Assembler::shadd16(Condition cond, Register rd, Register rn, Register rm) {
9720 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9722 rm.GetCode());
9729 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9731 (rn.GetCode() << 16) | rm.GetCode());
9735 Delegate(kShadd16, &Assembler::shadd16, cond, rd, rn, rm);
9738 void Assembler::shadd8(Condition cond, Register rd, Register rn, Register rm) {
9743 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9745 rm.GetCode());
9752 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9754 (rn.GetCode() << 16) | rm.GetCode());
9758 Delegate(kShadd8, &Assembler::shadd8, cond, rd, rn, rm);
9761 void Assembler::shasx(Condition cond, Register rd, Register rn, Register rm) {
9766 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9768 rm.GetCode());
9775 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9777 (rn.GetCode() << 16) | rm.GetCode());
9781 Delegate(kShasx, &Assembler::shasx, cond, rd, rn, rm);
9784 void Assembler::shsax(Condition cond, Register rd, Register rn, Register rm) {
9789 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9791 rm.GetCode());
9798 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9800 (rn.GetCode() << 16) | rm.GetCode());
9804 Delegate(kShsax, &Assembler::shsax, cond, rd, rn, rm);
9807 void Assembler::shsub16(Condition cond, Register rd, Register rn, Register rm) {
9812 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9814 rm.GetCode());
9821 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9823 (rn.GetCode() << 16) | rm.GetCode());
9827 Delegate(kShsub16, &Assembler::shsub16, cond, rd, rn, rm);
9830 void Assembler::shsub8(Condition cond, Register rd, Register rn, Register rm) {
9835 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9837 rm.GetCode());
9844 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9846 (rn.GetCode() << 16) | rm.GetCode());
9850 Delegate(kShsub8, &Assembler::shsub8, cond, rd, rn, rm);
9854 Condition cond, Register rd, Register rn, Register rm, Register ra) {
9860 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9862 rm.GetCode() | (ra.GetCode() << 12));
9869 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
9872 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
9876 Delegate(kSmlabb, &Assembler::smlabb, cond, rd, rn, rm, ra);
9880 Condition cond, Register rd, Register rn, Register rm, Register ra) {
9886 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9888 rm.GetCode() | (ra.GetCode() << 12));
9895 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
9898 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
9902 Delegate(kSmlabt, &Assembler::smlabt, cond, rd, rn, rm, ra);
9906 Condition cond, Register rd, Register rn, Register rm, Register ra) {
9912 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9914 rm.GetCode() | (ra.GetCode() << 12));
9921 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9923 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
9927 Delegate(kSmlad, &Assembler::smlad, cond, rd, rn, rm, ra);
9931 Condition cond, Register rd, Register rn, Register rm, Register ra) {
9937 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9939 rm.GetCode() | (ra.GetCode() << 12));
9946 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
9948 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
9952 Delegate(kSmladx, &Assembler::smladx, cond, rd, rn, rm, ra);
9956 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
9961 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
9964 (rn.GetCode() << 16) | rm.GetCode());
9971 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
9975 (rm.GetCode() << 8));
9979 Delegate(kSmlal, &Assembler::smlal, cond, rdlo, rdhi, rn, rm);
9983 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
9988 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
9991 (rn.GetCode() << 16) | rm.GetCode());
9998 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10002 (rm.GetCode() << 8));
10006 Delegate(kSmlalbb, &Assembler::smlalbb, cond, rdlo, rdhi, rn, rm);
10010 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10015 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10018 (rn.GetCode() << 16) | rm.GetCode());
10025 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10029 (rm.GetCode() << 8));
10033 Delegate(kSmlalbt, &Assembler::smlalbt, cond, rdlo, rdhi, rn, rm);
10037 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10042 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10045 (rn.GetCode() << 16) | rm.GetCode());
10052 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10056 (rm.GetCode() << 8));
10060 Delegate(kSmlald, &Assembler::smlald, cond, rdlo, rdhi, rn, rm);
10064 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10069 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10072 (rn.GetCode() << 16) | rm.GetCode());
10079 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10083 (rm.GetCode() << 8));
10087 Delegate(kSmlaldx, &Assembler::smlaldx, cond, rdlo, rdhi, rn, rm);
10091 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10097 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10101 (rm.GetCode() << 8));
10105 Delegate(kSmlals, &Assembler::smlals, cond, rdlo, rdhi, rn, rm);
10109 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10114 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10117 (rn.GetCode() << 16) | rm.GetCode());
10124 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10128 (rm.GetCode() << 8));
10132 Delegate(kSmlaltb, &Assembler::smlaltb, cond, rdlo, rdhi, rn, rm);
10136 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10141 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10144 (rn.GetCode() << 16) | rm.GetCode());
10151 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10155 (rm.GetCode() << 8));
10159 Delegate(kSmlaltt, &Assembler::smlaltt, cond, rdlo, rdhi, rn, rm);
10163 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10169 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10171 rm.GetCode() | (ra.GetCode() << 12));
10178 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10181 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10185 Delegate(kSmlatb, &Assembler::smlatb, cond, rd, rn, rm, ra);
10189 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10195 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10197 rm.GetCode() | (ra.GetCode() << 12));
10204 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10207 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10211 Delegate(kSmlatt, &Assembler::smlatt, cond, rd, rn, rm, ra);
10215 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10221 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10223 rm.GetCode() | (ra.GetCode() << 12));
10230 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10233 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10237 Delegate(kSmlawb, &Assembler::smlawb, cond, rd, rn, rm, ra);
10241 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10247 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10249 rm.GetCode() | (ra.GetCode() << 12));
10256 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10259 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10263 Delegate(kSmlawt, &Assembler::smlawt, cond, rd, rn, rm, ra);
10267 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10273 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10275 rm.GetCode() | (ra.GetCode() << 12));
10282 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10284 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10288 Delegate(kSmlsd, &Assembler::smlsd, cond, rd, rn, rm, ra);
10292 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10298 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10300 rm.GetCode() | (ra.GetCode() << 12));
10307 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10309 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10313 Delegate(kSmlsdx, &Assembler::smlsdx, cond, rd, rn, rm, ra);
10317 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10322 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10325 (rn.GetCode() << 16) | rm.GetCode());
10332 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10336 (rm.GetCode() << 8));
10340 Delegate(kSmlsld, &Assembler::smlsld, cond, rdlo, rdhi, rn, rm);
10344 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10349 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10352 (rn.GetCode() << 16) | rm.GetCode());
10359 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10363 (rm.GetCode() << 8));
10367 Delegate(kSmlsldx, &Assembler::smlsldx, cond, rdlo, rdhi, rn, rm);
10371 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10377 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10379 rm.GetCode() | (ra.GetCode() << 12));
10386 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10388 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10392 Delegate(kSmmla, &Assembler::smmla, cond, rd, rn, rm, ra);
10396 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10402 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10404 rm.GetCode() | (ra.GetCode() << 12));
10411 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10413 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10417 Delegate(kSmmlar, &Assembler::smmlar, cond, rd, rn, rm, ra);
10421 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10426 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10429 rm.GetCode() | (ra.GetCode() << 12));
10436 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10439 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10443 Delegate(kSmmls, &Assembler::smmls, cond, rd, rn, rm, ra);
10447 Condition cond, Register rd, Register rn, Register rm, Register ra) {
10452 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10455 rm.GetCode() | (ra.GetCode() << 12));
10462 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !ra.IsPC()) ||
10465 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
10469 Delegate(kSmmlsr, &Assembler::smmlsr, cond, rd, rn, rm, ra);
10472 void Assembler::smmul(Condition cond, Register rd, Register rn, Register rm) {
10477 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10479 rm.GetCode());
10486 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10488 rn.GetCode() | (rm.GetCode() << 8));
10492 Delegate(kSmmul, &Assembler::smmul, cond, rd, rn, rm);
10495 void Assembler::smmulr(Condition cond, Register rd, Register rn, Register rm) {
10500 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10502 rm.GetCode());
10509 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10511 rn.GetCode() | (rm.GetCode() << 8));
10515 Delegate(kSmmulr, &Assembler::smmulr, cond, rd, rn, rm);
10518 void Assembler::smuad(Condition cond, Register rd, Register rn, Register rm) {
10523 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10525 rm.GetCode());
10532 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10534 rn.GetCode() | (rm.GetCode() << 8));
10538 Delegate(kSmuad, &Assembler::smuad, cond, rd, rn, rm);
10541 void Assembler::smuadx(Condition cond, Register rd, Register rn, Register rm) {
10546 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10548 rm.GetCode());
10555 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10557 rn.GetCode() | (rm.GetCode() << 8));
10561 Delegate(kSmuadx, &Assembler::smuadx, cond, rd, rn, rm);
10564 void Assembler::smulbb(Condition cond, Register rd, Register rn, Register rm) {
10569 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10571 rm.GetCode());
10578 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10580 rn.GetCode() | (rm.GetCode() << 8));
10584 Delegate(kSmulbb, &Assembler::smulbb, cond, rd, rn, rm);
10587 void Assembler::smulbt(Condition cond, Register rd, Register rn, Register rm) {
10592 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10594 rm.GetCode());
10601 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10603 rn.GetCode() | (rm.GetCode() << 8));
10607 Delegate(kSmulbt, &Assembler::smulbt, cond, rd, rn, rm);
10611 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10616 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10619 (rn.GetCode() << 16) | rm.GetCode());
10626 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10630 (rm.GetCode() << 8));
10634 Delegate(kSmull, &Assembler::smull, cond, rdlo, rdhi, rn, rm);
10638 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
10644 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
10648 (rm.GetCode() << 8));
10652 Delegate(kSmulls, &Assembler::smulls, cond, rdlo, rdhi, rn, rm);
10655 void Assembler::smultb(Condition cond, Register rd, Register rn, Register rm) {
10660 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10662 rm.GetCode());
10669 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10671 rn.GetCode() | (rm.GetCode() << 8));
10675 Delegate(kSmultb, &Assembler::smultb, cond, rd, rn, rm);
10678 void Assembler::smultt(Condition cond, Register rd, Register rn, Register rm) {
10683 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10685 rm.GetCode());
10692 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10694 rn.GetCode() | (rm.GetCode() << 8));
10698 Delegate(kSmultt, &Assembler::smultt, cond, rd, rn, rm);
10701 void Assembler::smulwb(Condition cond, Register rd, Register rn, Register rm) {
10706 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10708 rm.GetCode());
10715 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10717 rn.GetCode() | (rm.GetCode() << 8));
10721 Delegate(kSmulwb, &Assembler::smulwb, cond, rd, rn, rm);
10724 void Assembler::smulwt(Condition cond, Register rd, Register rn, Register rm) {
10729 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10731 rm.GetCode());
10738 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10740 rn.GetCode() | (rm.GetCode() << 8));
10744 Delegate(kSmulwt, &Assembler::smulwt, cond, rd, rn, rm);
10747 void Assembler::smusd(Condition cond, Register rd, Register rn, Register rm) {
10752 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10754 rm.GetCode());
10761 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10763 rn.GetCode() | (rm.GetCode() << 8));
10767 Delegate(kSmusd, &Assembler::smusd, cond, rd, rn, rm);
10770 void Assembler::smusdx(Condition cond, Register rd, Register rn, Register rm) {
10775 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10777 rm.GetCode());
10784 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10786 rn.GetCode() | (rm.GetCode() << 8));
10790 Delegate(kSmusdx, &Assembler::smusdx, cond, rd, rn, rm);
10878 void Assembler::ssax(Condition cond, Register rd, Register rn, Register rm) {
10883 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10885 rm.GetCode());
10892 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10894 (rn.GetCode() << 16) | rm.GetCode());
10898 Delegate(kSsax, &Assembler::ssax, cond, rd, rn, rm);
10901 void Assembler::ssub16(Condition cond, Register rd, Register rn, Register rm) {
10906 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10908 rm.GetCode());
10915 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10917 (rn.GetCode() << 16) | rm.GetCode());
10921 Delegate(kSsub16, &Assembler::ssub16, cond, rd, rn, rm);
10924 void Assembler::ssub8(Condition cond, Register rd, Register rn, Register rm) {
10929 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10931 rm.GetCode());
10938 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
10940 (rn.GetCode() << 16) | rm.GetCode());
10944 Delegate(kSsub8, &Assembler::ssub8, cond, rd, rn, rm);
11478 Register rm = operand.GetOffsetRegister();
11481 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
11484 (rm.GetCode() << 6));
11493 Register rm = operand.GetOffsetRegister();
11500 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
11502 rm.GetCode() | (amount << 4));
11509 (!rm.IsPC() || AllowUnpredictable())) {
11514 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11520 cond.IsNotNever() && (!rm.IsPC() || AllowUnpredictable())) {
11525 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11531 (!rm.IsPC() || AllowUnpredictable())) {
11536 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11639 Register rm = operand.GetOffsetRegister();
11642 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
11645 (rm.GetCode() << 6));
11654 Register rm = operand.GetOffsetRegister();
11661 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
11663 rm.GetCode() | (amount << 4));
11670 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
11675 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11682 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
11687 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11693 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
11698 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11792 Register rm = operand.GetOffsetRegister();
11797 ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||
11801 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11808 ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||
11812 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
11819 ((((rt.GetCode() & 1) == 0) && !rt2.IsPC() && !rm.IsPC()) ||
11823 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12055 Register rm = operand.GetOffsetRegister();
12058 if (!size.IsWide() && rt.IsLow() && rn.IsLow() && rm.IsLow() &&
12061 (rm.GetCode() << 6));
12068 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12071 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12077 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12080 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12086 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12089 (rt.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12098 Register rm = operand.GetOffsetRegister();
12105 ((!rt.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12107 rm.GetCode() | (amount << 4));
12218 Register rm = operand.GetBaseRegister();
12223 rm.IsLow()) {
12225 (rm.GetCode() << 6));
12230 if (rn.Is(sp) && ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12231 EmitT32_32(0xebad0000U | (rd.GetCode() << 8) | rm.GetCode());
12242 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12245 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
12252 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12254 EmitT32_32(0xebad0000U | (rd.GetCode() << 8) | rm.GetCode() |
12265 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12273 (rd.GetCode() << 12) | rm.GetCode() |
12280 Register rm = operand.GetBaseRegister();
12286 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
12289 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12385 Register rm = operand.GetBaseRegister();
12390 rm.IsLow()) {
12392 (rm.GetCode() << 6));
12403 !rd.Is(pc) && ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12406 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
12413 !rd.Is(pc) && (!rm.IsPC() || AllowUnpredictable())) {
12415 EmitT32_32(0xebbd0000U | (rd.GetCode() << 8) | rm.GetCode() |
12426 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12434 (rd.GetCode() << 12) | rm.GetCode() |
12441 Register rm = operand.GetBaseRegister();
12447 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) ||
12450 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12532 Register rm = operand.GetBaseRegister();
12539 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12542 rm.GetCode() | (amount_ << 4));
12550 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12553 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12569 Register rm = operand.GetBaseRegister();
12576 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12579 rm.GetCode() | (amount_ << 4));
12587 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12590 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12606 Register rm = operand.GetBaseRegister();
12613 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12616 rm.GetCode() | (amount_ << 4));
12624 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12627 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
12643 Register rm = operand.GetBaseRegister();
12647 if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
12648 EmitT32_16(0xb240 | rd.GetCode() | (rm.GetCode() << 3));
12660 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12662 EmitT32_32(0xfa4ff080U | (rd.GetCode() << 8) | rm.GetCode() |
12671 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12674 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
12686 Register rm = operand.GetBaseRegister();
12693 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12695 EmitT32_32(0xfa2ff080U | (rd.GetCode() << 8) | rm.GetCode() |
12704 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12707 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
12722 Register rm = operand.GetBaseRegister();
12726 if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
12727 EmitT32_16(0xb200 | rd.GetCode() | (rm.GetCode() << 3));
12739 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12741 EmitT32_32(0xfa0ff080U | (rd.GetCode() << 8) | rm.GetCode() |
12750 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12753 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
12761 void Assembler::tbb(Condition cond, Register rn, Register rm) {
12767 (!rm.IsPC() || AllowUnpredictable())) {
12768 EmitT32_32(0xe8d0f000U | (rn.GetCode() << 16) | rm.GetCode());
12773 Delegate(kTbb, &Assembler::tbb, cond, rn, rm);
12776 void Assembler::tbh(Condition cond, Register rn, Register rm) {
12782 (!rm.IsPC() || AllowUnpredictable())) {
12783 EmitT32_32(0xe8d0f010U | (rn.GetCode() << 16) | rm.GetCode());
12788 Delegate(kTbh, &Assembler::tbh, cond, rn, rm);
12818 Register rm = operand.GetBaseRegister();
12824 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12826 EmitT32_32(0xea900f00U | (rn.GetCode() << 16) | rm.GetCode() |
12837 (rn.GetCode() << 16) | rm.GetCode() |
12844 Register rm = operand.GetBaseRegister();
12850 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
12852 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |
12892 Register rm = operand.GetBaseRegister();
12896 if (!size.IsWide() && rn.IsLow() && rm.IsLow()) {
12897 EmitT32_16(0x4200 | rn.GetCode() | (rm.GetCode() << 3));
12908 ((!rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12910 EmitT32_32(0xea100f00U | (rn.GetCode() << 16) | rm.GetCode() |
12921 (rn.GetCode() << 16) | rm.GetCode() |
12928 Register rm = operand.GetBaseRegister();
12934 ((!rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || AllowUnpredictable())) {
12936 (rn.GetCode() << 16) | rm.GetCode() | (shift.GetType() << 5) |
12945 void Assembler::uadd16(Condition cond, Register rd, Register rn, Register rm) {
12950 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12952 rm.GetCode());
12959 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12961 (rn.GetCode() << 16) | rm.GetCode());
12965 Delegate(kUadd16, &Assembler::uadd16, cond, rd, rn, rm);
12968 void Assembler::uadd8(Condition cond, Register rd, Register rn, Register rm) {
12973 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12975 rm.GetCode());
12982 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12984 (rn.GetCode() << 16) | rm.GetCode());
12988 Delegate(kUadd8, &Assembler::uadd8, cond, rd, rn, rm);
12991 void Assembler::uasx(Condition cond, Register rd, Register rn, Register rm) {
12996 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
12998 rm.GetCode());
13005 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13007 (rn.GetCode() << 16) | rm.GetCode());
13011 Delegate(kUasx, &Assembler::uasx, cond, rd, rn, rm);
13075 void Assembler::udiv(Condition cond, Register rd, Register rn, Register rm) {
13080 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13082 rm.GetCode());
13089 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13091 rn.GetCode() | (rm.GetCode() << 8));
13095 Delegate(kUdiv, &Assembler::udiv, cond, rd, rn, rm);
13098 void Assembler::uhadd16(Condition cond, Register rd, Register rn, Register rm) {
13103 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13105 rm.GetCode());
13112 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13114 (rn.GetCode() << 16) | rm.GetCode());
13118 Delegate(kUhadd16, &Assembler::uhadd16, cond, rd, rn, rm);
13121 void Assembler::uhadd8(Condition cond, Register rd, Register rn, Register rm) {
13126 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13128 rm.GetCode());
13135 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13137 (rn.GetCode() << 16) | rm.GetCode());
13141 Delegate(kUhadd8, &Assembler::uhadd8, cond, rd, rn, rm);
13144 void Assembler::uhasx(Condition cond, Register rd, Register rn, Register rm) {
13149 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13151 rm.GetCode());
13158 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13160 (rn.GetCode() << 16) | rm.GetCode());
13164 Delegate(kUhasx, &Assembler::uhasx, cond, rd, rn, rm);
13167 void Assembler::uhsax(Condition cond, Register rd, Register rn, Register rm) {
13172 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13174 rm.GetCode());
13181 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13183 (rn.GetCode() << 16) | rm.GetCode());
13187 Delegate(kUhsax, &Assembler::uhsax, cond, rd, rn, rm);
13190 void Assembler::uhsub16(Condition cond, Register rd, Register rn, Register rm) {
13195 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13197 rm.GetCode());
13204 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13206 (rn.GetCode() << 16) | rm.GetCode());
13210 Delegate(kUhsub16, &Assembler::uhsub16, cond, rd, rn, rm);
13213 void Assembler::uhsub8(Condition cond, Register rd, Register rn, Register rm) {
13218 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13220 rm.GetCode());
13227 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13229 (rn.GetCode() << 16) | rm.GetCode());
13233 Delegate(kUhsub8, &Assembler::uhsub8, cond, rd, rn, rm);
13237 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
13242 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13245 (rn.GetCode() << 16) | rm.GetCode());
13252 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13256 (rm.GetCode() << 8));
13260 Delegate(kUmaal, &Assembler::umaal, cond, rdlo, rdhi, rn, rm);
13264 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
13269 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13272 (rn.GetCode() << 16) | rm.GetCode());
13279 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13283 (rm.GetCode() << 8));
13287 Delegate(kUmlal, &Assembler::umlal, cond, rdlo, rdhi, rn, rm);
13291 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
13297 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13301 (rm.GetCode() << 8));
13305 Delegate(kUmlals, &Assembler::umlals, cond, rdlo, rdhi, rn, rm);
13309 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
13314 if (((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13317 (rn.GetCode() << 16) | rm.GetCode());
13324 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13328 (rm.GetCode() << 8));
13332 Delegate(kUmull, &Assembler::umull, cond, rdlo, rdhi, rn, rm);
13336 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) {
13342 ((!rdlo.IsPC() && !rdhi.IsPC() && !rn.IsPC() && !rm.IsPC()) ||
13346 (rm.GetCode() << 8));
13350 Delegate(kUmulls, &Assembler::umulls, cond, rdlo, rdhi, rn, rm);
13353 void Assembler::uqadd16(Condition cond, Register rd, Register rn, Register rm) {
13358 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13360 rm.GetCode());
13367 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13369 (rn.GetCode() << 16) | rm.GetCode());
13373 Delegate(kUqadd16, &Assembler::uqadd16, cond, rd, rn, rm);
13376 void Assembler::uqadd8(Condition cond, Register rd, Register rn, Register rm) {
13381 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13383 rm.GetCode());
13390 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13392 (rn.GetCode() << 16) | rm.GetCode());
13396 Delegate(kUqadd8, &Assembler::uqadd8, cond, rd, rn, rm);
13399 void Assembler::uqasx(Condition cond, Register rd, Register rn, Register rm) {
13404 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13406 rm.GetCode());
13413 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13415 (rn.GetCode() << 16) | rm.GetCode());
13419 Delegate(kUqasx, &Assembler::uqasx, cond, rd, rn, rm);
13422 void Assembler::uqsax(Condition cond, Register rd, Register rn, Register rm) {
13427 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13429 rm.GetCode());
13436 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13438 (rn.GetCode() << 16) | rm.GetCode());
13442 Delegate(kUqsax, &Assembler::uqsax, cond, rd, rn, rm);
13445 void Assembler::uqsub16(Condition cond, Register rd, Register rn, Register rm) {
13450 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13452 rm.GetCode());
13459 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13461 (rn.GetCode() << 16) | rm.GetCode());
13465 Delegate(kUqsub16, &Assembler::uqsub16, cond, rd, rn, rm);
13468 void Assembler::uqsub8(Condition cond, Register rd, Register rn, Register rm) {
13473 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13475 rm.GetCode());
13482 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13484 (rn.GetCode() << 16) | rm.GetCode());
13488 Delegate(kUqsub8, &Assembler::uqsub8, cond, rd, rn, rm);
13491 void Assembler::usad8(Condition cond, Register rd, Register rn, Register rm) {
13496 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13498 rm.GetCode());
13505 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13507 rn.GetCode() | (rm.GetCode() << 8));
13511 Delegate(kUsad8, &Assembler::usad8, cond, rd, rn, rm);
13515 Condition cond, Register rd, Register rn, Register rm, Register ra) {
13521 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13523 rm.GetCode() | (ra.GetCode() << 12));
13530 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13532 rn.GetCode() | (rm.GetCode() << 8) | (ra.GetCode() << 12));
13536 Delegate(kUsada8, &Assembler::usada8, cond, rd, rn, rm, ra);
13615 void Assembler::usax(Condition cond, Register rd, Register rn, Register rm) {
13620 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13622 rm.GetCode());
13629 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13631 (rn.GetCode() << 16) | rm.GetCode());
13635 Delegate(kUsax, &Assembler::usax, cond, rd, rn, rm);
13638 void Assembler::usub16(Condition cond, Register rd, Register rn, Register rm) {
13643 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13645 rm.GetCode());
13652 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13654 (rn.GetCode() << 16) | rm.GetCode());
13658 Delegate(kUsub16, &Assembler::usub16, cond, rd, rn, rm);
13661 void Assembler::usub8(Condition cond, Register rd, Register rn, Register rm) {
13666 if (((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13668 rm.GetCode());
13675 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13677 (rn.GetCode() << 16) | rm.GetCode());
13681 Delegate(kUsub8, &Assembler::usub8, cond, rd, rn, rm);
13691 Register rm = operand.GetBaseRegister();
13698 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13701 rm.GetCode() | (amount_ << 4));
13709 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13712 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
13728 Register rm = operand.GetBaseRegister();
13735 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13738 rm.GetCode() | (amount_ << 4));
13746 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13749 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
13765 Register rm = operand.GetBaseRegister();
13772 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13775 rm.GetCode() | (amount_ << 4));
13783 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13786 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() |
13802 Register rm = operand.GetBaseRegister();
13806 if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
13807 EmitT32_16(0xb2c0 | rd.GetCode() | (rm.GetCode() << 3));
13819 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13821 EmitT32_32(0xfa5ff080U | (rd.GetCode() << 8) | rm.GetCode() |
13830 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13833 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
13845 Register rm = operand.GetBaseRegister();
13852 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13854 EmitT32_32(0xfa3ff080U | (rd.GetCode() << 8) | rm.GetCode() |
13863 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13866 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
13881 Register rm = operand.GetBaseRegister();
13885 if (!size.IsWide() && rd.IsLow() && rm.IsLow()) {
13886 EmitT32_16(0xb280 | rd.GetCode() | (rm.GetCode() << 3));
13898 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13900 EmitT32_32(0xfa1ff080U | (rd.GetCode() << 8) | rm.GetCode() |
13909 ((!rd.IsPC() && !rm.IsPC()) || AllowUnpredictable())) {
13912 (rd.GetCode() << 12) | rm.GetCode() | (amount_ << 10));
13921 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
13931 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13942 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13947 Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm);
13951 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
13961 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13972 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
13977 Delegate(kVaba, &Assembler::vaba, cond, dt, rd, rn, rm);
13981 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
13991 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14002 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14007 Delegate(kVabal, &Assembler::vabal, cond, dt, rd, rn, rm);
14011 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14020 rm.Encode(5, 0));
14030 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14040 rm.Encode(5, 0));
14049 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14054 Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm);
14058 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14067 rm.Encode(5, 0));
14077 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14087 rm.Encode(5, 0));
14096 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14101 Delegate(kVabd, &Assembler::vabd, cond, dt, rd, rn, rm);
14105 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
14115 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14126 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14131 Delegate(kVabdl, &Assembler::vabdl, cond, dt, rd, rn, rm);
14134 void Assembler::vabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {
14144 rd.Encode(22, 12) | rm.Encode(5, 0));
14151 EmitT32_32(0xeeb00bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
14161 rd.Encode(22, 12) | rm.Encode(5, 0));
14168 rm.Encode(5, 0));
14172 Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);
14175 void Assembler::vabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {
14185 rd.Encode(22, 12) | rm.Encode(5, 0));
14196 rd.Encode(22, 12) | rm.Encode(5, 0));
14201 Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);
14204 void Assembler::vabs(Condition cond, DataType dt, SRegister rd, SRegister rm) {
14210 EmitT32_32(0xeeb00ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
14218 rm.Encode(5, 0));
14222 Delegate(kVabs, &Assembler::vabs, cond, dt, rd, rm);
14226 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14234 rm.Encode(5, 0));
14244 rm.Encode(5, 0));
14249 Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm);
14253 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14261 rm.Encode(5, 0));
14271 rm.Encode(5, 0));
14276 Delegate(kVacge, &Assembler::vacge, cond, dt, rd, rn, rm);
14280 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14288 rm.Encode(5, 0));
14298 rm.Encode(5, 0));
14303 Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm);
14307 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14315 rm.Encode(5, 0));
14325 rm.Encode(5, 0));
14330 Delegate(kVacgt, &Assembler::vacgt, cond, dt, rd, rn, rm);
14334 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14342 rm.Encode(5, 0));
14352 rm.Encode(5, 0));
14357 Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm);
14361 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14369 rm.Encode(5, 0));
14379 rm.Encode(5, 0));
14384 Delegate(kVacle, &Assembler::vacle, cond, dt, rd, rn, rm);
14388 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14396 rm.Encode(5, 0));
14406 rm.Encode(5, 0));
14411 Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm);
14415 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14423 rm.Encode(5, 0));
14433 rm.Encode(5, 0));
14438 Delegate(kVaclt, &Assembler::vaclt, cond, dt, rd, rn, rm);
14442 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14451 rm.Encode(5, 0));
14459 rm.Encode(5, 0));
14467 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14477 rm.Encode(5, 0));
14484 rn.Encode(7, 16) | rm.Encode(5, 0));
14491 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14496 Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);
14500 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14509 rm.Encode(5, 0));
14518 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14528 rm.Encode(5, 0));
14536 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14541 Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);
14545 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
14552 rm.Encode(5, 0));
14560 rn.Encode(7, 16) | rm.Encode(5, 0));
14564 Delegate(kVadd, &Assembler::vadd, cond, dt, rd, rn, rm);
14568 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
14577 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14587 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14592 Delegate(kVaddhn, &Assembler::vaddhn, cond, dt, rd, rn, rm);
14596 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
14606 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14617 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14622 Delegate(kVaddl, &Assembler::vaddl, cond, dt, rd, rn, rm);
14626 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
14636 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14647 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
14652 Delegate(kVaddw, &Assembler::vaddw, cond, dt, rd, rn, rm);
14691 DRegister rm = operand.GetRegister();
14697 rm.Encode(5, 0));
14705 rm.Encode(5, 0));
14749 QRegister rm = operand.GetRegister();
14755 rm.Encode(5, 0));
14763 rm.Encode(5, 0));
14807 DRegister rm = operand.GetRegister();
14813 rm.Encode(5, 0));
14821 rm.Encode(5, 0));
14865 QRegister rm = operand.GetRegister();
14871 rm.Encode(5, 0));
14879 rm.Encode(5, 0));
14888 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14896 rm.Encode(5, 0));
14904 rm.Encode(5, 0));
14908 Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm);
14912 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14920 rm.Encode(5, 0));
14928 rm.Encode(5, 0));
14932 Delegate(kVbif, &Assembler::vbif, cond, dt, rd, rn, rm);
14936 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14944 rm.Encode(5, 0));
14952 rm.Encode(5, 0));
14956 Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm);
14960 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
14968 rm.Encode(5, 0));
14976 rm.Encode(5, 0));
14980 Delegate(kVbit, &Assembler::vbit, cond, dt, rd, rn, rm);
14984 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
14992 rm.Encode(5, 0));
15000 rm.Encode(5, 0));
15004 Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm);
15008 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15016 rm.Encode(5, 0));
15024 rm.Encode(5, 0));
15028 Delegate(kVbsl, &Assembler::vbsl, cond, dt, rd, rn, rm);
15034 DRegister rm,
15049 rd.Encode(22, 12) | rm.Encode(5, 0));
15061 rd.Encode(22, 12) | rm.Encode(5, 0));
15068 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);
15074 QRegister rm,
15089 rd.Encode(22, 12) | rm.Encode(5, 0));
15101 rd.Encode(22, 12) | rm.Encode(5, 0));
15108 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);
15112 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15122 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15131 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15141 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15149 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15154 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);
15158 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15168 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15177 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15187 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15195 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15200 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);
15206 DRegister rm,
15221 rd.Encode(22, 12) | rm.Encode(5, 0));
15233 rd.Encode(22, 12) | rm.Encode(5, 0));
15240 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand);
15246 QRegister rm,
15261 rd.Encode(22, 12) | rm.Encode(5, 0));
15273 rd.Encode(22, 12) | rm.Encode(5, 0));
15280 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand);
15284 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15294 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15303 rm.Encode(5, 0));
15314 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15322 rm.Encode(5, 0));
15327 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm);
15331 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15341 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15350 rm.Encode(5, 0));
15361 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15369 rm.Encode(5, 0));
15374 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rn, rm);
15380 DRegister rm,
15395 rd.Encode(22, 12) | rm.Encode(5, 0));
15407 rd.Encode(22, 12) | rm.Encode(5, 0));
15414 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand);
15420 QRegister rm,
15435 rd.Encode(22, 12) | rm.Encode(5, 0));
15447 rd.Encode(22, 12) | rm.Encode(5, 0));
15454 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand);
15458 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15468 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15477 rm.Encode(5, 0));
15488 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15496 rm.Encode(5, 0));
15501 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm);
15505 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15515 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15524 rm.Encode(5, 0));
15535 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
15543 rm.Encode(5, 0));
15548 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm);
15554 DRegister rm,
15569 rd.Encode(22, 12) | rm.Encode(5, 0));
15581 rd.Encode(22, 12) | rm.Encode(5, 0));
15588 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);
15594 QRegister rm,
15609 rd.Encode(22, 12) | rm.Encode(5, 0));
15621 rd.Encode(22, 12) | rm.Encode(5, 0));
15628 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);
15632 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15642 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15651 rm.Encode(7, 16));
15662 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15670 rm.Encode(7, 16));
15675 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);
15679 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15689 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15698 rm.Encode(7, 16));
15709 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15717 rm.Encode(7, 16));
15722 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rn, rm);
15725 void Assembler::vcls(Condition cond, DataType dt, DRegister rd, DRegister rm) {
15734 rd.Encode(22, 12) | rm.Encode(5, 0));
15744 rd.Encode(22, 12) | rm.Encode(5, 0));
15749 Delegate(kVcls, &Assembler::vcls, cond, dt, rd, rm);
15752 void Assembler::vcls(Condition cond, DataType dt, QRegister rd, QRegister rm) {
15761 rd.Encode(22, 12) | rm.Encode(5, 0));
15771 rd.Encode(22, 12) | rm.Encode(5, 0));
15776 Delegate(kVcls, &Assembler::vcls, cond, dt, rd, rm);
15782 DRegister rm,
15797 rd.Encode(22, 12) | rm.Encode(5, 0));
15809 rd.Encode(22, 12) | rm.Encode(5, 0));
15816 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rm, operand);
15822 QRegister rm,
15837 rd.Encode(22, 12) | rm.Encode(5, 0));
15849 rd.Encode(22, 12) | rm.Encode(5, 0));
15856 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rm, operand);
15860 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
15870 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15879 rm.Encode(7, 16));
15890 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15898 rm.Encode(7, 16));
15903 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm);
15907 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
15917 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15926 rm.Encode(7, 16));
15937 rd.Encode(22, 12) | rn.Encode(5, 0) | rm.Encode(7, 16));
15945 rm.Encode(7, 16));
15950 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm);
15953 void Assembler::vclz(Condition cond, DataType dt, DRegister rd, DRegister rm) {
15962 rd.Encode(22, 12) | rm.Encode(5, 0));
15972 rd.Encode(22, 12) | rm.Encode(5, 0));
15977 Delegate(kVclz, &Assembler::vclz, cond, dt, rd, rm);
15980 void Assembler::vclz(Condition cond, DataType dt, QRegister rd, QRegister rm) {
15989 rd.Encode(22, 12) | rm.Encode(5, 0));
15999 rd.Encode(22, 12) | rm.Encode(5, 0));
16004 Delegate(kVclz, &Assembler::vclz, cond, dt, rd, rm);
16014 SRegister rm = operand.GetRegister();
16018 EmitT32_32(0xeeb40a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
16026 rm.Encode(5, 0));
16057 DRegister rm = operand.GetRegister();
16061 EmitT32_32(0xeeb40b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
16069 rm.Encode(5, 0));
16100 SRegister rm = operand.GetRegister();
16104 EmitT32_32(0xeeb40ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16112 rm.Encode(5, 0));
16143 DRegister rm = operand.GetRegister();
16147 EmitT32_32(0xeeb40bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16155 rm.Encode(5, 0));
16179 void Assembler::vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm) {
16186 EmitT32_32(0xffb00500U | rd.Encode(22, 12) | rm.Encode(5, 0));
16195 EmitA32(0xf3b00500U | rd.Encode(22, 12) | rm.Encode(5, 0));
16200 Delegate(kVcnt, &Assembler::vcnt, cond, dt, rd, rm);
16203 void Assembler::vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm) {
16210 EmitT32_32(0xffb00540U | rd.Encode(22, 12) | rm.Encode(5, 0));
16219 EmitA32(0xf3b00540U | rd.Encode(22, 12) | rm.Encode(5, 0));
16224 Delegate(kVcnt, &Assembler::vcnt, cond, dt, rd, rm);
16228 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
16235 EmitT32_32(0xeeb70ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16242 rd.Encode(22, 12) | rm.Encode(5, 0));
16250 rm.Encode(5, 0));
16257 rm.Encode(5, 0));
16261 Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16265 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
16271 EmitT32_32(0xeeb70bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16277 EmitT32_32(0xeebc0bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16283 EmitT32_32(0xeebd0bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16291 rm.Encode(5, 0));
16297 rm.Encode(5, 0));
16303 rm.Encode(5, 0));
16307 Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16314 DRegister rm,
16328 rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));
16334 if (dt1.Is(F64) && encoded_dt_2.IsValid() && rd.Is(rm) &&
16350 if (encoded_dt_3.IsValid() && dt2.Is(F64) && rd.Is(rm) &&
16372 rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));
16377 if (dt1.Is(F64) && encoded_dt_2.IsValid() && rd.Is(rm) &&
16394 if (encoded_dt_3.IsValid() && dt2.Is(F64) && rd.Is(rm) &&
16411 Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);
16418 QRegister rm,
16430 rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));
16442 rd.Encode(22, 12) | rm.Encode(5, 0) | (fbits_ << 16));
16447 Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);
16454 SRegister rm,
16462 if (dt1.Is(F32) && encoded_dt.IsValid() && rd.Is(rm) &&
16478 if (encoded_dt_2.IsValid() && dt2.Is(F32) && rd.Is(rm) &&
16495 if (dt1.Is(F32) && encoded_dt.IsValid() && rd.Is(rm) &&
16512 if (encoded_dt_2.IsValid() && dt2.Is(F32) && rd.Is(rm) &&
16529 Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm, fbits);
16533 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
16542 rd.Encode(22, 12) | rm.Encode(5, 0));
16552 rd.Encode(22, 12) | rm.Encode(5, 0));
16557 Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16561 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
16570 rd.Encode(22, 12) | rm.Encode(5, 0));
16580 rd.Encode(22, 12) | rm.Encode(5, 0));
16585 Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16589 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm) {
16596 EmitT32_32(0xffb60600U | rd.Encode(22, 12) | rm.Encode(5, 0));
16605 EmitA32(0xf3b60600U | rd.Encode(22, 12) | rm.Encode(5, 0));
16610 Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16614 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm) {
16621 EmitT32_32(0xffb60700U | rd.Encode(22, 12) | rm.Encode(5, 0));
16630 EmitA32(0xf3b60700U | rd.Encode(22, 12) | rm.Encode(5, 0));
16635 Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16639 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
16646 EmitT32_32(0xeebc0ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16652 EmitT32_32(0xeebd0ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
16659 rd.Encode(22, 12) | rm.Encode(5, 0));
16667 rm.Encode(5, 0));
16673 rm.Encode(5, 0));
16680 rm.Encode(5, 0));
16684 Delegate(kVcvt, &Assembler::vcvt, cond, dt1, dt2, rd, rm);
16687 void Assembler::vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
16695 rd.Encode(22, 12) | rm.Encode(5, 0));
16703 rd.Encode(22, 12) | rm.Encode(5, 0));
16707 Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);
16710 void Assembler::vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
16718 rd.Encode(22, 12) | rm.Encode(5, 0));
16726 rd.Encode(22, 12) | rm.Encode(5, 0));
16730 Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);
16733 void Assembler::vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
16741 rd.Encode(22, 12) | rm.Encode(5, 0));
16749 rd.Encode(22, 12) | rm.Encode(5, 0));
16753 Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);
16756 void Assembler::vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
16764 rd.Encode(22, 12) | rm.Encode(5, 0));
16772 rd.Encode(22, 12) | rm.Encode(5, 0));
16776 Delegate(kVcvta, &Assembler::vcvta, dt1, dt2, rd, rm);
16780 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
16786 EmitT32_32(0xeeb20a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
16792 EmitT32_32(0xeeb30a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
16800 rm.Encode(5, 0));
16806 rm.Encode(5, 0));
16810 Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);
16814 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
16820 EmitT32_32(0xeeb20b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
16828 rm.Encode(5, 0));
16832 Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);
16836 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
16842 EmitT32_32(0xeeb30b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
16850 rm.Encode(5, 0));
16854 Delegate(kVcvtb, &Assembler::vcvtb, cond, dt1, dt2, rd, rm);
16857 void Assembler::vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
16865 rd.Encode(22, 12) | rm.Encode(5, 0));
16873 rd.Encode(22, 12) | rm.Encode(5, 0));
16877 Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);
16880 void Assembler::vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
16888 rd.Encode(22, 12) | rm.Encode(5, 0));
16896 rd.Encode(22, 12) | rm.Encode(5, 0));
16900 Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);
16903 void Assembler::vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
16911 rd.Encode(22, 12) | rm.Encode(5, 0));
16919 rd.Encode(22, 12) | rm.Encode(5, 0));
16923 Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);
16926 void Assembler::vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
16934 rd.Encode(22, 12) | rm.Encode(5, 0));
16942 rd.Encode(22, 12) | rm.Encode(5, 0));
16946 Delegate(kVcvtm, &Assembler::vcvtm, dt1, dt2, rd, rm);
16949 void Assembler::vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
16957 rd.Encode(22, 12) | rm.Encode(5, 0));
16965 rd.Encode(22, 12) | rm.Encode(5, 0));
16969 Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);
16972 void Assembler::vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
16980 rd.Encode(22, 12) | rm.Encode(5, 0));
16988 rd.Encode(22, 12) | rm.Encode(5, 0));
16992 Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);
16995 void Assembler::vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
17003 rd.Encode(22, 12) | rm.Encode(5, 0));
17011 rd.Encode(22, 12) | rm.Encode(5, 0));
17015 Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);
17018 void Assembler::vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
17026 rd.Encode(22, 12) | rm.Encode(5, 0));
17034 rd.Encode(22, 12) | rm.Encode(5, 0));
17038 Delegate(kVcvtn, &Assembler::vcvtn, dt1, dt2, rd, rm);
17041 void Assembler::vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) {
17049 rd.Encode(22, 12) | rm.Encode(5, 0));
17057 rd.Encode(22, 12) | rm.Encode(5, 0));
17061 Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);
17064 void Assembler::vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) {
17072 rd.Encode(22, 12) | rm.Encode(5, 0));
17080 rd.Encode(22, 12) | rm.Encode(5, 0));
17084 Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);
17087 void Assembler::vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
17095 rd.Encode(22, 12) | rm.Encode(5, 0));
17103 rd.Encode(22, 12) | rm.Encode(5, 0));
17107 Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);
17110 void Assembler::vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
17118 rd.Encode(22, 12) | rm.Encode(5, 0));
17126 rd.Encode(22, 12) | rm.Encode(5, 0));
17130 Delegate(kVcvtp, &Assembler::vcvtp, dt1, dt2, rd, rm);
17134 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
17140 EmitT32_32(0xeebc0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
17146 EmitT32_32(0xeebd0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
17154 rm.Encode(5, 0));
17160 rm.Encode(5, 0));
17164 Delegate(kVcvtr, &Assembler::vcvtr, cond, dt1, dt2, rd, rm);
17168 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
17174 EmitT32_32(0xeebc0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
17180 EmitT32_32(0xeebd0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
17188 rm.Encode(5, 0));
17194 rm.Encode(5, 0));
17198 Delegate(kVcvtr, &Assembler::vcvtr, cond, dt1, dt2, rd, rm);
17202 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) {
17208 EmitT32_32(0xeeb20ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
17214 EmitT32_32(0xeeb30ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
17222 rm.Encode(5, 0));
17228 rm.Encode(5, 0));
17232 Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);
17236 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) {
17242 EmitT32_32(0xeeb20bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
17250 rm.Encode(5, 0));
17254 Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);
17258 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) {
17264 EmitT32_32(0xeeb30bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
17272 rm.Encode(5, 0));
17276 Delegate(kVcvtt, &Assembler::vcvtt, cond, dt1, dt2, rd, rm);
17280 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17287 rm.Encode(5, 0));
17295 rn.Encode(7, 16) | rm.Encode(5, 0));
17299 Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm);
17303 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17310 rm.Encode(5, 0));
17318 rn.Encode(7, 16) | rm.Encode(5, 0));
17322 Delegate(kVdiv, &Assembler::vdiv, cond, dt, rd, rn, rm);
17390 DRegisterLane rm) {
17393 Dt_imm4_1 encoded_dt(dt, rm);
17399 rd.Encode(22, 12) | rm.Encode(5, 0));
17409 rd.Encode(22, 12) | rm.Encode(5, 0));
17414 Delegate(kVdup, &Assembler::vdup, cond, dt, rd, rm);
17420 DRegisterLane rm) {
17423 Dt_imm4_1 encoded_dt(dt, rm);
17429 rd.Encode(22, 12) | rm.Encode(5, 0));
17439 rd.Encode(22, 12) | rm.Encode(5, 0));
17444 Delegate(kVdup, &Assembler::vdup, cond, dt, rd, rm);
17448 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17456 rm.Encode(5, 0));
17464 rm.Encode(5, 0));
17468 Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm);
17472 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17480 rm.Encode(5, 0));
17488 rm.Encode(5, 0));
17492 Delegate(kVeor, &Assembler::veor, cond, dt, rd, rn, rm);
17499 DRegister rm,
17511 rm.Encode(5, 0) | (imm << 8));
17522 rm.Encode(5, 0) | (imm4 << 8));
17532 rm.Encode(5, 0) | (imm << 8));
17542 rm.Encode(5, 0) | (imm4 << 8));
17549 Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);
17556 QRegister rm,
17568 rm.Encode(5, 0) | (imm << 8));
17579 rm.Encode(5, 0) | (imm4 << 8));
17589 rm.Encode(5, 0) | (imm << 8));
17599 rm.Encode(5, 0) | (imm4 << 8));
17606 Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);
17610 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17618 rm.Encode(5, 0));
17626 rm.Encode(5, 0));
17635 rm.Encode(5, 0));
17642 rn.Encode(7, 16) | rm.Encode(5, 0));
17646 Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);
17650 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17658 rm.Encode(5, 0));
17668 rm.Encode(5, 0));
17673 Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);
17677 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17684 rm.Encode(5, 0));
17692 rn.Encode(7, 16) | rm.Encode(5, 0));
17696 Delegate(kVfma, &Assembler::vfma, cond, dt, rd, rn, rm);
17700 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17708 rm.Encode(5, 0));
17716 rm.Encode(5, 0));
17725 rm.Encode(5, 0));
17732 rn.Encode(7, 16) | rm.Encode(5, 0));
17736 Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);
17740 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17748 rm.Encode(5, 0));
17758 rm.Encode(5, 0));
17763 Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);
17767 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17774 rm.Encode(5, 0));
17782 rn.Encode(7, 16) | rm.Encode(5, 0));
17786 Delegate(kVfms, &Assembler::vfms, cond, dt, rd, rn, rm);
17790 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17797 rm.Encode(5, 0));
17805 rn.Encode(7, 16) | rm.Encode(5, 0));
17809 Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm);
17813 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17820 rm.Encode(5, 0));
17828 rn.Encode(7, 16) | rm.Encode(5, 0));
17832 Delegate(kVfnma, &Assembler::vfnma, cond, dt, rd, rn, rm);
17836 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
17843 rm.Encode(5, 0));
17851 rn.Encode(7, 16) | rm.Encode(5, 0));
17855 Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm);
17859 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17866 rm.Encode(5, 0));
17874 rn.Encode(7, 16) | rm.Encode(5, 0));
17878 Delegate(kVfnms, &Assembler::vfnms, cond, dt, rd, rn, rm);
17882 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17892 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17903 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17908 Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm);
17912 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17922 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17933 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17938 Delegate(kVhadd, &Assembler::vhadd, cond, dt, rd, rn, rm);
17942 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
17952 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17963 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17968 Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm);
17972 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
17982 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17993 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
17998 Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm);
18260 Register rm = operand.GetOffsetRegister();
18270 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18293 (rn.GetCode() << 16) | rm.GetCode());
18301 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18308 (rn.GetCode() << 16) | rm.GetCode());
18315 (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&
18322 rm.GetCode());
18331 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18354 (rn.GetCode() << 16) | rm.GetCode());
18361 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18368 (rn.GetCode() << 16) | rm.GetCode());
18374 (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&
18380 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
18639 Register rm = operand.GetOffsetRegister();
18650 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18666 (rn.GetCode() << 16) | rm.GetCode());
18675 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18682 (rn.GetCode() << 16) | rm.GetCode());
18691 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18697 rm.GetCode());
18708 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18724 (rn.GetCode() << 16) | rm.GetCode());
18732 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18739 (rn.GetCode() << 16) | rm.GetCode());
18747 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18752 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
18845 Register rm = operand.GetOffsetRegister();
18853 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18860 (rn.GetCode() << 16) | rm.GetCode());
18870 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18877 (rn.GetCode() << 16) | rm.GetCode());
19015 Register rm = operand.GetOffsetRegister();
19030 (rn.GetCode() << 16) | rm.GetCode());
19046 rm.GetCode());
19063 (rn.GetCode() << 16) | rm.GetCode());
19077 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
19297 Register rm = operand.GetOffsetRegister();
19308 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19315 (rn.GetCode() << 16) | rm.GetCode());
19324 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19331 (rn.GetCode() << 16) | rm.GetCode());
19340 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19346 rm.GetCode());
19356 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19363 (rn.GetCode() << 16) | rm.GetCode());
19371 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19378 (rn.GetCode() << 16) | rm.GetCode());
19386 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
19391 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
19916 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
19925 rm.Encode(5, 0));
19935 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
19945 rm.Encode(5, 0));
19954 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
19959 Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm);
19963 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
19972 rm.Encode(5, 0));
19982 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
19992 rm.Encode(5, 0));
20001 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20006 Delegate(kVmax, &Assembler::vmax, cond, dt, rd, rn, rm);
20009 void Assembler::vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20016 rm.Encode(5, 0));
20023 rm.Encode(5, 0));
20031 rm.Encode(5, 0));
20037 rm.Encode(5, 0));
20041 Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);
20044 void Assembler::vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20051 rm.Encode(5, 0));
20059 rm.Encode(5, 0));
20063 Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);
20066 void Assembler::vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20073 rm.Encode(5, 0));
20081 rm.Encode(5, 0));
20085 Delegate(kVmaxnm, &Assembler::vmaxnm, dt, rd, rn, rm);
20089 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20098 rm.Encode(5, 0));
20108 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20118 rm.Encode(5, 0));
20127 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20132 Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm);
20136 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20145 rm.Encode(5, 0));
20155 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20165 rm.Encode(5, 0));
20174 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20179 Delegate(kVmin, &Assembler::vmin, cond, dt, rd, rn, rm);
20182 void Assembler::vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20189 rm.Encode(5, 0));
20196 rm.Encode(5, 0));
20204 rm.Encode(5, 0));
20210 rm.Encode(5, 0));
20214 Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);
20217 void Assembler::vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20224 rm.Encode(5, 0));
20232 rm.Encode(5, 0));
20236 Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);
20239 void Assembler::vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20246 rm.Encode(5, 0));
20254 rm.Encode(5, 0));
20258 Delegate(kVminnm, &Assembler::vminnm, dt, rd, rn, rm);
20262 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
20269 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20270 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20271 (rm.GetLane() <= 1)))) {
20275 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20283 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20284 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20285 (rm.GetLane() <= 1)))) {
20289 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20294 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20298 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
20305 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20306 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20307 (rm.GetLane() <= 1)))) {
20311 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20319 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20320 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20321 (rm.GetLane() <= 1)))) {
20325 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20330 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20334 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20343 rm.Encode(5, 0));
20351 rm.Encode(5, 0));
20359 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20369 rm.Encode(5, 0));
20376 rn.Encode(7, 16) | rm.Encode(5, 0));
20383 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20388 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20392 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20401 rm.Encode(5, 0));
20410 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20420 rm.Encode(5, 0));
20428 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20433 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20437 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20444 rm.Encode(5, 0));
20452 rn.Encode(7, 16) | rm.Encode(5, 0));
20456 Delegate(kVmla, &Assembler::vmla, cond, dt, rd, rn, rm);
20460 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
20467 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20468 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20469 (rm.GetLane() <= 1)))) {
20473 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20481 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20482 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20483 (rm.GetLane() <= 1)))) {
20487 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20492 Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm);
20496 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
20506 rn.Encode(7, 16) | rm.Encode(5, 0));
20517 rn.Encode(7, 16) | rm.Encode(5, 0));
20522 Delegate(kVmlal, &Assembler::vmlal, cond, dt, rd, rn, rm);
20526 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
20533 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20534 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20535 (rm.GetLane() <= 1)))) {
20539 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20547 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20548 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20549 (rm.GetLane() <= 1)))) {
20553 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20558 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20562 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
20569 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20570 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20571 (rm.GetLane() <= 1)))) {
20575 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20583 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20584 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20585 (rm.GetLane() <= 1)))) {
20589 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20594 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20598 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
20607 rm.Encode(5, 0));
20615 rm.Encode(5, 0));
20623 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20633 rm.Encode(5, 0));
20640 rn.Encode(7, 16) | rm.Encode(5, 0));
20647 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20652 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20656 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
20665 rm.Encode(5, 0));
20674 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20684 rm.Encode(5, 0));
20692 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
20697 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20701 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
20708 rm.Encode(5, 0));
20716 rn.Encode(7, 16) | rm.Encode(5, 0));
20720 Delegate(kVmls, &Assembler::vmls, cond, dt, rd, rn, rm);
20724 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
20731 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20732 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20733 (rm.GetLane() <= 1)))) {
20737 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20745 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
20746 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
20747 (rm.GetLane() <= 1)))) {
20751 rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
20756 Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm);
20760 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
20770 rn.Encode(7, 16) | rm.Encode(5, 0));
20781 rn.Encode(7, 16) | rm.Encode(5, 0));
20786 Delegate(kVmlsl, &Assembler::vmlsl, cond, dt, rd, rn, rm);
20831 void Assembler::vmov(Condition cond, Register rt, Register rt2, DRegister rm) {
20838 rm.Encode(5, 0));
20847 (rt2.GetCode() << 16) | rm.Encode(5, 0));
20851 Delegate(kVmov, &Assembler::vmov, cond, rt, rt2, rm);
20854 void Assembler::vmov(Condition cond, DRegister rm, Register rt, Register rt2) {
20860 EmitT32_32(0xec400b10U | rm.Encode(5, 0) | (rt.GetCode() << 12) |
20869 EmitA32(0x0c400b10U | (cond.GetCondition() << 28) | rm.Encode(5, 0) |
20874 Delegate(kVmov, &Assembler::vmov, cond, rm, rt, rt2);
20878 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1) {
20883 if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&
20886 rm.Encode(5, 0));
20892 if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&
20896 (rt2.GetCode() << 16) | rm.Encode(5, 0));
20900 Delegate(kVmov, &Assembler::vmov, cond, rt, rt2, rm, rm1);
20904 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2) {
20909 if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&
20911 EmitT32_32(0xec400a10U | rm.Encode(5, 0) | (rt.GetCode() << 12) |
20918 if ((((rm.GetCode() + 1) % kNumberOfSRegisters) == rm1.GetCode()) &&
20921 EmitA32(0x0c400a10U | (cond.GetCondition() << 28) | rm.Encode(5, 0) |
20926 Delegate(kVmov, &Assembler::vmov, cond, rm, rm1, rt, rt2);
21017 DRegister rm = operand.GetRegister();
21021 EmitT32_32(0xeeb00b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
21028 EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
21029 rm.Encode(5, 0));
21038 rm.Encode(5, 0));
21044 EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
21045 rm.Encode(5, 0));
21091 QRegister rm = operand.GetRegister();
21096 EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
21097 rm.Encode(5, 0));
21106 EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
21107 rm.Encode(5, 0));
21144 SRegister rm = operand.GetRegister();
21148 EmitT32_32(0xeeb00a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
21156 rm.Encode(5, 0));
21196 void Assembler::vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm) {
21206 rd.Encode(22, 12) | rm.Encode(5, 0));
21217 rd.Encode(22, 12) | rm.Encode(5, 0));
21222 Delegate(kVmovl, &Assembler::vmovl, cond, dt, rd, rm);
21225 void Assembler::vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) {
21234 rd.Encode(22, 12) | rm.Encode(5, 0));
21244 rd.Encode(22, 12) | rm.Encode(5, 0));
21249 Delegate(kVmovn, &Assembler::vmovn, cond, dt, rd, rm);
21396 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21405 rm.Encode(5, 0));
21413 rm.Encode(5, 0));
21422 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21432 rm.Encode(5, 0));
21439 rn.Encode(7, 16) | rm.Encode(5, 0));
21447 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21452 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);
21456 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
21465 rm.Encode(5, 0));
21475 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21485 rm.Encode(5, 0));
21494 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21499 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);
21503 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21510 rm.Encode(5, 0));
21518 rn.Encode(7, 16) | rm.Encode(5, 0));
21522 Delegate(kVmul, &Assembler::vmul, cond, dt, rd, rn, rm);
21578 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
21589 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21601 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
21606 Delegate(kVmull, &Assembler::vmull, cond, dt, rd, rn, rm);
21644 DRegister rm = operand.GetRegister();
21649 EmitT32_32(0xffb00580U | rd.Encode(22, 12) | rm.Encode(5, 0));
21656 EmitA32(0xf3b00580U | rd.Encode(22, 12) | rm.Encode(5, 0));
21699 QRegister rm = operand.GetRegister();
21704 EmitT32_32(0xffb005c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
21711 EmitA32(0xf3b005c0U | rd.Encode(22, 12) | rm.Encode(5, 0));
21719 void Assembler::vneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {
21729 rd.Encode(22, 12) | rm.Encode(5, 0));
21736 EmitT32_32(0xeeb10b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
21746 rd.Encode(22, 12) | rm.Encode(5, 0));
21753 rm.Encode(5, 0));
21757 Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);
21760 void Assembler::vneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {
21770 rd.Encode(22, 12) | rm.Encode(5, 0));
21781 rd.Encode(22, 12) | rm.Encode(5, 0));
21786 Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);
21789 void Assembler::vneg(Condition cond, DataType dt, SRegister rd, SRegister rm) {
21795 EmitT32_32(0xeeb10a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
21803 rm.Encode(5, 0));
21807 Delegate(kVneg, &Assembler::vneg, cond, dt, rd, rm);
21811 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21818 rm.Encode(5, 0));
21826 rn.Encode(7, 16) | rm.Encode(5, 0));
21830 Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm);
21834 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21841 rm.Encode(5, 0));
21849 rn.Encode(7, 16) | rm.Encode(5, 0));
21853 Delegate(kVnmla, &Assembler::vnmla, cond, dt, rd, rn, rm);
21857 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21864 rm.Encode(5, 0));
21872 rn.Encode(7, 16) | rm.Encode(5, 0));
21876 Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm);
21880 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21887 rm.Encode(5, 0));
21895 rn.Encode(7, 16) | rm.Encode(5, 0));
21899 Delegate(kVnmls, &Assembler::vnmls, cond, dt, rd, rn, rm);
21903 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
21910 rm.Encode(5, 0));
21918 rn.Encode(7, 16) | rm.Encode(5, 0));
21922 Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm);
21926 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
21933 rm.Encode(5, 0));
21941 rn.Encode(7, 16) | rm.Encode(5, 0));
21945 Delegate(kVnmul, &Assembler::vnmul, cond, dt, rd, rn, rm);
21984 DRegister rm = operand.GetRegister();
21990 rm.Encode(5, 0));
21998 rm.Encode(5, 0));
22042 QRegister rm = operand.GetRegister();
22048 rm.Encode(5, 0));
22056 rm.Encode(5, 0));
22072 DRegister rm = operand.GetRegister();
22078 rm.Encode(5, 0));
22086 rm.Encode(5, 0));
22130 QRegister rm = operand.GetRegister();
22136 rm.Encode(5, 0));
22144 rm.Encode(5, 0));
22183 DRegister rm) {
22193 rd.Encode(22, 12) | rm.Encode(5, 0));
22204 rd.Encode(22, 12) | rm.Encode(5, 0));
22209 Delegate(kVpadal, &Assembler::vpadal, cond, dt, rd, rm);
22215 QRegister rm) {
22225 rd.Encode(22, 12) | rm.Encode(5, 0));
22236 rd.Encode(22, 12) | rm.Encode(5, 0));
22241 Delegate(kVpadal, &Assembler::vpadal, cond, dt, rd, rm);
22245 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22254 rm.Encode(5, 0));
22263 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22273 rm.Encode(5, 0));
22281 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22286 Delegate(kVpadd, &Assembler::vpadd, cond, dt, rd, rn, rm);
22292 DRegister rm) {
22302 rd.Encode(22, 12) | rm.Encode(5, 0));
22313 rd.Encode(22, 12) | rm.Encode(5, 0));
22318 Delegate(kVpaddl, &Assembler::vpaddl, cond, dt, rd, rm);
22324 QRegister rm) {
22334 rd.Encode(22, 12) | rm.Encode(5, 0));
22345 rd.Encode(22, 12) | rm.Encode(5, 0));
22350 Delegate(kVpaddl, &Assembler::vpaddl, cond, dt, rd, rm);
22354 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22363 rm.Encode(5, 0));
22373 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22383 rm.Encode(5, 0));
22392 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22397 Delegate(kVpmax, &Assembler::vpmax, cond, dt, rd, rn, rm);
22401 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22410 rm.Encode(5, 0));
22420 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22430 rm.Encode(5, 0));
22439 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22444 Delegate(kVpmin, &Assembler::vpmin, cond, dt, rd, rn, rm);
22549 void Assembler::vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm) {
22558 rd.Encode(22, 12) | rm.Encode(5, 0));
22568 rd.Encode(22, 12) | rm.Encode(5, 0));
22573 Delegate(kVqabs, &Assembler::vqabs, cond, dt, rd, rm);
22576 void Assembler::vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm) {
22585 rd.Encode(22, 12) | rm.Encode(5, 0));
22595 rd.Encode(22, 12) | rm.Encode(5, 0));
22600 Delegate(kVqabs, &Assembler::vqabs, cond, dt, rd, rm);
22604 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22614 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22625 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22630 Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm);
22634 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
22644 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22655 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22660 Delegate(kVqadd, &Assembler::vqadd, cond, dt, rd, rn, rm);
22664 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
22673 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22683 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22688 Delegate(kVqdmlal, &Assembler::vqdmlal, cond, dt, rd, rn, rm);
22742 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
22751 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22761 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22766 Delegate(kVqdmlsl, &Assembler::vqdmlsl, cond, dt, rd, rn, rm);
22820 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
22829 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22839 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22844 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22848 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
22857 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22867 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22872 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22876 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
22883 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
22884 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
22885 (rm.GetLane() <= 1))) &&
22889 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22897 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
22898 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
22899 (rm.GetLane() <= 1))) &&
22903 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22908 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22912 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
22919 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
22920 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
22921 (rm.GetLane() <= 1))) &&
22925 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22933 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
22934 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
22935 (rm.GetLane() <= 1))) &&
22939 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22944 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm);
22948 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
22957 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22967 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
22972 Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);
22976 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) {
22983 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
22984 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
22985 (rm.GetLane() <= 1))) &&
22989 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
22997 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
22998 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
22999 (rm.GetLane() <= 1))) &&
23003 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23008 Delegate(kVqdmull, &Assembler::vqdmull, cond, dt, rd, rn, rm);
23014 QRegister rm) {
23024 rd.Encode(22, 12) | rm.Encode(5, 0));
23035 rd.Encode(22, 12) | rm.Encode(5, 0));
23040 Delegate(kVqmovn, &Assembler::vqmovn, cond, dt, rd, rm);
23046 QRegister rm) {
23055 rd.Encode(22, 12) | rm.Encode(5, 0));
23065 rd.Encode(22, 12) | rm.Encode(5, 0));
23070 Delegate(kVqmovun, &Assembler::vqmovun, cond, dt, rd, rm);
23073 void Assembler::vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm) {
23082 rd.Encode(22, 12) | rm.Encode(5, 0));
23092 rd.Encode(22, 12) | rm.Encode(5, 0));
23097 Delegate(kVqneg, &Assembler::vqneg, cond, dt, rd, rm);
23100 void Assembler::vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm) {
23109 rd.Encode(22, 12) | rm.Encode(5, 0));
23119 rd.Encode(22, 12) | rm.Encode(5, 0));
23124 Delegate(kVqneg, &Assembler::vqneg, cond, dt, rd, rm);
23128 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
23137 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23147 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23152 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23156 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
23165 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23175 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23180 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23184 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) {
23191 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
23192 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
23193 (rm.GetLane() <= 1))) &&
23197 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23205 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
23206 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
23207 (rm.GetLane() <= 1))) &&
23211 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23216 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23220 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) {
23227 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
23228 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
23229 (rm.GetLane() <= 1))) &&
23233 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23241 (((dt.GetSize() == 16) && (rm.GetCode() <= 7) && (rm.GetLane() <= 3)) ||
23242 ((dt.GetSize() == 32) && (rm.GetCode() <= 15) &&
23243 (rm.GetLane() <= 1))) &&
23247 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.EncodeX(dt, 5, 0));
23252 Delegate(kVqrdmulh, &Assembler::vqrdmulh, cond, dt, rd, rn, rm);
23256 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
23266 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23277 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23282 Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn);
23286 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
23296 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23307 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23312 Delegate(kVqrshl, &Assembler::vqrshl, cond, dt, rd, rm, rn);
23318 QRegister rm,
23334 rd.Encode(22, 12) | rm.Encode(5, 0));
23346 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23358 rd.Encode(22, 12) | rm.Encode(5, 0));
23368 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23375 Delegate(kVqrshrn, &Assembler::vqrshrn, cond, dt, rd, rm, operand);
23381 QRegister rm,
23397 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23406 rd.Encode(22, 12) | rm.Encode(5, 0));
23418 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23426 rd.Encode(22, 12) | rm.Encode(5, 0));
23433 Delegate(kVqrshrun, &Assembler::vqrshrun, cond, dt, rd, rm, operand);
23439 DRegister rm,
23453 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23464 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23482 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23495 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23502 Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand);
23508 QRegister rm,
23522 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23533 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
23551 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23564 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23571 Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand);
23577 DRegister rm,
23593 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23606 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23613 Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);
23619 QRegister rm,
23635 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23648 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23655 Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);
23661 QRegister rm,
23677 rd.Encode(22, 12) | rm.Encode(5, 0));
23689 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23701 rd.Encode(22, 12) | rm.Encode(5, 0));
23711 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23718 Delegate(kVqshrn, &Assembler::vqshrn, cond, dt, rd, rm, operand);
23724 QRegister rm,
23740 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23749 rd.Encode(22, 12) | rm.Encode(5, 0));
23761 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
23769 rd.Encode(22, 12) | rm.Encode(5, 0));
23776 Delegate(kVqshrun, &Assembler::vqshrun, cond, dt, rd, rm, operand);
23780 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
23790 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23801 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23806 Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);
23810 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
23820 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23831 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23836 Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);
23840 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
23849 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23859 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
23864 Delegate(kVraddhn, &Assembler::vraddhn, cond, dt, rd, rn, rm);
23870 DRegister rm) {
23880 rd.Encode(22, 12) | rm.Encode(5, 0));
23891 rd.Encode(22, 12) | rm.Encode(5, 0));
23896 Delegate(kVrecpe, &Assembler::vrecpe, cond, dt, rd, rm);
23902 QRegister rm) {
23912 rd.Encode(22, 12) | rm.Encode(5, 0));
23923 rd.Encode(22, 12) | rm.Encode(5, 0));
23928 Delegate(kVrecpe, &Assembler::vrecpe, cond, dt, rd, rm);
23932 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
23940 rm.Encode(5, 0));
23950 rm.Encode(5, 0));
23955 Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm);
23959 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
23967 rm.Encode(5, 0));
23977 rm.Encode(5, 0));
23982 Delegate(kVrecps, &Assembler::vrecps, cond, dt, rd, rn, rm);
23988 DRegister rm) {
23997 rd.Encode(22, 12) | rm.Encode(5, 0));
24007 rd.Encode(22, 12) | rm.Encode(5, 0));
24012 Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm);
24018 QRegister rm) {
24027 rd.Encode(22, 12) | rm.Encode(5, 0));
24037 rd.Encode(22, 12) | rm.Encode(5, 0));
24042 Delegate(kVrev16, &Assembler::vrev16, cond, dt, rd, rm);
24048 DRegister rm) {
24057 rd.Encode(22, 12) | rm.Encode(5, 0));
24067 rd.Encode(22, 12) | rm.Encode(5, 0));
24072 Delegate(kVrev32, &Assembler::vrev32, cond, dt, rd, rm);
24078 QRegister rm) {
24087 rd.Encode(22, 12) | rm.Encode(5, 0));
24097 rd.Encode(22, 12) | rm.Encode(5, 0));
24102 Delegate(kVrev32, &Assembler::vrev32, cond, dt, rd, rm);
24108 DRegister rm) {
24117 rd.Encode(22, 12) | rm.Encode(5, 0));
24127 rd.Encode(22, 12) | rm.Encode(5, 0));
24132 Delegate(kVrev64, &Assembler::vrev64, cond, dt, rd, rm);
24138 QRegister rm) {
24147 rd.Encode(22, 12) | rm.Encode(5, 0));
24157 rd.Encode(22, 12) | rm.Encode(5, 0));
24162 Delegate(kVrev64, &Assembler::vrev64, cond, dt, rd, rm);
24166 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
24176 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24187 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24192 Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm);
24196 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
24206 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24217 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
24222 Delegate(kVrhadd, &Assembler::vrhadd, cond, dt, rd, rn, rm);
24225 void Assembler::vrinta(DataType dt, DRegister rd, DRegister rm) {
24233 rd.Encode(22, 12) | rm.Encode(5, 0));
24239 EmitT32_32(0xfeb80b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24247 rd.Encode(22, 12) | rm.Encode(5, 0));
24252 EmitA32(0xfeb80b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24256 Delegate(kVrinta, &Assembler::vrinta, dt, rd, rm);
24259 void Assembler::vrinta(DataType dt, QRegister rd, QRegister rm) {
24267 rd.Encode(22, 12) | rm.Encode(5, 0));
24275 rd.Encode(22, 12) | rm.Encode(5, 0));
24279 Delegate(kVrinta, &Assembler::vrinta, dt, rd, rm);
24282 void Assembler::vrinta(DataType dt, SRegister rd, SRegister rm) {
24288 EmitT32_32(0xfeb80a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24295 EmitA32(0xfeb80a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24299 Delegate(kVrinta, &Assembler::vrinta, dt, rd, rm);
24302 void Assembler::vrintm(DataType dt, DRegister rd, DRegister rm) {
24310 rd.Encode(22, 12) | rm.Encode(5, 0));
24316 EmitT32_32(0xfebb0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24324 rd.Encode(22, 12) | rm.Encode(5, 0));
24329 EmitA32(0xfebb0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24333 Delegate(kVrintm, &Assembler::vrintm, dt, rd, rm);
24336 void Assembler::vrintm(DataType dt, QRegister rd, QRegister rm) {
24344 rd.Encode(22, 12) | rm.Encode(5, 0));
24352 rd.Encode(22, 12) | rm.Encode(5, 0));
24356 Delegate(kVrintm, &Assembler::vrintm, dt, rd, rm);
24359 void Assembler::vrintm(DataType dt, SRegister rd, SRegister rm) {
24365 EmitT32_32(0xfebb0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24372 EmitA32(0xfebb0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24376 Delegate(kVrintm, &Assembler::vrintm, dt, rd, rm);
24379 void Assembler::vrintn(DataType dt, DRegister rd, DRegister rm) {
24387 rd.Encode(22, 12) | rm.Encode(5, 0));
24393 EmitT32_32(0xfeb90b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24401 rd.Encode(22, 12) | rm.Encode(5, 0));
24406 EmitA32(0xfeb90b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24410 Delegate(kVrintn, &Assembler::vrintn, dt, rd, rm);
24413 void Assembler::vrintn(DataType dt, QRegister rd, QRegister rm) {
24421 rd.Encode(22, 12) | rm.Encode(5, 0));
24429 rd.Encode(22, 12) | rm.Encode(5, 0));
24433 Delegate(kVrintn, &Assembler::vrintn, dt, rd, rm);
24436 void Assembler::vrintn(DataType dt, SRegister rd, SRegister rm) {
24442 EmitT32_32(0xfeb90a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24449 EmitA32(0xfeb90a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24453 Delegate(kVrintn, &Assembler::vrintn, dt, rd, rm);
24456 void Assembler::vrintp(DataType dt, DRegister rd, DRegister rm) {
24464 rd.Encode(22, 12) | rm.Encode(5, 0));
24470 EmitT32_32(0xfeba0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24478 rd.Encode(22, 12) | rm.Encode(5, 0));
24483 EmitA32(0xfeba0b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24487 Delegate(kVrintp, &Assembler::vrintp, dt, rd, rm);
24490 void Assembler::vrintp(DataType dt, QRegister rd, QRegister rm) {
24498 rd.Encode(22, 12) | rm.Encode(5, 0));
24506 rd.Encode(22, 12) | rm.Encode(5, 0));
24510 Delegate(kVrintp, &Assembler::vrintp, dt, rd, rm);
24513 void Assembler::vrintp(DataType dt, SRegister rd, SRegister rm) {
24519 EmitT32_32(0xfeba0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24526 EmitA32(0xfeba0a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24530 Delegate(kVrintp, &Assembler::vrintp, dt, rd, rm);
24536 SRegister rm) {
24542 EmitT32_32(0xeeb60a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24550 rm.Encode(5, 0));
24554 Delegate(kVrintr, &Assembler::vrintr, cond, dt, rd, rm);
24560 DRegister rm) {
24566 EmitT32_32(0xeeb60b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24574 rm.Encode(5, 0));
24578 Delegate(kVrintr, &Assembler::vrintr, cond, dt, rd, rm);
24584 DRegister rm) {
24592 rd.Encode(22, 12) | rm.Encode(5, 0));
24598 EmitT32_32(0xeeb70b40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24606 rd.Encode(22, 12) | rm.Encode(5, 0));
24612 rm.Encode(5, 0));
24616 Delegate(kVrintx, &Assembler::vrintx, cond, dt, rd, rm);
24619 void Assembler::vrintx(DataType dt, QRegister rd, QRegister rm) {
24627 rd.Encode(22, 12) | rm.Encode(5, 0));
24635 rd.Encode(22, 12) | rm.Encode(5, 0));
24639 Delegate(kVrintx, &Assembler::vrintx, dt, rd, rm);
24645 SRegister rm) {
24651 EmitT32_32(0xeeb70a40U | rd.Encode(22, 12) | rm.Encode(5, 0));
24659 rm.Encode(5, 0));
24663 Delegate(kVrintx, &Assembler::vrintx, cond, dt, rd, rm);
24669 DRegister rm) {
24677 rd.Encode(22, 12) | rm.Encode(5, 0));
24683 EmitT32_32(0xeeb60bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24691 rd.Encode(22, 12) | rm.Encode(5, 0));
24697 rm.Encode(5, 0));
24701 Delegate(kVrintz, &Assembler::vrintz, cond, dt, rd, rm);
24704 void Assembler::vrintz(DataType dt, QRegister rd, QRegister rm) {
24712 rd.Encode(22, 12) | rm.Encode(5, 0));
24720 rd.Encode(22, 12) | rm.Encode(5, 0));
24724 Delegate(kVrintz, &Assembler::vrintz, dt, rd, rm);
24730 SRegister rm) {
24736 EmitT32_32(0xeeb60ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
24744 rm.Encode(5, 0));
24748 Delegate(kVrintz, &Assembler::vrintz, cond, dt, rd, rm);
24752 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) {
24762 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24773 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24778 Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn);
24782 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) {
24792 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24803 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
24808 Delegate(kVrshl, &Assembler::vrshl, cond, dt, rd, rm, rn);
24814 DRegister rm,
24830 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24838 EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
24839 rm.Encode(5, 0));
24852 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24859 EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
24860 rm.Encode(5, 0));
24867 Delegate(kVrshr, &Assembler::vrshr, cond, dt, rd, rm, operand);
24873 QRegister rm,
24889 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24897 EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
24898 rm.Encode(5, 0));
24911 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24918 EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
24919 rm.Encode(5, 0));
24926 Delegate(kVrshr, &Assembler::vrshr, cond, dt, rd, rm, operand);
24932 QRegister rm,
24948 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24957 rd.Encode(22, 12) | rm.Encode(5, 0));
24969 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
24977 rd.Encode(22, 12) | rm.Encode(5, 0));
24984 Delegate(kVrshrn, &Assembler::vrshrn, cond, dt, rd, rm, operand);
24990 DRegister rm) {
25000 rd.Encode(22, 12) | rm.Encode(5, 0));
25011 rd.Encode(22, 12) | rm.Encode(5, 0));
25016 Delegate(kVrsqrte, &Assembler::vrsqrte, cond, dt, rd, rm);
25022 QRegister rm) {
25032 rd.Encode(22, 12) | rm.Encode(5, 0));
25043 rd.Encode(22, 12) | rm.Encode(5, 0));
25048 Delegate(kVrsqrte, &Assembler::vrsqrte, cond, dt, rd, rm);
25052 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25060 rm.Encode(5, 0));
25070 rm.Encode(5, 0));
25075 Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm);
25079 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
25087 rm.Encode(5, 0));
25097 rm.Encode(5, 0));
25102 Delegate(kVrsqrts, &Assembler::vrsqrts, cond, dt, rd, rn, rm);
25108 DRegister rm,
25124 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25137 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25144 Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand);
25150 QRegister rm,
25166 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25179 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25186 Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand);
25190 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
25199 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
25209 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
25214 Delegate(kVrsubhn, &Assembler::vrsubhn, cond, dt, rd, rn, rm);
25217 void Assembler::vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25224 rm.Encode(5, 0));
25232 rm.Encode(5, 0));
25236 Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm);
25239 void Assembler::vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25246 rm.Encode(5, 0));
25254 rm.Encode(5, 0));
25258 Delegate(kVseleq, &Assembler::vseleq, dt, rd, rn, rm);
25261 void Assembler::vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25268 rm.Encode(5, 0));
25276 rm.Encode(5, 0));
25280 Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm);
25283 void Assembler::vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25290 rm.Encode(5, 0));
25298 rm.Encode(5, 0));
25302 Delegate(kVselge, &Assembler::vselge, dt, rd, rn, rm);
25305 void Assembler::vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25312 rm.Encode(5, 0));
25320 rm.Encode(5, 0));
25324 Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm);
25327 void Assembler::vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25334 rm.Encode(5, 0));
25342 rm.Encode(5, 0));
25346 Delegate(kVselgt, &Assembler::vselgt, dt, rd, rn, rm);
25349 void Assembler::vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) {
25356 rm.Encode(5, 0));
25364 rm.Encode(5, 0));
25368 Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm);
25371 void Assembler::vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) {
25378 rm.Encode(5, 0));
25386 rm.Encode(5, 0));
25390 Delegate(kVselvs, &Assembler::vselvs, dt, rd, rn, rm);
25396 DRegister rm,
25412 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25425 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25442 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
25453 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
25459 Delegate(kVshl, &Assembler::vshl, cond, dt, rd, rm, operand);
25465 QRegister rm,
25481 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25494 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25511 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
25522 rd.Encode(22, 12) | rm.Encode(5, 0) | rn.Encode(7, 16));
25528 Delegate(kVshl, &Assembler::vshl, cond, dt, rd, rm, operand);
25534 DRegister rm,
25550 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25559 rd.Encode(22, 12) | rm.Encode(5, 0));
25571 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25579 rd.Encode(22, 12) | rm.Encode(5, 0));
25586 Delegate(kVshll, &Assembler::vshll, cond, dt, rd, rm, operand);
25592 DRegister rm,
25608 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25616 EmitT32_32(0xef200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
25617 rm.Encode(5, 0));
25630 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25637 EmitA32(0xf2200110U | rd.Encode(22, 12) | rm.Encode(7, 16) |
25638 rm.Encode(5, 0));
25645 Delegate(kVshr, &Assembler::vshr, cond, dt, rd, rm, operand);
25651 QRegister rm,
25667 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25675 EmitT32_32(0xef200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
25676 rm.Encode(5, 0));
25689 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25696 EmitA32(0xf2200150U | rd.Encode(22, 12) | rm.Encode(7, 16) |
25697 rm.Encode(5, 0));
25704 Delegate(kVshr, &Assembler::vshr, cond, dt, rd, rm, operand);
25710 QRegister rm,
25726 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25735 rd.Encode(22, 12) | rm.Encode(5, 0));
25747 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25755 rd.Encode(22, 12) | rm.Encode(5, 0));
25762 Delegate(kVshrn, &Assembler::vshrn, cond, dt, rd, rm, operand);
25768 DRegister rm,
25784 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25797 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25804 Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand);
25810 QRegister rm,
25826 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25839 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25846 Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand);
25849 void Assembler::vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm) {
25855 EmitT32_32(0xeeb10ac0U | rd.Encode(22, 12) | rm.Encode(5, 0));
25863 rm.Encode(5, 0));
25867 Delegate(kVsqrt, &Assembler::vsqrt, cond, dt, rd, rm);
25870 void Assembler::vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm) {
25876 EmitT32_32(0xeeb10bc0U | rd.Encode(22, 12) | rm.Encode(5, 0));
25884 rm.Encode(5, 0));
25888 Delegate(kVsqrt, &Assembler::vsqrt, cond, dt, rd, rm);
25894 DRegister rm,
25910 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25923 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25930 Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand);
25936 QRegister rm,
25952 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25965 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
25972 Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand);
25978 DRegister rm,
25994 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
26007 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
26014 Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand);
26020 QRegister rm,
26036 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
26049 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16));
26056 Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand);
26255 Register rm = operand.GetOffsetRegister();
26264 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26287 (rn.GetCode() << 16) | rm.GetCode());
26294 (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&
26301 rm.GetCode());
26310 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26333 (rn.GetCode() << 16) | rm.GetCode());
26339 (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&
26345 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
26537 Register rm = operand.GetOffsetRegister();
26547 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26563 (rn.GetCode() << 16) | rm.GetCode());
26572 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26578 rm.GetCode());
26589 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26605 (rn.GetCode() << 16) | rm.GetCode());
26613 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26618 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
26711 Register rm = operand.GetOffsetRegister();
26719 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26726 (rn.GetCode() << 16) | rm.GetCode());
26736 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
26743 (rn.GetCode() << 16) | rm.GetCode());
26823 Register rm = operand.GetOffsetRegister();
26838 rm.GetCode());
26854 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
27006 Register rm = operand.GetOffsetRegister();
27015 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
27022 (rn.GetCode() << 16) | rm.GetCode());
27031 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
27037 rm.GetCode());
27047 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
27054 (rn.GetCode() << 16) | rm.GetCode());
27062 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
27067 first.Encode(22, 12) | (rn.GetCode() << 16) | rm.GetCode());
27356 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
27365 rm.Encode(5, 0));
27373 rm.Encode(5, 0));
27381 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27391 rm.Encode(5, 0));
27398 rn.Encode(7, 16) | rm.Encode(5, 0));
27405 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27410 Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);
27414 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
27423 rm.Encode(5, 0));
27432 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27442 rm.Encode(5, 0));
27450 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27455 Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);
27459 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) {
27466 rm.Encode(5, 0));
27474 rn.Encode(7, 16) | rm.Encode(5, 0));
27478 Delegate(kVsub, &Assembler::vsub, cond, dt, rd, rn, rm);
27482 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) {
27491 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27501 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27506 Delegate(kVsubhn, &Assembler::vsubhn, cond, dt, rd, rn, rm);
27510 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) {
27520 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27531 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27536 Delegate(kVsubl, &Assembler::vsubl, cond, dt, rd, rn, rm);
27540 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) {
27550 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27561 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27566 Delegate(kVsubw, &Assembler::vsubw, cond, dt, rd, rn, rm);
27569 void Assembler::vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) {
27576 EmitT32_32(0xffb20000U | rd.Encode(22, 12) | rm.Encode(5, 0));
27583 EmitA32(0xf3b20000U | rd.Encode(22, 12) | rm.Encode(5, 0));
27587 Delegate(kVswp, &Assembler::vswp, cond, dt, rd, rm);
27590 void Assembler::vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) {
27597 EmitT32_32(0xffb20040U | rd.Encode(22, 12) | rm.Encode(5, 0));
27604 EmitA32(0xf3b20040U | rd.Encode(22, 12) | rm.Encode(5, 0));
27608 Delegate(kVswp, &Assembler::vswp, cond, dt, rd, rm);
27615 DRegister rm) {
27626 (len_encoding << 8) | rm.Encode(5, 0));
27639 (len_encoding << 8) | rm.Encode(5, 0));
27644 Delegate(kVtbl, &Assembler::vtbl, cond, dt, rd, nreglist, rm);
27651 DRegister rm) {
27662 (len_encoding << 8) | rm.Encode(5, 0));
27675 (len_encoding << 8) | rm.Encode(5, 0));
27680 Delegate(kVtbx, &Assembler::vtbx, cond, dt, rd, nreglist, rm);
27683 void Assembler::vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm) {
27692 rd.Encode(22, 12) | rm.Encode(5, 0));
27702 rd.Encode(22, 12) | rm.Encode(5, 0));
27707 Delegate(kVtrn, &Assembler::vtrn, cond, dt, rd, rm);
27710 void Assembler::vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm) {
27719 rd.Encode(22, 12) | rm.Encode(5, 0));
27729 rd.Encode(22, 12) | rm.Encode(5, 0));
27734 Delegate(kVtrn, &Assembler::vtrn, cond, dt, rd, rm);
27738 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) {
27747 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27757 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27762 Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm);
27766 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) {
27775 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27785 rd.Encode(22, 12) | rn.Encode(7, 16) | rm.Encode(5, 0));
27790 Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm);
27793 void Assembler::vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm) {
27802 rd.Encode(22, 12) | rm.Encode(5, 0));
27810 EmitT32_32(0xffba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));
27820 rd.Encode(22, 12) | rm.Encode(5, 0));
27827 EmitA32(0xf3ba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));
27832 Delegate(kVuzp, &Assembler::vuzp, cond, dt, rd, rm);
27835 void Assembler::vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm) {
27844 rd.Encode(22, 12) | rm.Encode(5, 0));
27854 rd.Encode(22, 12) | rm.Encode(5, 0));
27859 Delegate(kVuzp, &Assembler::vuzp, cond, dt, rd, rm);
27862 void Assembler::vzip(Condition cond, DataType dt, DRegister rd, DRegister rm) {
27871 rd.Encode(22, 12) | rm.Encode(5, 0));
27879 EmitT32_32(0xffba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));
27889 rd.Encode(22, 12) | rm.Encode(5, 0));
27896 EmitA32(0xf3ba0080U | rd.Encode(22, 12) | rm.Encode(5, 0));
27901 Delegate(kVzip, &Assembler::vzip, cond, dt, rd, rm);
27904 void Assembler::vzip(Condition cond, DataType dt, QRegister rd, QRegister rm) {
27913 rd.Encode(22, 12) | rm.Encode(5, 0));
27923 rd.Encode(22, 12) | rm.Encode(5, 0));
27928 Delegate(kVzip, &Assembler::vzip, cond, dt, rd, rm);