Lines Matching refs:operand
1927 const Operand& operand) {
1930 if (operand.IsImmediate()) {
1931 uint32_t imm = operand.GetImmediate();
1955 if (operand.IsImmediateShiftedRegister()) {
1956 Register rm = operand.GetBaseRegister();
1957 if (operand.IsPlainRegister()) {
1968 Shift shift = operand.GetShift();
1969 uint32_t amount = operand.GetShiftAmount();
1976 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
1987 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
1992 if (operand.IsRegisterShiftedRegister()) {
1993 Register rm = operand.GetBaseRegister();
1994 Shift shift = operand.GetShift();
1995 Register rs = operand.GetShiftRegister();
2008 Delegate(kAdc, &Assembler::adc, cond, size, rd, rn, operand);
2015 const Operand& operand) {
2018 if (operand.IsImmediate()) {
2019 uint32_t imm = operand.GetImmediate();
2043 if (operand.IsImmediateShiftedRegister()) {
2044 Register rm = operand.GetBaseRegister();
2045 if (operand.IsPlainRegister()) {
2056 Shift shift = operand.GetShift();
2057 uint32_t amount = operand.GetShiftAmount();
2064 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
2075 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
2080 if (operand.IsRegisterShiftedRegister()) {
2081 Register rm = operand.GetBaseRegister();
2082 Shift shift = operand.GetShift();
2083 Register rs = operand.GetShiftRegister();
2096 Delegate(kAdcs, &Assembler::adcs, cond, size, rd, rn, operand);
2103 const Operand& operand) {
2106 if (operand.IsImmediate()) {
2107 uint32_t imm = operand.GetImmediate();
2216 if (operand.IsImmediateShiftedRegister()) {
2217 Register rm = operand.GetBaseRegister();
2218 if (operand.IsPlainRegister()) {
2255 Shift shift = operand.GetShift();
2256 uint32_t amount = operand.GetShiftAmount();
2263 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
2273 (operand.GetTypeEncodingValue() << 4) |
2284 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
2292 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
2297 if (operand.IsRegisterShiftedRegister()) {
2298 Register rm = operand.GetBaseRegister();
2299 Shift shift = operand.GetShift();
2300 Register rs = operand.GetShiftRegister();
2313 Delegate(kAdd, &Assembler::add, cond, size, rd, rn, operand);
2316 void Assembler::add(Condition cond, Register rd, const Operand& operand) {
2319 if (operand.IsImmediate()) {
2320 uint32_t imm = operand.GetImmediate();
2330 if (operand.IsPlainRegister()) {
2331 Register rm = operand.GetBaseRegister();
2345 Delegate(kAdd, &Assembler::add, cond, rd, operand);
2352 const Operand& operand) {
2355 if (operand.IsImmediate()) {
2356 uint32_t imm = operand.GetImmediate();
2410 if (operand.IsImmediateShiftedRegister()) {
2411 Register rm = operand.GetBaseRegister();
2412 if (operand.IsPlainRegister()) {
2424 Shift shift = operand.GetShift();
2425 uint32_t amount = operand.GetShiftAmount();
2432 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
2442 (operand.GetTypeEncodingValue() << 4) |
2453 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
2461 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
2466 if (operand.IsRegisterShiftedRegister()) {
2467 Register rm = operand.GetBaseRegister();
2468 Shift shift = operand.GetShift();
2469 Register rs = operand.GetShiftRegister();
2482 Delegate(kAdds, &Assembler::adds, cond, size, rd, rn, operand);
2485 void Assembler::adds(Register rd, const Operand& operand) {
2488 if (operand.IsImmediate()) {
2489 uint32_t imm = operand.GetImmediate();
2499 Delegate(kAdds, &Assembler::adds, rd, operand);
2505 const Operand& operand) {
2508 if (operand.IsImmediate()) {
2509 uint32_t imm = operand.GetImmediate();
2535 Delegate(kAddw, &Assembler::addw, cond, rd, rn, operand);
2701 const Operand& operand) {
2704 if (operand.IsImmediate()) {
2705 uint32_t imm = operand.GetImmediate();
2729 if (operand.IsImmediateShiftedRegister()) {
2730 Register rm = operand.GetBaseRegister();
2731 if (operand.IsPlainRegister()) {
2742 Shift shift = operand.GetShift();
2743 uint32_t amount = operand.GetShiftAmount();
2750 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
2761 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
2766 if (operand.IsRegisterShiftedRegister()) {
2767 Register rm = operand.GetBaseRegister();
2768 Shift shift = operand.GetShift();
2769 Register rs = operand.GetShiftRegister();
2782 Delegate(kAnd, &Assembler::and_, cond, size, rd, rn, operand);
2789 const Operand& operand) {
2792 if (operand.IsImmediate()) {
2793 uint32_t imm = operand.GetImmediate();
2817 if (operand.IsImmediateShiftedRegister()) {
2818 Register rm = operand.GetBaseRegister();
2819 if (operand.IsPlainRegister()) {
2830 Shift shift = operand.GetShift();
2831 uint32_t amount = operand.GetShiftAmount();
2838 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
2849 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
2854 if (operand.IsRegisterShiftedRegister()) {
2855 Register rm = operand.GetBaseRegister();
2856 Shift shift = operand.GetShift();
2857 Register rs = operand.GetShiftRegister();
2870 Delegate(kAnds, &Assembler::ands, cond, size, rd, rn, operand);
2877 const Operand& operand) {
2880 if (operand.IsImmediate()) {
2881 uint32_t imm = operand.GetImmediate();
2911 if (operand.IsPlainRegister()) {
2912 Register rs = operand.GetBaseRegister();
2939 Delegate(kAsr, &Assembler::asr, cond, size, rd, rm, operand);
2946 const Operand& operand) {
2949 if (operand.IsImmediate()) {
2950 uint32_t imm = operand.GetImmediate();
2980 if (operand.IsPlainRegister()) {
2981 Register rs = operand.GetBaseRegister();
3008 Delegate(kAsrs, &Assembler::asrs, cond, size, rd, rm, operand);
3254 const Operand& operand) {
3257 if (operand.IsImmediate()) {
3258 uint32_t imm = operand.GetImmediate();
3282 if (operand.IsImmediateShiftedRegister()) {
3283 Register rm = operand.GetBaseRegister();
3284 if (operand.IsPlainRegister()) {
3295 Shift shift = operand.GetShift();
3296 uint32_t amount = operand.GetShiftAmount();
3303 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
3314 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
3319 if (operand.IsRegisterShiftedRegister()) {
3320 Register rm = operand.GetBaseRegister();
3321 Shift shift = operand.GetShift();
3322 Register rs = operand.GetShiftRegister();
3335 Delegate(kBic, &Assembler::bic, cond, size, rd, rn, operand);
3342 const Operand& operand) {
3345 if (operand.IsImmediate()) {
3346 uint32_t imm = operand.GetImmediate();
3370 if (operand.IsImmediateShiftedRegister()) {
3371 Register rm = operand.GetBaseRegister();
3372 if (operand.IsPlainRegister()) {
3383 Shift shift = operand.GetShift();
3384 uint32_t amount = operand.GetShiftAmount();
3391 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
3402 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
3407 if (operand.IsRegisterShiftedRegister()) {
3408 Register rm = operand.GetBaseRegister();
3409 Shift shift = operand.GetShift();
3410 Register rs = operand.GetShiftRegister();
3423 Delegate(kBics, &Assembler::bics, cond, size, rd, rn, operand);
3826 const Operand& operand) {
3829 if (operand.IsImmediate()) {
3830 uint32_t imm = operand.GetImmediate();
3853 if (operand.IsImmediateShiftedRegister()) {
3854 Register rm = operand.GetBaseRegister();
3855 if (operand.IsPlainRegister()) {
3865 Shift shift = operand.GetShift();
3866 uint32_t amount = operand.GetShiftAmount();
3873 (operand.GetTypeEncodingValue() << 4) |
3884 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
3889 if (operand.IsRegisterShiftedRegister()) {
3890 Register rm = operand.GetBaseRegister();
3891 Shift shift = operand.GetShift();
3892 Register rs = operand.GetShiftRegister();
3904 Delegate(kCmn, &Assembler::cmn, cond, size, rn, operand);
3910 const Operand& operand) {
3913 if (operand.IsImmediate()) {
3914 uint32_t imm = operand.GetImmediate();
3943 if (operand.IsImmediateShiftedRegister()) {
3944 Register rm = operand.GetBaseRegister();
3945 if (operand.IsPlainRegister()) {
3963 Shift shift = operand.GetShift();
3964 uint32_t amount = operand.GetShiftAmount();
3971 (operand.GetTypeEncodingValue() << 4) |
3982 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
3987 if (operand.IsRegisterShiftedRegister()) {
3988 Register rm = operand.GetBaseRegister();
3989 Shift shift = operand.GetShift();
3990 Register rs = operand.GetShiftRegister();
4002 Delegate(kCmp, &Assembler::cmp, cond, size, rn, operand);
4189 const Operand& operand) {
4192 if (operand.IsImmediate()) {
4193 uint32_t imm = operand.GetImmediate();
4217 if (operand.IsImmediateShiftedRegister()) {
4218 Register rm = operand.GetBaseRegister();
4219 if (operand.IsPlainRegister()) {
4230 Shift shift = operand.GetShift();
4231 uint32_t amount = operand.GetShiftAmount();
4238 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
4249 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
4254 if (operand.IsRegisterShiftedRegister()) {
4255 Register rm = operand.GetBaseRegister();
4256 Shift shift = operand.GetShift();
4257 Register rs = operand.GetShiftRegister();
4270 Delegate(kEor, &Assembler::eor, cond, size, rd, rn, operand);
4277 const Operand& operand) {
4280 if (operand.IsImmediate()) {
4281 uint32_t imm = operand.GetImmediate();
4305 if (operand.IsImmediateShiftedRegister()) {
4306 Register rm = operand.GetBaseRegister();
4307 if (operand.IsPlainRegister()) {
4318 Shift shift = operand.GetShift();
4319 uint32_t amount = operand.GetShiftAmount();
4326 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
4337 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
4342 if (operand.IsRegisterShiftedRegister()) {
4343 Register rm = operand.GetBaseRegister();
4344 Shift shift = operand.GetShift();
4345 Register rs = operand.GetShiftRegister();
4358 Delegate(kEors, &Assembler::eors, cond, size, rd, rn, operand);
4583 void Assembler::lda(Condition cond, Register rt, const MemOperand& operand) {
4586 if (operand.IsImmediateZero()) {
4587 Register rn = operand.GetBaseRegister();
4590 if (operand.IsOffset() &&
4598 if (operand.IsOffset() && cond.IsNotNever() &&
4606 Delegate(kLda, &Assembler::lda, cond, rt, operand);
4609 void Assembler::ldab(Condition cond, Register rt, const MemOperand& operand) {
4612 if (operand.IsImmediateZero()) {
4613 Register rn = operand.GetBaseRegister();
4616 if (operand.IsOffset() &&
4624 if (operand.IsOffset() && cond.IsNotNever() &&
4632 Delegate(kLdab, &Assembler::ldab, cond, rt, operand);
4635 void Assembler::ldaex(Condition cond, Register rt, const MemOperand& operand) {
4638 if (operand.IsImmediateZero()) {
4639 Register rn = operand.GetBaseRegister();
4642 if (operand.IsOffset() &&
4650 if (operand.IsOffset() && cond.IsNotNever() &&
4658 Delegate(kLdaex, &Assembler::ldaex, cond, rt, operand);
4661 void Assembler::ldaexb(Condition cond, Register rt, const MemOperand& operand) {
4664 if (operand.IsImmediateZero()) {
4665 Register rn = operand.GetBaseRegister();
4668 if (operand.IsOffset() &&
4676 if (operand.IsOffset() && cond.IsNotNever() &&
4684 Delegate(kLdaexb, &Assembler::ldaexb, cond, rt, operand);
4690 const MemOperand& operand) {
4693 if (operand.IsImmediateZero()) {
4694 Register rn = operand.GetBaseRegister();
4697 if (operand.IsOffset() &&
4707 operand.IsOffset() && cond.IsNotNever() &&
4716 Delegate(kLdaexd, &Assembler::ldaexd, cond, rt, rt2, operand);
4719 void Assembler::ldaexh(Condition cond, Register rt, const MemOperand& operand) {
4722 if (operand.IsImmediateZero()) {
4723 Register rn = operand.GetBaseRegister();
4726 if (operand.IsOffset() &&
4734 if (operand.IsOffset() && cond.IsNotNever() &&
4742 Delegate(kLdaexh, &Assembler::ldaexh, cond, rt, operand);
4745 void Assembler::ldah(Condition cond, Register rt, const MemOperand& operand) {
4748 if (operand.IsImmediateZero()) {
4749 Register rn = operand.GetBaseRegister();
4752 if (operand.IsOffset() &&
4760 if (operand.IsOffset() && cond.IsNotNever() &&
4768 Delegate(kLdah, &Assembler::ldah, cond, rt, operand);
4996 const MemOperand& operand) {
4999 if (operand.IsImmediate()) {
5000 Register rn = operand.GetBaseRegister();
5001 int32_t offset = operand.GetOffsetImmediate();
5005 (offset <= 124) && ((offset % 4) == 0) && operand.IsOffset()) {
5014 ((offset % 4) == 0) && rn.Is(sp) && operand.IsOffset()) {
5022 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
5032 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
5042 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
5045 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5054 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
5057 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5066 rn.Is(pc) && operand.IsOffset() &&
5069 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5077 if ((offset >= -4095) && (offset <= 4095) && operand.IsOffset() &&
5079 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5087 if ((offset >= -4095) && (offset <= 4095) && operand.IsPostIndex() &&
5089 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5097 if ((offset >= -4095) && (offset <= 4095) && operand.IsPreIndex() &&
5099 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5108 operand.IsOffset() && cond.IsNotNever()) {
5109 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5117 if (operand.IsPlainRegister()) {
5118 Register rn = operand.GetBaseRegister();
5119 Sign sign = operand.GetSign();
5120 Register rm = operand.GetOffsetRegister();
5124 sign.IsPlus() && operand.IsOffset()) {
5132 if (operand.IsShiftedRegister()) {
5133 Register rn = operand.GetBaseRegister();
5134 Sign sign = operand.GetSign();
5135 Register rm = operand.GetOffsetRegister();
5136 Shift shift = operand.GetShift();
5137 uint32_t amount = operand.GetShiftAmount();
5141 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
5151 if (operand.IsShiftValid() && operand.IsOffset() && cond.IsNotNever() &&
5162 if (operand.IsShiftValid() && operand.IsPostIndex() &&
5173 if (operand.IsShiftValid() && operand.IsPreIndex() && cond.IsNotNever() &&
5185 Delegate(kLdr, &Assembler::ldr, cond, size, rt, operand);
5314 const MemOperand& operand) {
5317 if (operand.IsImmediate()) {
5318 Register rn = operand.GetBaseRegister();
5319 int32_t offset = operand.GetOffsetImmediate();
5323 (offset <= 31) && operand.IsOffset()) {
5331 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
5339 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
5347 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
5348 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5357 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
5358 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5367 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) {
5368 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5376 if ((offset >= -4095) && (offset <= 4095) && operand.IsOffset() &&
5379 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5387 if ((offset >= -4095) && (offset <= 4095) && operand.IsPostIndex() &&
5390 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5398 if ((offset >= -4095) && (offset <= 4095) && operand.IsPreIndex() &&
5401 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5410 operand.IsOffset() && cond.IsNotNever() &&
5412 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5420 if (operand.IsPlainRegister()) {
5421 Register rn = operand.GetBaseRegister();
5422 Sign sign = operand.GetSign();
5423 Register rm = operand.GetOffsetRegister();
5427 sign.IsPlus() && operand.IsOffset()) {
5435 if (operand.IsShiftedRegister()) {
5436 Register rn = operand.GetBaseRegister();
5437 Sign sign = operand.GetSign();
5438 Register rm = operand.GetOffsetRegister();
5439 Shift shift = operand.GetShift();
5440 uint32_t amount = operand.GetShiftAmount();
5444 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) &&
5453 if (operand.IsShiftValid() && operand.IsOffset() && cond.IsNotNever() &&
5464 if (operand.IsShiftValid() && operand.IsPostIndex() &&
5476 if (operand.IsShiftValid() && operand.IsPreIndex() && cond.IsNotNever() &&
5488 Delegate(kLdrb, &Assembler::ldrb, cond, size, rt, operand);
5582 const MemOperand& operand) {
5585 if (operand.IsImmediate()) {
5586 Register rn = operand.GetBaseRegister();
5587 int32_t offset = operand.GetOffsetImmediate();
5591 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
5593 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5602 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
5604 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5613 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
5615 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5624 operand.IsOffset() &&
5626 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5636 (offset >= -255) && (offset <= 255) && operand.IsOffset() &&
5640 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5649 (offset >= -255) && (offset <= 255) && operand.IsPostIndex() &&
5653 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5662 (offset >= -255) && (offset <= 255) && operand.IsPreIndex() &&
5666 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5676 operand.IsOffset() && cond.IsNotNever() &&
5679 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5688 if (operand.IsPlainRegister()) {
5689 Register rn = operand.GetBaseRegister();
5690 Sign sign = operand.GetSign();
5691 Register rm = operand.GetOffsetRegister();
5695 operand.IsOffset() && cond.IsNotNever() &&
5706 operand.IsPostIndex() && cond.IsNotNever() &&
5717 operand.IsPreIndex() && cond.IsNotNever() &&
5728 Delegate(kLdrd, &Assembler::ldrd, cond, rt, rt2, operand);
5829 void Assembler::ldrex(Condition cond, Register rt, const MemOperand& operand) {
5832 if (operand.IsImmediate()) {
5833 Register rn = operand.GetBaseRegister();
5834 int32_t offset = operand.GetOffsetImmediate();
5838 operand.IsOffset() &&
5848 if ((offset == 0) && operand.IsOffset() && cond.IsNotNever() &&
5856 Delegate(kLdrex, &Assembler::ldrex, cond, rt, operand);
5859 void Assembler::ldrexb(Condition cond, Register rt, const MemOperand& operand) {
5862 if (operand.IsImmediateZero()) {
5863 Register rn = operand.GetBaseRegister();
5866 if (operand.IsOffset() &&
5874 if (operand.IsOffset() && cond.IsNotNever() &&
5882 Delegate(kLdrexb, &Assembler::ldrexb, cond, rt, operand);
5888 const MemOperand& operand) {
5891 if (operand.IsImmediateZero()) {
5892 Register rn = operand.GetBaseRegister();
5895 if (operand.IsOffset() &&
5905 operand.IsOffset() && cond.IsNotNever() &&
5914 Delegate(kLdrexd, &Assembler::ldrexd, cond, rt, rt2, operand);
5917 void Assembler::ldrexh(Condition cond, Register rt, const MemOperand& operand) {
5920 if (operand.IsImmediateZero()) {
5921 Register rn = operand.GetBaseRegister();
5924 if (operand.IsOffset() &&
5932 if (operand.IsOffset() && cond.IsNotNever() &&
5940 Delegate(kLdrexh, &Assembler::ldrexh, cond, rt, operand);
5946 const MemOperand& operand) {
5949 if (operand.IsImmediate()) {
5950 Register rn = operand.GetBaseRegister();
5951 int32_t offset = operand.GetOffsetImmediate();
5955 (offset <= 62) && ((offset % 2) == 0) && operand.IsOffset()) {
5964 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
5972 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
5980 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
5981 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
5990 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
5991 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6000 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) {
6001 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6009 if ((offset >= -255) && (offset <= 255) && operand.IsOffset() &&
6012 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6020 if ((offset >= -255) && (offset <= 255) && operand.IsPostIndex() &&
6023 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6031 if ((offset >= -255) && (offset <= 255) && operand.IsPreIndex() &&
6034 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6043 operand.IsOffset() && cond.IsNotNever() &&
6045 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6054 if (operand.IsPlainRegister()) {
6055 Register rn = operand.GetBaseRegister();
6056 Sign sign = operand.GetSign();
6057 Register rm = operand.GetOffsetRegister();
6061 sign.IsPlus() && operand.IsOffset()) {
6069 if (operand.IsOffset() && cond.IsNotNever() &&
6078 if (operand.IsPostIndex() && cond.IsNotNever() &&
6087 if (operand.IsPreIndex() && cond.IsNotNever() &&
6097 if (operand.IsShiftedRegister()) {
6098 Register rn = operand.GetBaseRegister();
6099 Sign sign = operand.GetSign();
6100 Register rm = operand.GetOffsetRegister();
6101 Shift shift = operand.GetShift();
6102 uint32_t amount = operand.GetShiftAmount();
6106 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) &&
6115 Delegate(kLdrh, &Assembler::ldrh, cond, size, rt, operand);
6210 const MemOperand& operand) {
6213 if (operand.IsImmediate()) {
6214 Register rn = operand.GetBaseRegister();
6215 int32_t offset = operand.GetOffsetImmediate();
6219 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
6227 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
6235 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
6236 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6245 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
6246 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6255 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) {
6256 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6264 if ((offset >= -255) && (offset <= 255) && operand.IsOffset() &&
6267 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6275 if ((offset >= -255) && (offset <= 255) && operand.IsPostIndex() &&
6278 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6286 if ((offset >= -255) && (offset <= 255) && operand.IsPreIndex() &&
6289 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6298 operand.IsOffset() && cond.IsNotNever() &&
6300 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6309 if (operand.IsPlainRegister()) {
6310 Register rn = operand.GetBaseRegister();
6311 Sign sign = operand.GetSign();
6312 Register rm = operand.GetOffsetRegister();
6316 sign.IsPlus() && operand.IsOffset()) {
6324 if (operand.IsOffset() && cond.IsNotNever() &&
6333 if (operand.IsPostIndex() && cond.IsNotNever() &&
6342 if (operand.IsPreIndex() && cond.IsNotNever() &&
6352 if (operand.IsShiftedRegister()) {
6353 Register rn = operand.GetBaseRegister();
6354 Sign sign = operand.GetSign();
6355 Register rm = operand.GetOffsetRegister();
6356 Shift shift = operand.GetShift();
6357 uint32_t amount = operand.GetShiftAmount();
6361 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) &&
6370 Delegate(kLdrsb, &Assembler::ldrsb, cond, size, rt, operand);
6465 const MemOperand& operand) {
6468 if (operand.IsImmediate()) {
6469 Register rn = operand.GetBaseRegister();
6470 int32_t offset = operand.GetOffsetImmediate();
6474 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
6482 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc)) {
6490 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
6491 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6500 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf)) {
6501 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6510 rn.Is(pc) && operand.IsOffset() && !rt.Is(pc)) {
6511 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6519 if ((offset >= -255) && (offset <= 255) && operand.IsOffset() &&
6522 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6530 if ((offset >= -255) && (offset <= 255) && operand.IsPostIndex() &&
6533 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6541 if ((offset >= -255) && (offset <= 255) && operand.IsPreIndex() &&
6544 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6553 operand.IsOffset() && cond.IsNotNever() &&
6555 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
6564 if (operand.IsPlainRegister()) {
6565 Register rn = operand.GetBaseRegister();
6566 Sign sign = operand.GetSign();
6567 Register rm = operand.GetOffsetRegister();
6571 sign.IsPlus() && operand.IsOffset()) {
6579 if (operand.IsOffset() && cond.IsNotNever() &&
6588 if (operand.IsPostIndex() && cond.IsNotNever() &&
6597 if (operand.IsPreIndex() && cond.IsNotNever() &&
6607 if (operand.IsShiftedRegister()) {
6608 Register rn = operand.GetBaseRegister();
6609 Sign sign = operand.GetSign();
6610 Register rm = operand.GetOffsetRegister();
6611 Shift shift = operand.GetShift();
6612 uint32_t amount = operand.GetShiftAmount();
6616 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) && !rt.Is(pc) &&
6625 Delegate(kLdrsh, &Assembler::ldrsh, cond, size, rt, operand);
6721 const Operand& operand) {
6724 if (operand.IsImmediate()) {
6725 uint32_t imm = operand.GetImmediate();
6751 if (operand.IsPlainRegister()) {
6752 Register rs = operand.GetBaseRegister();
6779 Delegate(kLsl, &Assembler::lsl, cond, size, rd, rm, operand);
6786 const Operand& operand) {
6789 if (operand.IsImmediate()) {
6790 uint32_t imm = operand.GetImmediate();
6816 if (operand.IsPlainRegister()) {
6817 Register rs = operand.GetBaseRegister();
6844 Delegate(kLsls, &Assembler::lsls, cond, size, rd, rm, operand);
6851 const Operand& operand) {
6854 if (operand.IsImmediate()) {
6855 uint32_t imm = operand.GetImmediate();
6885 if (operand.IsPlainRegister()) {
6886 Register rs = operand.GetBaseRegister();
6913 Delegate(kLsr, &Assembler::lsr, cond, size, rd, rm, operand);
6920 const Operand& operand) {
6923 if (operand.IsImmediate()) {
6924 uint32_t imm = operand.GetImmediate();
6954 if (operand.IsPlainRegister()) {
6955 Register rs = operand.GetBaseRegister();
6982 Delegate(kLsrs, &Assembler::lsrs, cond, size, rd, rm, operand);
7057 const Operand& operand) {
7060 if (operand.IsImmediateShiftedRegister()) {
7061 Register rm = operand.GetBaseRegister();
7062 if (operand.IsPlainRegister()) {
7075 Shift shift = operand.GetShift();
7076 uint32_t amount = operand.GetShiftAmount();
7085 (operand.GetTypeEncodingValue() << 11) | (amount_ << 6));
7094 (operand.GetTypeEncodingValue() << 4) |
7105 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
7110 if (operand.IsRegisterShiftedRegister()) {
7111 Register rm = operand.GetBaseRegister();
7112 Shift shift = operand.GetShift();
7113 Register rs = operand.GetShiftRegister();
7162 if (operand.IsImmediate()) {
7163 uint32_t imm = operand.GetImmediate();
7208 Delegate(kMov, &Assembler::mov, cond, size, rd, operand);
7214 const Operand& operand) {
7217 if (operand.IsImmediateShiftedRegister()) {
7218 Register rm = operand.GetBaseRegister();
7219 Shift shift = operand.GetShift();
7220 uint32_t amount = operand.GetShiftAmount();
7228 (operand.GetTypeEncodingValue() << 11) | (amount_ << 6));
7237 (operand.GetTypeEncodingValue() << 4) |
7249 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
7254 if (operand.IsRegisterShiftedRegister()) {
7255 Register rm = operand.GetBaseRegister();
7256 Shift shift = operand.GetShift();
7257 Register rs = operand.GetShiftRegister();
7306 if (operand.IsImmediate()) {
7307 uint32_t imm = operand.GetImmediate();
7336 Delegate(kMovs, &Assembler::movs, cond, size, rd, operand);
7339 void Assembler::movt(Condition cond, Register rd, const Operand& operand) {
7342 if (operand.IsImmediate()) {
7343 uint32_t imm = operand.GetImmediate();
7363 Delegate(kMovt, &Assembler::movt, cond, rd, operand);
7366 void Assembler::movw(Condition cond, Register rd, const Operand& operand) {
7369 if (operand.IsImmediate()) {
7370 uint32_t imm = operand.GetImmediate();
7390 Delegate(kMovw, &Assembler::movw, cond, rd, operand);
7416 const Operand& operand) {
7419 if (operand.IsImmediate()) {
7420 uint32_t imm = operand.GetImmediate();
7433 if (operand.IsPlainRegister()) {
7434 Register rn = operand.GetBaseRegister();
7453 Delegate(kMsr, &Assembler::msr, cond, spec_reg, operand);
7513 const Operand& operand) {
7516 if (operand.IsImmediate()) {
7517 uint32_t imm = operand.GetImmediate();
7540 if (operand.IsImmediateShiftedRegister()) {
7541 Register rm = operand.GetBaseRegister();
7542 if (operand.IsPlainRegister()) {
7552 Shift shift = operand.GetShift();
7553 uint32_t amount = operand.GetShiftAmount();
7560 (operand.GetTypeEncodingValue() << 4) |
7571 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
7576 if (operand.IsRegisterShiftedRegister()) {
7577 Register rm = operand.GetBaseRegister();
7578 Shift shift = operand.GetShift();
7579 Register rs = operand.GetShiftRegister();
7591 Delegate(kMvn, &Assembler::mvn, cond, size, rd, operand);
7597 const Operand& operand) {
7600 if (operand.IsImmediate()) {
7601 uint32_t imm = operand.GetImmediate();
7624 if (operand.IsImmediateShiftedRegister()) {
7625 Register rm = operand.GetBaseRegister();
7626 if (operand.IsPlainRegister()) {
7636 Shift shift = operand.GetShift();
7637 uint32_t amount = operand.GetShiftAmount();
7644 (operand.GetTypeEncodingValue() << 4) |
7655 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
7660 if (operand.IsRegisterShiftedRegister()) {
7661 Register rm = operand.GetBaseRegister();
7662 Shift shift = operand.GetShift();
7663 Register rs = operand.GetShiftRegister();
7675 Delegate(kMvns, &Assembler::mvns, cond, size, rd, operand);
7707 const Operand& operand) {
7710 if (operand.IsImmediate()) {
7711 uint32_t imm = operand.GetImmediate();
7726 if (operand.IsImmediateShiftedRegister()) {
7727 Register rm = operand.GetBaseRegister();
7728 Shift shift = operand.GetShift();
7729 uint32_t amount = operand.GetShiftAmount();
7736 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
7743 Delegate(kOrn, &Assembler::orn, cond, rd, rn, operand);
7749 const Operand& operand) {
7752 if (operand.IsImmediate()) {
7753 uint32_t imm = operand.GetImmediate();
7768 if (operand.IsImmediateShiftedRegister()) {
7769 Register rm = operand.GetBaseRegister();
7770 Shift shift = operand.GetShift();
7771 uint32_t amount = operand.GetShiftAmount();
7778 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
7785 Delegate(kOrns, &Assembler::orns, cond, rd, rn, operand);
7792 const Operand& operand) {
7795 if (operand.IsImmediate()) {
7796 uint32_t imm = operand.GetImmediate();
7820 if (operand.IsImmediateShiftedRegister()) {
7821 Register rm = operand.GetBaseRegister();
7822 if (operand.IsPlainRegister()) {
7833 Shift shift = operand.GetShift();
7834 uint32_t amount = operand.GetShiftAmount();
7841 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
7852 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
7857 if (operand.IsRegisterShiftedRegister()) {
7858 Register rm = operand.GetBaseRegister();
7859 Shift shift = operand.GetShift();
7860 Register rs = operand.GetShiftRegister();
7873 Delegate(kOrr, &Assembler::orr, cond, size, rd, rn, operand);
7880 const Operand& operand) {
7883 if (operand.IsImmediate()) {
7884 uint32_t imm = operand.GetImmediate();
7908 if (operand.IsImmediateShiftedRegister()) {
7909 Register rm = operand.GetBaseRegister();
7910 if (operand.IsPlainRegister()) {
7921 Shift shift = operand.GetShift();
7922 uint32_t amount = operand.GetShiftAmount();
7929 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
7940 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
7945 if (operand.IsRegisterShiftedRegister()) {
7946 Register rm = operand.GetBaseRegister();
7947 Shift shift = operand.GetShift();
7948 Register rs = operand.GetShiftRegister();
7961 Delegate(kOrrs, &Assembler::orrs, cond, size, rd, rn, operand);
7967 const Operand& operand) {
7970 if (operand.IsImmediateShiftedRegister()) {
7971 Register rm = operand.GetBaseRegister();
7972 Shift shift = operand.GetShift();
7973 uint32_t amount = operand.GetShiftAmount();
7995 Delegate(kPkhbt, &Assembler::pkhbt, cond, rd, rn, operand);
8001 const Operand& operand) {
8004 if (operand.IsImmediateShiftedRegister()) {
8005 Register rm = operand.GetBaseRegister();
8006 Shift shift = operand.GetShift();
8007 uint32_t amount = operand.GetShiftAmount();
8032 Delegate(kPkhtb, &Assembler::pkhtb, cond, rd, rn, operand);
8116 void Assembler::pld(Condition cond, const MemOperand& operand) {
8119 if (operand.IsImmediate()) {
8120 Register rn = operand.GetBaseRegister();
8121 int32_t offset = operand.GetOffsetImmediate();
8125 operand.IsOffset()) {
8126 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
8135 operand.IsOffset()) {
8137 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
8145 if (operand.IsImmediate()) {
8146 Register rn = operand.GetBaseRegister();
8147 int32_t offset = operand.GetOffsetImmediate();
8150 if ((offset >= 0) && (offset <= 4095) && operand.IsOffset() &&
8157 if ((-offset >= 0) && (-offset <= 255) && operand.IsOffset() &&
8165 if ((offset >= -4095) && (offset <= 4095) && operand.IsOffset() &&
8168 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
8176 if (operand.IsShiftedRegister()) {
8177 Register rn = operand.GetBaseRegister();
8178 Sign sign = operand.GetSign();
8179 Register rm = operand.GetOffsetRegister();
8180 Shift shift = operand.GetShift();
8181 uint32_t amount = operand.GetShiftAmount();
8184 if (sign.IsPlus() && shift.IsLSL() && operand.IsOffset() &&
8194 if (!shift.IsRRX() && shift.IsValidAmount(amount) && operand.IsOffset() &&
8205 if (shift.IsRRX() && operand.IsOffset() &&
8216 Delegate(kPld, &Assembler::pld, cond, operand);
8219 void Assembler::pldw(Condition cond, const MemOperand& operand) {
8222 if (operand.IsImmediate()) {
8223 Register rn = operand.GetBaseRegister();
8224 int32_t offset = operand.GetOffsetImmediate();
8227 if ((offset >= 0) && (offset <= 4095) && operand.IsOffset() &&
8234 if ((-offset >= 0) && (-offset <= 255) && operand.IsOffset() &&
8242 if ((offset >= -4095) && (offset <= 4095) && operand.IsOffset() &&
8245 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
8253 if (operand.IsShiftedRegister()) {
8254 Register rn = operand.GetBaseRegister();
8255 Sign sign = operand.GetSign();
8256 Register rm = operand.GetOffsetRegister();
8257 Shift shift = operand.GetShift();
8258 uint32_t amount = operand.GetShiftAmount();
8261 if (sign.IsPlus() && shift.IsLSL() && operand.IsOffset() &&
8271 if (!shift.IsRRX() && shift.IsValidAmount(amount) && operand.IsOffset() &&
8282 if (shift.IsRRX() && operand.IsOffset() &&
8293 Delegate(kPldw, &Assembler::pldw, cond, operand);
8296 void Assembler::pli(Condition cond, const MemOperand& operand) {
8299 if (operand.IsImmediate()) {
8300 Register rn = operand.GetBaseRegister();
8301 int32_t offset = operand.GetOffsetImmediate();
8304 if ((offset >= 0) && (offset <= 4095) && operand.IsOffset() &&
8311 if ((-offset >= 0) && (-offset <= 255) && operand.IsOffset() &&
8319 if ((offset >= -4095) && (offset <= 4095) && operand.IsOffset() &&
8322 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
8330 if (operand.IsImmediate()) {
8331 Register rn = operand.GetBaseRegister();
8332 int32_t offset = operand.GetOffsetImmediate();
8336 operand.IsOffset()) {
8337 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
8346 operand.IsOffset()) {
8348 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
8356 if (operand.IsShiftedRegister()) {
8357 Register rn = operand.GetBaseRegister();
8358 Sign sign = operand.GetSign();
8359 Register rm = operand.GetOffsetRegister();
8360 Shift shift = operand.GetShift();
8361 uint32_t amount = operand.GetShiftAmount();
8364 if (sign.IsPlus() && shift.IsLSL() && operand.IsOffset() &&
8374 if (shift.IsRRX() && operand.IsOffset() &&
8384 if (!shift.IsRRX() && shift.IsValidAmount(amount) && operand.IsOffset() &&
8396 Delegate(kPli, &Assembler::pli, cond, operand);
8967 const Operand& operand) {
8970 if (operand.IsImmediate()) {
8971 uint32_t imm = operand.GetImmediate();
8990 if (operand.IsPlainRegister()) {
8991 Register rs = operand.GetBaseRegister();
9018 Delegate(kRor, &Assembler::ror, cond, size, rd, rm, operand);
9025 const Operand& operand) {
9028 if (operand.IsImmediate()) {
9029 uint32_t imm = operand.GetImmediate();
9048 if (operand.IsPlainRegister()) {
9049 Register rs = operand.GetBaseRegister();
9076 Delegate(kRors, &Assembler::rors, cond, size, rd, rm, operand);
9125 const Operand& operand) {
9128 if (operand.IsImmediate()) {
9129 uint32_t imm = operand.GetImmediate();
9160 if (operand.IsImmediateShiftedRegister()) {
9161 Register rm = operand.GetBaseRegister();
9162 Shift shift = operand.GetShift();
9163 uint32_t amount = operand.GetShiftAmount();
9170 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
9181 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
9186 if (operand.IsRegisterShiftedRegister()) {
9187 Register rm = operand.GetBaseRegister();
9188 Shift shift = operand.GetShift();
9189 Register rs = operand.GetShiftRegister();
9202 Delegate(kRsb, &Assembler::rsb, cond, size, rd, rn, operand);
9209 const Operand& operand) {
9212 if (operand.IsImmediate()) {
9213 uint32_t imm = operand.GetImmediate();
9244 if (operand.IsImmediateShiftedRegister()) {
9245 Register rm = operand.GetBaseRegister();
9246 Shift shift = operand.GetShift();
9247 uint32_t amount = operand.GetShiftAmount();
9254 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
9265 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
9270 if (operand.IsRegisterShiftedRegister()) {
9271 Register rm = operand.GetBaseRegister();
9272 Shift shift = operand.GetShift();
9273 Register rs = operand.GetShiftRegister();
9286 Delegate(kRsbs, &Assembler::rsbs, cond, size, rd, rn, operand);
9292 const Operand& operand) {
9295 if (operand.IsImmediate()) {
9296 uint32_t imm = operand.GetImmediate();
9308 if (operand.IsImmediateShiftedRegister()) {
9309 Register rm = operand.GetBaseRegister();
9310 Shift shift = operand.GetShift();
9311 uint32_t amount = operand.GetShiftAmount();
9318 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
9323 if (operand.IsRegisterShiftedRegister()) {
9324 Register rm = operand.GetBaseRegister();
9325 Shift shift = operand.GetShift();
9326 Register rs = operand.GetShiftRegister();
9339 Delegate(kRsc, &Assembler::rsc, cond, rd, rn, operand);
9345 const Operand& operand) {
9348 if (operand.IsImmediate()) {
9349 uint32_t imm = operand.GetImmediate();
9361 if (operand.IsImmediateShiftedRegister()) {
9362 Register rm = operand.GetBaseRegister();
9363 Shift shift = operand.GetShift();
9364 uint32_t amount = operand.GetShiftAmount();
9371 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
9376 if (operand.IsRegisterShiftedRegister()) {
9377 Register rm = operand.GetBaseRegister();
9378 Shift shift = operand.GetShift();
9379 Register rs = operand.GetShiftRegister();
9392 Delegate(kRscs, &Assembler::rscs, cond, rd, rn, operand);
9468 const Operand& operand) {
9471 if (operand.IsImmediate()) {
9472 uint32_t imm = operand.GetImmediate();
9496 if (operand.IsImmediateShiftedRegister()) {
9497 Register rm = operand.GetBaseRegister();
9498 if (operand.IsPlainRegister()) {
9509 Shift shift = operand.GetShift();
9510 uint32_t amount = operand.GetShiftAmount();
9517 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
9528 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
9533 if (operand.IsRegisterShiftedRegister()) {
9534 Register rm = operand.GetBaseRegister();
9535 Shift shift = operand.GetShift();
9536 Register rs = operand.GetShiftRegister();
9549 Delegate(kSbc, &Assembler::sbc, cond, size, rd, rn, operand);
9556 const Operand& operand) {
9559 if (operand.IsImmediate()) {
9560 uint32_t imm = operand.GetImmediate();
9584 if (operand.IsImmediateShiftedRegister()) {
9585 Register rm = operand.GetBaseRegister();
9586 if (operand.IsPlainRegister()) {
9597 Shift shift = operand.GetShift();
9598 uint32_t amount = operand.GetShiftAmount();
9605 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
9616 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
9621 if (operand.IsRegisterShiftedRegister()) {
9622 Register rm = operand.GetBaseRegister();
9623 Shift shift = operand.GetShift();
9624 Register rs = operand.GetShiftRegister();
9637 Delegate(kSbcs, &Assembler::sbcs, cond, size, rd, rn, operand);
10796 const Operand& operand) {
10799 if (operand.IsImmediateShiftedRegister()) {
10800 Register rn = operand.GetBaseRegister();
10801 Shift shift = operand.GetShift();
10802 uint32_t amount = operand.GetShiftAmount();
10849 Delegate(kSsat, &Assembler::ssat, cond, rd, imm, operand);
10947 void Assembler::stl(Condition cond, Register rt, const MemOperand& operand) {
10950 if (operand.IsImmediateZero()) {
10951 Register rn = operand.GetBaseRegister();
10954 if (operand.IsOffset() &&
10962 if (operand.IsOffset() && cond.IsNotNever() &&
10970 Delegate(kStl, &Assembler::stl, cond, rt, operand);
10973 void Assembler::stlb(Condition cond, Register rt, const MemOperand& operand) {
10976 if (operand.IsImmediateZero()) {
10977 Register rn = operand.GetBaseRegister();
10980 if (operand.IsOffset() &&
10988 if (operand.IsOffset() && cond.IsNotNever() &&
10996 Delegate(kStlb, &Assembler::stlb, cond, rt, operand);
11002 const MemOperand& operand) {
11005 if (operand.IsImmediateZero()) {
11006 Register rn = operand.GetBaseRegister();
11009 if (operand.IsOffset() &&
11018 if (operand.IsOffset() && cond.IsNotNever() &&
11026 Delegate(kStlex, &Assembler::stlex, cond, rd, rt, operand);
11032 const MemOperand& operand) {
11035 if (operand.IsImmediateZero()) {
11036 Register rn = operand.GetBaseRegister();
11039 if (operand.IsOffset() &&
11048 if (operand.IsOffset() && cond.IsNotNever() &&
11056 Delegate(kStlexb, &Assembler::stlexb, cond, rd, rt, operand);
11063 const MemOperand& operand) {
11066 if (operand.IsImmediateZero()) {
11067 Register rn = operand.GetBaseRegister();
11070 if (operand.IsOffset() &&
11081 operand.IsOffset() && cond.IsNotNever() &&
11091 Delegate(kStlexd, &Assembler::stlexd, cond, rd, rt, rt2, operand);
11097 const MemOperand& operand) {
11100 if (operand.IsImmediateZero()) {
11101 Register rn = operand.GetBaseRegister();
11104 if (operand.IsOffset() &&
11113 if (operand.IsOffset() && cond.IsNotNever() &&
11121 Delegate(kStlexh, &Assembler::stlexh, cond, rd, rt, operand);
11124 void Assembler::stlh(Condition cond, Register rt, const MemOperand& operand) {
11127 if (operand.IsImmediateZero()) {
11128 Register rn = operand.GetBaseRegister();
11131 if (operand.IsOffset() &&
11139 if (operand.IsOffset() && cond.IsNotNever() &&
11147 Delegate(kStlh, &Assembler::stlh, cond, rt, operand);
11378 const MemOperand& operand) {
11381 if (operand.IsImmediate()) {
11382 Register rn = operand.GetBaseRegister();
11383 int32_t offset = operand.GetOffsetImmediate();
11387 (offset <= 124) && ((offset % 4) == 0) && operand.IsOffset()) {
11396 ((offset % 4) == 0) && rn.Is(sp) && operand.IsOffset()) {
11404 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11413 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11422 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11424 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11433 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11435 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11444 if ((offset >= -4095) && (offset <= 4095) && operand.IsOffset() &&
11446 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11454 if ((offset >= -4095) && (offset <= 4095) && operand.IsPostIndex() &&
11456 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11464 if ((offset >= -4095) && (offset <= 4095) && operand.IsPreIndex() &&
11466 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11475 if (operand.IsPlainRegister()) {
11476 Register rn = operand.GetBaseRegister();
11477 Sign sign = operand.GetSign();
11478 Register rm = operand.GetOffsetRegister();
11482 sign.IsPlus() && operand.IsOffset()) {
11490 if (operand.IsShiftedRegister()) {
11491 Register rn = operand.GetBaseRegister();
11492 Sign sign = operand.GetSign();
11493 Register rm = operand.GetOffsetRegister();
11494 Shift shift = operand.GetShift();
11495 uint32_t amount = operand.GetShiftAmount();
11499 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11508 if (operand.IsShiftValid() && operand.IsOffset() && cond.IsNotNever() &&
11519 if (operand.IsShiftValid() && operand.IsPostIndex() &&
11530 if (operand.IsShiftValid() && operand.IsPreIndex() && cond.IsNotNever() &&
11542 Delegate(kStr, &Assembler::str, cond, size, rt, operand);
11548 const MemOperand& operand) {
11551 if (operand.IsImmediate()) {
11552 Register rn = operand.GetBaseRegister();
11553 int32_t offset = operand.GetOffsetImmediate();
11557 (offset <= 31) && operand.IsOffset()) {
11565 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11574 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11583 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11585 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11594 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11596 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11605 if ((offset >= -4095) && (offset <= 4095) && operand.IsOffset() &&
11607 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11615 if ((offset >= -4095) && (offset <= 4095) && operand.IsPostIndex() &&
11617 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11625 if ((offset >= -4095) && (offset <= 4095) && operand.IsPreIndex() &&
11627 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11636 if (operand.IsPlainRegister()) {
11637 Register rn = operand.GetBaseRegister();
11638 Sign sign = operand.GetSign();
11639 Register rm = operand.GetOffsetRegister();
11643 sign.IsPlus() && operand.IsOffset()) {
11651 if (operand.IsShiftedRegister()) {
11652 Register rn = operand.GetBaseRegister();
11653 Sign sign = operand.GetSign();
11654 Register rm = operand.GetOffsetRegister();
11655 Shift shift = operand.GetShift();
11656 uint32_t amount = operand.GetShiftAmount();
11660 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11669 if (operand.IsShiftValid() && operand.IsOffset() && cond.IsNotNever() &&
11680 if (operand.IsShiftValid() && operand.IsPostIndex() &&
11692 if (operand.IsShiftValid() && operand.IsPreIndex() && cond.IsNotNever() &&
11704 Delegate(kStrb, &Assembler::strb, cond, size, rt, operand);
11710 const MemOperand& operand) {
11713 if (operand.IsImmediate()) {
11714 Register rn = operand.GetBaseRegister();
11715 int32_t offset = operand.GetOffsetImmediate();
11719 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11721 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11730 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11732 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11741 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
11743 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11753 (offset >= -255) && (offset <= 255) && operand.IsOffset() &&
11756 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11765 (offset >= -255) && (offset <= 255) && operand.IsPostIndex() &&
11768 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11777 (offset >= -255) && (offset <= 255) && operand.IsPreIndex() &&
11780 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
11789 if (operand.IsPlainRegister()) {
11790 Register rn = operand.GetBaseRegister();
11791 Sign sign = operand.GetSign();
11792 Register rm = operand.GetOffsetRegister();
11796 operand.IsOffset() && cond.IsNotNever() &&
11807 operand.IsPostIndex() && cond.IsNotNever() &&
11818 operand.IsPreIndex() && cond.IsNotNever() &&
11829 Delegate(kStrd, &Assembler::strd, cond, rt, rt2, operand);
11835 const MemOperand& operand) {
11838 if (operand.IsImmediate()) {
11839 Register rn = operand.GetBaseRegister();
11840 int32_t offset = operand.GetOffsetImmediate();
11844 operand.IsOffset() &&
11854 if ((offset == 0) && operand.IsOffset() && cond.IsNotNever() &&
11862 Delegate(kStrex, &Assembler::strex, cond, rd, rt, operand);
11868 const MemOperand& operand) {
11871 if (operand.IsImmediateZero()) {
11872 Register rn = operand.GetBaseRegister();
11875 if (operand.IsOffset() &&
11884 if (operand.IsOffset() && cond.IsNotNever() &&
11892 Delegate(kStrexb, &Assembler::strexb, cond, rd, rt, operand);
11899 const MemOperand& operand) {
11902 if (operand.IsImmediateZero()) {
11903 Register rn = operand.GetBaseRegister();
11906 if (operand.IsOffset() &&
11917 operand.IsOffset() && cond.IsNotNever() &&
11927 Delegate(kStrexd, &Assembler::strexd, cond, rd, rt, rt2, operand);
11933 const MemOperand& operand) {
11936 if (operand.IsImmediateZero()) {
11937 Register rn = operand.GetBaseRegister();
11940 if (operand.IsOffset() &&
11949 if (operand.IsOffset() && cond.IsNotNever() &&
11957 Delegate(kStrexh, &Assembler::strexh, cond, rd, rt, operand);
11963 const MemOperand& operand) {
11966 if (operand.IsImmediate()) {
11967 Register rn = operand.GetBaseRegister();
11968 int32_t offset = operand.GetOffsetImmediate();
11972 (offset <= 62) && ((offset % 2) == 0) && operand.IsOffset()) {
11981 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11990 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
11999 operand.IsPostIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
12001 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
12010 operand.IsPreIndex() && ((rn.GetCode() & 0xf) != 0xf) &&
12012 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
12021 if ((offset >= -255) && (offset <= 255) && operand.IsOffset() &&
12023 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
12031 if ((offset >= -255) && (offset <= 255) && operand.IsPostIndex() &&
12033 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
12041 if ((offset >= -255) && (offset <= 255) && operand.IsPreIndex() &&
12043 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
12052 if (operand.IsPlainRegister()) {
12053 Register rn = operand.GetBaseRegister();
12054 Sign sign = operand.GetSign();
12055 Register rm = operand.GetOffsetRegister();
12059 sign.IsPlus() && operand.IsOffset()) {
12067 if (operand.IsOffset() && cond.IsNotNever() &&
12076 if (operand.IsPostIndex() && cond.IsNotNever() &&
12085 if (operand.IsPreIndex() && cond.IsNotNever() &&
12095 if (operand.IsShiftedRegister()) {
12096 Register rn = operand.GetBaseRegister();
12097 Sign sign = operand.GetSign();
12098 Register rm = operand.GetOffsetRegister();
12099 Shift shift = operand.GetShift();
12100 uint32_t amount = operand.GetShiftAmount();
12104 operand.IsOffset() && ((rn.GetCode() & 0xf) != 0xf) &&
12113 Delegate(kStrh, &Assembler::strh, cond, size, rt, operand);
12120 const Operand& operand) {
12123 if (operand.IsImmediate()) {
12124 uint32_t imm = operand.GetImmediate();
12217 if (operand.IsImmediateShiftedRegister()) {
12218 Register rm = operand.GetBaseRegister();
12219 if (operand.IsPlainRegister()) {
12237 Shift shift = operand.GetShift();
12238 uint32_t amount = operand.GetShiftAmount();
12245 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
12255 (operand.GetTypeEncodingValue() << 4) |
12266 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
12274 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
12279 if (operand.IsRegisterShiftedRegister()) {
12280 Register rm = operand.GetBaseRegister();
12281 Shift shift = operand.GetShift();
12282 Register rs = operand.GetShiftRegister();
12295 Delegate(kSub, &Assembler::sub, cond, size, rd, rn, operand);
12298 void Assembler::sub(Condition cond, Register rd, const Operand& operand) {
12301 if (operand.IsImmediate()) {
12302 uint32_t imm = operand.GetImmediate();
12312 Delegate(kSub, &Assembler::sub, cond, rd, operand);
12319 const Operand& operand) {
12322 if (operand.IsImmediate()) {
12323 uint32_t imm = operand.GetImmediate();
12384 if (operand.IsImmediateShiftedRegister()) {
12385 Register rm = operand.GetBaseRegister();
12386 if (operand.IsPlainRegister()) {
12398 Shift shift = operand.GetShift();
12399 uint32_t amount = operand.GetShiftAmount();
12406 rm.GetCode() | (operand.GetTypeEncodingValue() << 4) |
12416 (operand.GetTypeEncodingValue() << 4) |
12427 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
12435 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
12440 if (operand.IsRegisterShiftedRegister()) {
12441 Register rm = operand.GetBaseRegister();
12442 Shift shift = operand.GetShift();
12443 Register rs = operand.GetShiftRegister();
12456 Delegate(kSubs, &Assembler::subs, cond, size, rd, rn, operand);
12459 void Assembler::subs(Register rd, const Operand& operand) {
12462 if (operand.IsImmediate()) {
12463 uint32_t imm = operand.GetImmediate();
12473 Delegate(kSubs, &Assembler::subs, rd, operand);
12479 const Operand& operand) {
12482 if (operand.IsImmediate()) {
12483 uint32_t imm = operand.GetImmediate();
12502 Delegate(kSubw, &Assembler::subw, cond, rd, rn, operand);
12528 const Operand& operand) {
12531 if (operand.IsImmediateShiftedRegister()) {
12532 Register rm = operand.GetBaseRegister();
12533 Shift shift = operand.GetShift();
12534 uint32_t amount = operand.GetShiftAmount();
12559 Delegate(kSxtab, &Assembler::sxtab, cond, rd, rn, operand);
12565 const Operand& operand) {
12568 if (operand.IsImmediateShiftedRegister()) {
12569 Register rm = operand.GetBaseRegister();
12570 Shift shift = operand.GetShift();
12571 uint32_t amount = operand.GetShiftAmount();
12596 Delegate(kSxtab16, &Assembler::sxtab16, cond, rd, rn, operand);
12602 const Operand& operand) {
12605 if (operand.IsImmediateShiftedRegister()) {
12606 Register rm = operand.GetBaseRegister();
12607 Shift shift = operand.GetShift();
12608 uint32_t amount = operand.GetShiftAmount();
12633 Delegate(kSxtah, &Assembler::sxtah, cond, rd, rn, operand);
12639 const Operand& operand) {
12642 if (operand.IsImmediateShiftedRegister()) {
12643 Register rm = operand.GetBaseRegister();
12644 if (operand.IsPlainRegister()) {
12654 Shift shift = operand.GetShift();
12655 uint32_t amount = operand.GetShiftAmount();
12679 Delegate(kSxtb, &Assembler::sxtb, cond, size, rd, operand);
12682 void Assembler::sxtb16(Condition cond, Register rd, const Operand& operand) {
12685 if (operand.IsImmediateShiftedRegister()) {
12686 Register rm = operand.GetBaseRegister();
12687 Shift shift = operand.GetShift();
12688 uint32_t amount = operand.GetShiftAmount();
12712 Delegate(kSxtb16, &Assembler::sxtb16, cond, rd, operand);
12718 const Operand& operand) {
12721 if (operand.IsImmediateShiftedRegister()) {
12722 Register rm = operand.GetBaseRegister();
12723 if (operand.IsPlainRegister()) {
12733 Shift shift = operand.GetShift();
12734 uint32_t amount = operand.GetShiftAmount();
12758 Delegate(kSxth, &Assembler::sxth, cond, size, rd, operand);
12791 void Assembler::teq(Condition cond, Register rn, const Operand& operand) {
12794 if (operand.IsImmediate()) {
12795 uint32_t imm = operand.GetImmediate();
12817 if (operand.IsImmediateShiftedRegister()) {
12818 Register rm = operand.GetBaseRegister();
12819 Shift shift = operand.GetShift();
12820 uint32_t amount = operand.GetShiftAmount();
12827 (operand.GetTypeEncodingValue() << 4) |
12838 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
12843 if (operand.IsRegisterShiftedRegister()) {
12844 Register rm = operand.GetBaseRegister();
12845 Shift shift = operand.GetShift();
12846 Register rs = operand.GetShiftRegister();
12858 Delegate(kTeq, &Assembler::teq, cond, rn, operand);
12864 const Operand& operand) {
12867 if (operand.IsImmediate()) {
12868 uint32_t imm = operand.GetImmediate();
12891 if (operand.IsImmediateShiftedRegister()) {
12892 Register rm = operand.GetBaseRegister();
12893 if (operand.IsPlainRegister()) {
12903 Shift shift = operand.GetShift();
12904 uint32_t amount = operand.GetShiftAmount();
12911 (operand.GetTypeEncodingValue() << 4) |
12922 (operand.GetTypeEncodingValue() << 5) | (amount_ << 7));
12927 if (operand.IsRegisterShiftedRegister()) {
12928 Register rm = operand.GetBaseRegister();
12929 Shift shift = operand.GetShift();
12930 Register rs = operand.GetShiftRegister();
12942 Delegate(kTst, &Assembler::tst, cond, size, rn, operand);
13542 const Operand& operand) {
13545 if (operand.IsImmediateShiftedRegister()) {
13546 Register rn = operand.GetBaseRegister();
13547 Shift shift = operand.GetShift();
13548 uint32_t amount = operand.GetShiftAmount();
13589 Delegate(kUsat, &Assembler::usat, cond, rd, imm, operand);
13687 const Operand& operand) {
13690 if (operand.IsImmediateShiftedRegister()) {
13691 Register rm = operand.GetBaseRegister();
13692 Shift shift = operand.GetShift();
13693 uint32_t amount = operand.GetShiftAmount();
13718 Delegate(kUxtab, &Assembler::uxtab, cond, rd, rn, operand);
13724 const Operand& operand) {
13727 if (operand.IsImmediateShiftedRegister()) {
13728 Register rm = operand.GetBaseRegister();
13729 Shift shift = operand.GetShift();
13730 uint32_t amount = operand.GetShiftAmount();
13755 Delegate(kUxtab16, &Assembler::uxtab16, cond, rd, rn, operand);
13761 const Operand& operand) {
13764 if (operand.IsImmediateShiftedRegister()) {
13765 Register rm = operand.GetBaseRegister();
13766 Shift shift = operand.GetShift();
13767 uint32_t amount = operand.GetShiftAmount();
13792 Delegate(kUxtah, &Assembler::uxtah, cond, rd, rn, operand);
13798 const Operand& operand) {
13801 if (operand.IsImmediateShiftedRegister()) {
13802 Register rm = operand.GetBaseRegister();
13803 if (operand.IsPlainRegister()) {
13813 Shift shift = operand.GetShift();
13814 uint32_t amount = operand.GetShiftAmount();
13838 Delegate(kUxtb, &Assembler::uxtb, cond, size, rd, operand);
13841 void Assembler::uxtb16(Condition cond, Register rd, const Operand& operand) {
13844 if (operand.IsImmediateShiftedRegister()) {
13845 Register rm = operand.GetBaseRegister();
13846 Shift shift = operand.GetShift();
13847 uint32_t amount = operand.GetShiftAmount();
13871 Delegate(kUxtb16, &Assembler::uxtb16, cond, rd, operand);
13877 const Operand& operand) {
13880 if (operand.IsImmediateShiftedRegister()) {
13881 Register rm = operand.GetBaseRegister();
13882 if (operand.IsPlainRegister()) {
13892 Shift shift = operand.GetShift();
13893 uint32_t amount = operand.GetShiftAmount();
13917 Delegate(kUxth, &Assembler::uxth, cond, size, rd, operand);
14659 const DOperand& operand) {
14662 if (operand.IsImmediate()) {
14663 ImmediateVand encoded_dt(dt, operand.GetNeonImmediate());
14690 if (operand.IsRegister()) {
14691 DRegister rm = operand.GetRegister();
14710 Delegate(kVand, &Assembler::vand, cond, dt, rd, rn, operand);
14717 const QOperand& operand) {
14720 if (operand.IsImmediate()) {
14721 ImmediateVand encoded_dt(dt, operand.GetNeonImmediate());
14748 if (operand.IsRegister()) {
14749 QRegister rm = operand.GetRegister();
14768 Delegate(kVand, &Assembler::vand, cond, dt, rd, rn, operand);
14775 const DOperand& operand) {
14778 if (operand.IsImmediate()) {
14779 ImmediateVbic encoded_dt(dt, operand.GetNeonImmediate());
14806 if (operand.IsRegister()) {
14807 DRegister rm = operand.GetRegister();
14826 Delegate(kVbic, &Assembler::vbic, cond, dt, rd, rn, operand);
14833 const QOperand& operand) {
14836 if (operand.IsImmediate()) {
14837 ImmediateVbic encoded_dt(dt, operand.GetNeonImmediate());
14864 if (operand.IsRegister()) {
14865 QRegister rm = operand.GetRegister();
14884 Delegate(kVbic, &Assembler::vbic, cond, dt, rd, rn, operand);
15035 const DOperand& operand) {
15038 if (operand.IsImmediate()) {
15039 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
15040 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
15068 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);
15075 const QOperand& operand) {
15078 if (operand.IsImmediate()) {
15079 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
15080 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
15108 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);
15207 const DOperand& operand) {
15210 if (operand.IsImmediate()) {
15211 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
15212 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
15240 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand);
15247 const QOperand& operand) {
15250 if (operand.IsImmediate()) {
15251 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
15252 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
15280 Delegate(kVcge, &Assembler::vcge, cond, dt, rd, rm, operand);
15381 const DOperand& operand) {
15384 if (operand.IsImmediate()) {
15385 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
15386 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
15414 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand);
15421 const QOperand& operand) {
15424 if (operand.IsImmediate()) {
15425 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
15426 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
15454 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand);
15555 const DOperand& operand) {
15558 if (operand.IsImmediate()) {
15559 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
15560 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
15588 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);
15595 const QOperand& operand) {
15598 if (operand.IsImmediate()) {
15599 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
15600 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
15628 Delegate(kVcle, &Assembler::vcle, cond, dt, rd, rm, operand);
15783 const DOperand& operand) {
15786 if (operand.IsImmediate()) {
15787 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
15788 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
15816 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rm, operand);
15823 const QOperand& operand) {
15826 if (operand.IsImmediate()) {
15827 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
15828 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
15856 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rm, operand);
16010 const SOperand& operand) {
16013 if (operand.IsRegister()) {
16014 SRegister rm = operand.GetRegister();
16031 if (operand.IsImmediate()) {
16034 if (dt.Is(F32) && (operand.IsFloatZero())) {
16041 if (dt.Is(F32) && (operand.IsFloatZero()) && cond.IsNotNever()) {
16047 Delegate(kVcmp, &Assembler::vcmp, cond, dt, rd, operand);
16053 const DOperand& operand) {
16056 if (operand.IsRegister()) {
16057 DRegister rm = operand.GetRegister();
16074 if (operand.IsImmediate()) {
16077 if (dt.Is(F64) && (operand.IsFloatZero())) {
16084 if (dt.Is(F64) && (operand.IsFloatZero()) && cond.IsNotNever()) {
16090 Delegate(kVcmp, &Assembler::vcmp, cond, dt, rd, operand);
16096 const SOperand& operand) {
16099 if (operand.IsRegister()) {
16100 SRegister rm = operand.GetRegister();
16117 if (operand.IsImmediate()) {
16120 if (dt.Is(F32) && (operand.IsFloatZero())) {
16127 if (dt.Is(F32) && (operand.IsFloatZero()) && cond.IsNotNever()) {
16133 Delegate(kVcmpe, &Assembler::vcmpe, cond, dt, rd, operand);
16139 const DOperand& operand) {
16142 if (operand.IsRegister()) {
16143 DRegister rm = operand.GetRegister();
16160 if (operand.IsImmediate()) {
16163 if (dt.Is(F64) && (operand.IsFloatZero())) {
16170 if (dt.Is(F64) && (operand.IsFloatZero()) && cond.IsNotNever()) {
16176 Delegate(kVcmpe, &Assembler::vcmpe, cond, dt, rd, operand);
17500 const DOperand& operand) {
17503 if (operand.IsImmediate()) {
17504 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
17505 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
17549 Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);
17557 const QOperand& operand) {
17560 if (operand.IsImmediate()) {
17561 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
17562 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
17606 Delegate(kVext, &Assembler::vext, cond, dt, rd, rn, rm, operand);
18004 const AlignedMemOperand& operand) {
18007 if (operand.IsImmediateZero()) {
18008 Register rn = operand.GetBaseRegister();
18009 Alignment align = operand.GetAlignment();
18019 operand.IsOffset() && encoded_align_1.IsValid() &&
18051 operand.IsPostIndex() && encoded_align_1.IsValid() &&
18083 operand.IsOffset() && encoded_align_2.IsValid() &&
18099 operand.IsPostIndex() && encoded_align_2.IsValid() &&
18114 (nreglist.GetLength() == 1) && operand.IsOffset() &&
18127 (nreglist.GetLength() == 1) && operand.IsPostIndex() &&
18142 operand.IsOffset() && encoded_align_1.IsValid() &&
18173 operand.IsPostIndex() && encoded_align_1.IsValid() &&
18204 operand.IsOffset() && encoded_align_2.IsValid() &&
18219 operand.IsPostIndex() && encoded_align_2.IsValid() &&
18233 (nreglist.GetLength() == 1) && operand.IsOffset() &&
18245 (nreglist.GetLength() == 1) && operand.IsPostIndex() &&
18257 if (operand.IsPlainRegister()) {
18258 Register rn = operand.GetBaseRegister();
18259 Alignment align = operand.GetAlignment();
18260 Register rm = operand.GetOffsetRegister();
18386 Delegate(kVld1, &Assembler::vld1, cond, dt, nreglist, operand);
18392 const AlignedMemOperand& operand) {
18395 if (operand.IsImmediateZero()) {
18396 Register rn = operand.GetBaseRegister();
18397 Alignment align = operand.GetAlignment();
18408 operand.IsOffset() && encoded_align_1.IsValid() &&
18435 operand.IsPostIndex() && encoded_align_1.IsValid() &&
18461 operand.IsOffset() && encoded_align_2.IsValid() &&
18478 operand.IsPostIndex() && encoded_align_2.IsValid() &&
18495 operand.IsOffset() && encoded_align_3.IsValid() &&
18510 operand.IsPostIndex() && encoded_align_3.IsValid() &&
18527 operand.IsOffset() && encoded_align_1.IsValid() &&
18553 operand.IsPostIndex() && encoded_align_1.IsValid() &&
18578 operand.IsOffset() && encoded_align_2.IsValid() &&
18594 operand.IsPostIndex() && encoded_align_2.IsValid() &&
18610 operand.IsOffset() && encoded_align_3.IsValid() &&
18624 operand.IsPostIndex() && encoded_align_3.IsValid() &&
18636 if (operand.IsPlainRegister()) {
18637 Register rn = operand.GetBaseRegister();
18638 Alignment align = operand.GetAlignment();
18639 Register rm = operand.GetOffsetRegister();
18758 Delegate(kVld2, &Assembler::vld2, cond, dt, nreglist, operand);
18764 const AlignedMemOperand& operand) {
18767 if (operand.IsImmediateZero()) {
18768 Register rn = operand.GetBaseRegister();
18769 Alignment align = operand.GetAlignment();
18777 operand.IsOffset() && encoded_align_1.IsValid() &&
18794 operand.IsPostIndex() && encoded_align_1.IsValid() &&
18812 operand.IsOffset() && encoded_align_1.IsValid() &&
18828 operand.IsPostIndex() && encoded_align_1.IsValid() &&
18842 if (operand.IsPlainRegister()) {
18843 Register rn = operand.GetBaseRegister();
18844 Alignment align = operand.GetAlignment();
18845 Register rm = operand.GetOffsetRegister();
18883 Delegate(kVld3, &Assembler::vld3, cond, dt, nreglist, operand);
18889 const MemOperand& operand) {
18892 if (operand.IsImmediateZero()) {
18893 Register rn = operand.GetBaseRegister();
18901 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
18916 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
18931 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
18945 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
18960 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
18974 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
18988 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
19001 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
19012 if (operand.IsPlainRegister()) {
19013 Register rn = operand.GetBaseRegister();
19014 Sign sign = operand.GetSign();
19015 Register rm = operand.GetOffsetRegister();
19023 sign.IsPlus() && operand.IsPostIndex() &&
19039 sign.IsPlus() && operand.IsPostIndex() &&
19056 sign.IsPlus() && operand.IsPostIndex() &&
19071 sign.IsPlus() && operand.IsPostIndex() &&
19083 Delegate(kVld3, &Assembler::vld3, cond, dt, nreglist, operand);
19089 const AlignedMemOperand& operand) {
19092 if (operand.IsImmediateZero()) {
19093 Register rn = operand.GetBaseRegister();
19094 Alignment align = operand.GetAlignment();
19105 operand.IsOffset() && encoded_align_1.IsValid() &&
19122 operand.IsPostIndex() && encoded_align_1.IsValid() &&
19139 operand.IsOffset() && encoded_align_2.IsValid() &&
19156 operand.IsPostIndex() && encoded_align_2.IsValid() &&
19173 operand.IsOffset() && encoded_align_3.IsValid() &&
19188 operand.IsPostIndex() && encoded_align_3.IsValid() &&
19204 operand.IsOffset() && encoded_align_1.IsValid() &&
19220 operand.IsPostIndex() && encoded_align_1.IsValid() &&
19236 operand.IsOffset() && encoded_align_2.IsValid() &&
19252 operand.IsPostIndex() && encoded_align_2.IsValid() &&
19268 operand.IsOffset() && encoded_align_3.IsValid() &&
19282 operand.IsPostIndex() && encoded_align_3.IsValid() &&
19294 if (operand.IsPlainRegister()) {
19295 Register rn = operand.GetBaseRegister();
19296 Alignment align = operand.GetAlignment();
19297 Register rm = operand.GetOffsetRegister();
19397 Delegate(kVld4, &Assembler::vld4, cond, dt, nreglist, operand);
19708 const MemOperand& operand) {
19711 if (operand.IsImmediate()) {
19712 Register rn = operand.GetBaseRegister();
19713 int32_t offset = operand.GetOffsetImmediate();
19717 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset()) {
19718 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
19726 ((offset % 4) == 0) && operand.IsOffset() &&
19728 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
19738 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset() &&
19740 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
19748 ((offset % 4) == 0) && operand.IsOffset() && cond.IsNotNever() &&
19750 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
19758 Delegate(kVldr, &Assembler::vldr, cond, dt, rd, operand);
19862 const MemOperand& operand) {
19865 if (operand.IsImmediate()) {
19866 Register rn = operand.GetBaseRegister();
19867 int32_t offset = operand.GetOffsetImmediate();
19871 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset()) {
19872 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
19880 ((offset % 4) == 0) && operand.IsOffset() &&
19882 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
19892 ((offset % 4) == 0) && rn.Is(pc) && operand.IsOffset() &&
19894 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
19902 ((offset % 4) == 0) && operand.IsOffset() && cond.IsNotNever() &&
19904 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
19912 Delegate(kVldr, &Assembler::vldr, cond, dt, rd, operand);
20962 const DOperand& operand) {
20965 if (operand.IsImmediate()) {
20966 ImmediateVmov encoded_dt(dt, operand.GetNeonImmediate());
20995 if (operand.IsImmediate()) {
20996 ImmediateVFP vfp(operand.GetNeonImmediate());
21016 if (operand.IsRegister()) {
21017 DRegister rm = operand.GetRegister();
21051 Delegate(kVmov, &Assembler::vmov, cond, dt, rd, operand);
21057 const QOperand& operand) {
21060 if (operand.IsImmediate()) {
21061 ImmediateVmov encoded_dt(dt, operand.GetNeonImmediate());
21090 if (operand.IsRegister()) {
21091 QRegister rm = operand.GetRegister();
21113 Delegate(kVmov, &Assembler::vmov, cond, dt, rd, operand);
21119 const SOperand& operand) {
21122 if (operand.IsImmediate()) {
21123 ImmediateVFP vfp(operand.GetNeonImmediate());
21143 if (operand.IsRegister()) {
21144 SRegister rm = operand.GetRegister();
21161 Delegate(kVmov, &Assembler::vmov, cond, dt, rd, operand);
21612 const DOperand& operand) {
21615 if (operand.IsImmediate()) {
21616 ImmediateVmvn encoded_dt(dt, operand.GetNeonImmediate());
21643 if (operand.IsRegister()) {
21644 DRegister rm = operand.GetRegister();
21661 Delegate(kVmvn, &Assembler::vmvn, cond, dt, rd, operand);
21667 const QOperand& operand) {
21670 if (operand.IsImmediate()) {
21671 ImmediateVmvn encoded_dt(dt, operand.GetNeonImmediate());
21698 if (operand.IsRegister()) {
21699 QRegister rm = operand.GetRegister();
21716 Delegate(kVmvn, &Assembler::vmvn, cond, dt, rd, operand);
21952 const DOperand& operand) {
21955 if (operand.IsImmediate()) {
21956 ImmediateVorn encoded_dt(dt, operand.GetNeonImmediate());
21983 if (operand.IsRegister()) {
21984 DRegister rm = operand.GetRegister();
22003 Delegate(kVorn, &Assembler::vorn, cond, dt, rd, rn, operand);
22010 const QOperand& operand) {
22013 if (operand.IsImmediate()) {
22014 ImmediateVorn encoded_dt(dt, operand.GetNeonImmediate());
22041 if (operand.IsRegister()) {
22042 QRegister rm = operand.GetRegister();
22061 Delegate(kVorn, &Assembler::vorn, cond, dt, rd, rn, operand);
22068 const DOperand& operand) {
22071 if (operand.IsRegister()) {
22072 DRegister rm = operand.GetRegister();
22091 if (operand.IsImmediate()) {
22092 ImmediateVorr encoded_dt(dt, operand.GetNeonImmediate());
22119 Delegate(kVorr, &Assembler::vorr, cond, dt, rd, rn, operand);
22126 const QOperand& operand) {
22129 if (operand.IsRegister()) {
22130 QRegister rm = operand.GetRegister();
22149 if (operand.IsImmediate()) {
22150 ImmediateVorr encoded_dt(dt, operand.GetNeonImmediate());
22177 Delegate(kVorr, &Assembler::vorr, cond, dt, rd, rn, operand);
23319 const QOperand& operand) {
23322 if (operand.IsImmediate()) {
23323 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
23324 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
23375 Delegate(kVqrshrn, &Assembler::vqrshrn, cond, dt, rd, rm, operand);
23382 const QOperand& operand) {
23385 if (operand.IsImmediate()) {
23386 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
23387 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
23433 Delegate(kVqrshrun, &Assembler::vqrshrun, cond, dt, rd, rm, operand);
23440 const DOperand& operand) {
23443 if (operand.IsRegister()) {
23444 DRegister rn = operand.GetRegister();
23470 if (operand.IsImmediate()) {
23471 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
23472 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
23502 Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand);
23509 const QOperand& operand) {
23512 if (operand.IsRegister()) {
23513 QRegister rn = operand.GetRegister();
23539 if (operand.IsImmediate()) {
23540 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
23541 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
23571 Delegate(kVqshl, &Assembler::vqshl, cond, dt, rd, rm, operand);
23578 const DOperand& operand) {
23581 if (operand.IsImmediate()) {
23582 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
23583 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
23613 Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);
23620 const QOperand& operand) {
23623 if (operand.IsImmediate()) {
23624 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
23625 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
23655 Delegate(kVqshlu, &Assembler::vqshlu, cond, dt, rd, rm, operand);
23662 const QOperand& operand) {
23665 if (operand.IsImmediate()) {
23666 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
23667 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
23718 Delegate(kVqshrn, &Assembler::vqshrn, cond, dt, rd, rm, operand);
23725 const QOperand& operand) {
23728 if (operand.IsImmediate()) {
23729 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
23730 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
23776 Delegate(kVqshrun, &Assembler::vqshrun, cond, dt, rd, rm, operand);
24815 const DOperand& operand) {
24818 if (operand.IsImmediate()) {
24819 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
24820 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
24867 Delegate(kVrshr, &Assembler::vrshr, cond, dt, rd, rm, operand);
24874 const QOperand& operand) {
24877 if (operand.IsImmediate()) {
24878 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
24879 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
24926 Delegate(kVrshr, &Assembler::vrshr, cond, dt, rd, rm, operand);
24933 const QOperand& operand) {
24936 if (operand.IsImmediate()) {
24937 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
24938 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
24984 Delegate(kVrshrn, &Assembler::vrshrn, cond, dt, rd, rm, operand);
25109 const DOperand& operand) {
25112 if (operand.IsImmediate()) {
25113 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25114 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25144 Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand);
25151 const QOperand& operand) {
25154 if (operand.IsImmediate()) {
25155 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25156 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25186 Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand);
25397 const DOperand& operand) {
25400 if (operand.IsImmediate()) {
25401 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25402 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25432 if (operand.IsRegister()) {
25433 DRegister rn = operand.GetRegister();
25459 Delegate(kVshl, &Assembler::vshl, cond, dt, rd, rm, operand);
25466 const QOperand& operand) {
25469 if (operand.IsImmediate()) {
25470 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25471 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25501 if (operand.IsRegister()) {
25502 QRegister rn = operand.GetRegister();
25528 Delegate(kVshl, &Assembler::vshl, cond, dt, rd, rm, operand);
25535 const DOperand& operand) {
25538 if (operand.IsImmediate()) {
25539 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25540 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25586 Delegate(kVshll, &Assembler::vshll, cond, dt, rd, rm, operand);
25593 const DOperand& operand) {
25596 if (operand.IsImmediate()) {
25597 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25598 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25645 Delegate(kVshr, &Assembler::vshr, cond, dt, rd, rm, operand);
25652 const QOperand& operand) {
25655 if (operand.IsImmediate()) {
25656 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25657 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25704 Delegate(kVshr, &Assembler::vshr, cond, dt, rd, rm, operand);
25711 const QOperand& operand) {
25714 if (operand.IsImmediate()) {
25715 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25716 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25762 Delegate(kVshrn, &Assembler::vshrn, cond, dt, rd, rm, operand);
25769 const DOperand& operand) {
25772 if (operand.IsImmediate()) {
25773 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25774 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25804 Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand);
25811 const QOperand& operand) {
25814 if (operand.IsImmediate()) {
25815 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25816 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25846 Delegate(kVsli, &Assembler::vsli, cond, dt, rd, rm, operand);
25895 const DOperand& operand) {
25898 if (operand.IsImmediate()) {
25899 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25900 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25930 Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand);
25937 const QOperand& operand) {
25940 if (operand.IsImmediate()) {
25941 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25942 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
25972 Delegate(kVsra, &Assembler::vsra, cond, dt, rd, rm, operand);
25979 const DOperand& operand) {
25982 if (operand.IsImmediate()) {
25983 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
25984 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
26014 Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand);
26021 const QOperand& operand) {
26024 if (operand.IsImmediate()) {
26025 if (operand.GetNeonImmediate().CanConvert<uint32_t>()) {
26026 uint32_t imm = operand.GetNeonImmediate().GetImmediate<uint32_t>();
26056 Delegate(kVsri, &Assembler::vsri, cond, dt, rd, rm, operand);
26062 const AlignedMemOperand& operand) {
26065 if (operand.IsImmediateZero()) {
26066 Register rn = operand.GetBaseRegister();
26067 Alignment align = operand.GetAlignment();
26076 operand.IsOffset() && encoded_align_1.IsValid() &&
26108 operand.IsPostIndex() && encoded_align_1.IsValid() &&
26139 (nreglist.GetLength() == 1) && operand.IsOffset() &&
26152 (nreglist.GetLength() == 1) && operand.IsPostIndex() &&
26167 operand.IsOffset() && encoded_align_1.IsValid() &&
26198 operand.IsPostIndex() && encoded_align_1.IsValid() &&
26228 (nreglist.GetLength() == 1) && operand.IsOffset() &&
26240 (nreglist.GetLength() == 1) && operand.IsPostIndex() &&
26252 if (operand.IsPlainRegister()) {
26253 Register rn = operand.GetBaseRegister();
26254 Alignment align = operand.GetAlignment();
26255 Register rm = operand.GetOffsetRegister();
26351 Delegate(kVst1, &Assembler::vst1, cond, dt, nreglist, operand);
26357 const AlignedMemOperand& operand) {
26360 if (operand.IsImmediateZero()) {
26361 Register rn = operand.GetBaseRegister();
26362 Alignment align = operand.GetAlignment();
26372 operand.IsOffset() && encoded_align_1.IsValid() &&
26399 operand.IsPostIndex() && encoded_align_1.IsValid() &&
26425 operand.IsOffset() && encoded_align_2.IsValid() &&
26440 operand.IsPostIndex() && encoded_align_2.IsValid() &&
26457 operand.IsOffset() && encoded_align_1.IsValid() &&
26483 operand.IsPostIndex() && encoded_align_1.IsValid() &&
26508 operand.IsOffset() && encoded_align_2.IsValid() &&
26522 operand.IsPostIndex() && encoded_align_2.IsValid() &&
26534 if (operand.IsPlainRegister()) {
26535 Register rn = operand.GetBaseRegister();
26536 Alignment align = operand.GetAlignment();
26537 Register rm = operand.GetOffsetRegister();
26624 Delegate(kVst2, &Assembler::vst2, cond, dt, nreglist, operand);
26630 const AlignedMemOperand& operand) {
26633 if (operand.IsImmediateZero()) {
26634 Register rn = operand.GetBaseRegister();
26635 Alignment align = operand.GetAlignment();
26643 operand.IsOffset() && encoded_align_1.IsValid() &&
26660 operand.IsPostIndex() && encoded_align_1.IsValid() &&
26678 operand.IsOffset() && encoded_align_1.IsValid() &&
26694 operand.IsPostIndex() && encoded_align_1.IsValid() &&
26708 if (operand.IsPlainRegister()) {
26709 Register rn = operand.GetBaseRegister();
26710 Alignment align = operand.GetAlignment();
26711 Register rm = operand.GetOffsetRegister();
26749 Delegate(kVst3, &Assembler::vst3, cond, dt, nreglist, operand);
26755 const MemOperand& operand) {
26758 if (operand.IsImmediateZero()) {
26759 Register rn = operand.GetBaseRegister();
26767 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
26781 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
26796 operand.IsOffset() && (!rn.IsPC() || AllowUnpredictable())) {
26809 operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
26820 if (operand.IsPlainRegister()) {
26821 Register rn = operand.GetBaseRegister();
26822 Sign sign = operand.GetSign();
26823 Register rm = operand.GetOffsetRegister();
26831 sign.IsPlus() && operand.IsPostIndex() &&
26848 sign.IsPlus() && operand.IsPostIndex() &&
26860 Delegate(kVst3, &Assembler::vst3, cond, dt, nreglist, operand);
26866 const AlignedMemOperand& operand) {
26869 if (operand.IsImmediateZero()) {
26870 Register rn = operand.GetBaseRegister();
26871 Alignment align = operand.GetAlignment();
26880 operand.IsOffset() && encoded_align_1.IsValid() &&
26897 operand.IsPostIndex() && encoded_align_1.IsValid() &&
26914 operand.IsOffset() && encoded_align_2.IsValid() &&
26929 operand.IsPostIndex() && encoded_align_2.IsValid() &&
26945 operand.IsOffset() && encoded_align_1.IsValid() &&
26961 operand.IsPostIndex() && encoded_align_1.IsValid() &&
26977 operand.IsOffset() && encoded_align_2.IsValid() &&
26991 operand.IsPostIndex() && encoded_align_2.IsValid() &&
27003 if (operand.IsPlainRegister()) {
27004 Register rn = operand.GetBaseRegister();
27005 Alignment align = operand.GetAlignment();
27006 Register rm = operand.GetOffsetRegister();
27073 Delegate(kVst4, &Assembler::vst4, cond, dt, nreglist, operand);
27286 const MemOperand& operand) {
27289 if (operand.IsImmediate()) {
27290 Register rn = operand.GetBaseRegister();
27291 int32_t offset = operand.GetOffsetImmediate();
27295 ((offset % 4) == 0) && operand.IsOffset() &&
27297 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
27307 ((offset % 4) == 0) && operand.IsOffset() && cond.IsNotNever()) {
27308 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
27316 Delegate(kVstr, &Assembler::vstr, cond, dt, rd, operand);
27322 const MemOperand& operand) {
27325 if (operand.IsImmediate()) {
27326 Register rn = operand.GetBaseRegister();
27327 int32_t offset = operand.GetOffsetImmediate();
27331 ((offset % 4) == 0) && operand.IsOffset() &&
27333 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
27343 ((offset % 4) == 0) && operand.IsOffset() && cond.IsNotNever()) {
27344 uint32_t sign = operand.GetSign().IsPlus() ? 1 : 0;
27352 Delegate(kVstr, &Assembler::vstr, cond, dt, rd, operand);