Lines Matching defs:iAddr
18361 int iAddr; /* Subroutine entry address */
32060 pExpr->y.sub.regReturn, pExpr->y.sub.iAddr);
70250 int iAddr = hdr + 1; /* Address of ptr to pc */
70251 u8 *pTmp = &aData[iAddr]; /* Temporary ptr into aData[] */
70274 memcpy(&aData[iAddr], &aData[pc], 2);
70288 iAddr = pc;
70291 if( pc<=iAddr ){
83172 int iAddr; /* Address of next instruction to return */
83190 assert( p->iAddr<nOp );
83192 pRet = &aOp[p->iAddr];
83193 p->iAddr++;
83194 if( p->iAddr==nOp ){
83196 p->iAddr = 0;
92635 int iAddr;
92636 for(iAddr = (int)(pOp - aOp) - 1; ALWAYS(iAddr>=0); iAddr--){
92637 if( aOp[iAddr].opcode==OP_ReleaseReg ) continue;
92638 assert( aOp[iAddr].opcode==OP_Lt || aOp[iAddr].opcode==OP_Gt );
92908 u32 iAddr; /* Address of this instruction */
92911 iAddr = (int)(pOp - p->aOp);
92912 if( (p->pFrame->aOnce[iAddr/8] & (1<<(iAddr & 7)))!=0 ){
92916 p->pFrame->aOnce[iAddr/8] |= 1<<(iAddr & 7);
102581 int iAddr; /* Address */
102716 &pCur->iAddr,
102745 Op *pOp = pCur->aOp + pCur->iAddr;
102781 sqlite3_result_int(ctx, pCur->iAddr);
102817 if( pCur->iRowid==pCur->iAddr+1 ){
102869 pCur->iAddr = 0;
108611 int iAddr = sqlite3VdbeAddOp0(v, OP_Once);
108618 sqlite3VdbeJumpHere(v, iAddr);
108696 int iAddr = sqlite3VdbeAddOp0(v, OP_Once); VdbeCoverage(v);
108716 sqlite3VdbeJumpHere(v, iAddr);
108902 pExpr->y.sub.iAddr);
108914 pExpr->y.sub.iAddr =
109039 assert( sqlite3VdbeGetOp(v,pExpr->y.sub.iAddr-1)->opcode==OP_BeginSubrtn
109042 pExpr->y.sub.iAddr, 1);
109087 pExpr->y.sub.iAddr);
109096 pExpr->y.sub.iAddr =
109170 assert( sqlite3VdbeGetOp(v,pExpr->y.sub.iAddr-1)->opcode==OP_BeginSubrtn
109173 pExpr->y.sub.iAddr, 1);
109573 int iAddr;
109578 iAddr = sqlite3VdbeAddOp3(v, OP_IfNullRow, pParse->iSelfTab-1, 0, regOut);
109580 iAddr = 0;
109586 if( iAddr ) sqlite3VdbeJumpHere(v, iAddr);
135041 int iAddr = sqlite3VdbeCurrentAddr(v);
135047 aOp[2].p2 = iAddr+4;