Lines Matching refs:NA
502 if (arg != NA) { live[arg] = true; }
533 std::vector<Val> new_id(program.size(), NA);
538 if (*arg != NA) {
540 SkASSERT(*arg != NA);
571 if (arg != NA) { optimized[arg].death = id; }
585 if (arg != NA) { inst.can_hoist &= optimized[arg].can_hoist; }
594 if (arg != NA && optimized[arg].can_hoist) {
680 (void)push(Op::trace_line, mask.id,NA,NA,NA, line);
684 (void)push(Op::trace_var, mask.id,val.id,NA,NA, slot, kVarTypeInt.bits);
688 (void)push(Op::trace_var, mask.id,val.id,NA,NA, slot, kVarTypeFloat.bits);
693 (void)push(Op::trace_var, mask.id,val.id,NA,NA, slot, kVarTypeBool.bits);
697 (void)push(Op::trace_call, mask.id,NA,NA,NA, line, kCallTypeEnter.bits);
701 (void)push(Op::trace_call, mask.id,NA,NA,NA, line, kCallTypeExit.bits);
704 void Builder::store8 (Ptr ptr, I32 val) { (void)push(Op::store8 , val.id,NA,NA,NA, ptr.ix); }
705 void Builder::store16(Ptr ptr, I32 val) { (void)push(Op::store16, val.id,NA,NA,NA, ptr.ix); }
706 void Builder::store32(Ptr ptr, I32 val) { (void)push(Op::store32, val.id,NA,NA,NA, ptr.ix); }
708 (void)push(Op::store64, lo.id,hi.id,NA,NA, ptr.ix);
716 I32 Builder::load8 (Ptr ptr) { return {this, push(Op::load8 , NA,NA,NA,NA, ptr.ix) }; }
717 I32 Builder::load16(Ptr ptr) { return {this, push(Op::load16, NA,NA,NA,NA, ptr.ix) }; }
718 I32 Builder::load32(Ptr ptr) { return {this, push(Op::load32, NA,NA,NA,NA, ptr.ix) }; }
720 return {this, push(Op::load64 , NA,NA,NA,NA, ptr.ix,lane) };
723 return {this, push(Op::load128, NA,NA,NA,NA, ptr.ix,lane) };
727 return {this, push(Op::gather8 , index.id,NA,NA,NA, ptr.ix,offset)};
730 return {this, push(Op::gather16, index.id,NA,NA,NA, ptr.ix,offset)};
733 return {this, push(Op::gather32, index.id,NA,NA,NA, ptr.ix,offset)};
737 return {this, push(Op::uniform32, NA,NA,NA,NA, ptr.ix, offset)};
742 return {this, push(Op::array32, NA,NA,NA,NA, ptr.ix, offset, index * sizeof(int))};
745 I32 Builder::splat(int n) { return {this, push(Op::splat, NA,NA,NA,NA, n) }; }
1009 return {this, this->push(Op::shl_i32, x.id,NA,NA,NA, bits)};
1014 return {this, this->push(Op::shr_i32, x.id,NA,NA,NA, bits)};
1019 return {this, this->push(Op::sra_i32, x.id,NA,NA,NA, bits)};
3130 if (input != NA && instructions[input].death == id) {
3172 return id == NA ? (Reg)0
3228 // - NA: empty
3232 constexpr Val RES = NA-1,
3236 std::vector<int> stack_slot(instructions.size(), NA);
3254 NA, NA, NA, NA, NA, NA,RES,RES,
3292 regs[r] = NA;
3329 NA,NA,NA,NA, NA,NA,NA,NA,
3330 NA,NA,NA,NA, NA,NA,NA,NA,
3355 SkASSERT(stack_slot[v] != NA);
3373 NA, NA, NA, NA, NA, NA, NA, NA,
3375 NA, NA, NA, NA, NA, NA, NA, NA,
3376 NA, NA, NA, NA, NA, NA, NA, NA,
3391 SkASSERT(stack_slot[v] != NA);
3424 SkASSERT(v >= 0); // {NA,TMP,RES} need to be handled before calling this.
3425 return stack_slot[v] == NA // We haven't spilled it already?
3436 // Registers holding NA (nothing) are ideal, nothing to spill.
3437 if (v == NA) {
3473 SkASSERT(v == NA || v >= 0);
3488 regs[r] = NA;
3491 // Which register holds dst,x,y,z,w for this instruction? NA if none does yet.
3492 int rd = NA,
3493 rx = NA,
3494 ry = NA,
3495 rz = NA,
3496 rw = NA;
3509 if (v == id && rd != NA) { return rd; }
3510 if (v == x && rx != NA) { return rx; }
3511 if (v == y && ry != NA) { return ry; }
3512 if (v == z && rz != NA) { return rz; }
3513 if (v == w && rw != NA) { return rw; }
3521 return NA;
3529 if (int found = find_existing_reg(v); found != NA) {
3564 auto dst = [&](Val hint1 = NA, Val hint2 = NA) -> Reg {
3565 if (hint1 != NA && try_alias(hint1)) { return r(id); }
3566 if (hint2 != NA && try_alias(hint2)) { return r(id); }
3585 if (int found = find_existing_reg(v); found != NA) {
3597 return find_existing_reg(v) != NA;
4239 if (rd != NA && dies_here(regs[rd])) { regs[rd] = NA; }
4240 if (rx != NA && regs[rx] != NA && dies_here(regs[rx])) { regs[rx] = NA; }
4241 if (ry != NA && regs[ry] != NA && dies_here(regs[ry])) { regs[ry] = NA; }
4242 if (rz != NA && regs[rz] != NA && dies_here(regs[rz])) { regs[rz] = NA; }
4243 if (rw != NA && regs[rw] != NA && dies_here(regs[rw])) { regs[rw] = NA; }