Lines Matching refs:CTR
27 # | CTR block 4k+8 | AES block 4k+4 | GHASH block 4k+0 |
30 # | CTR block 4k+9 | AES block 4k+5 | GHASH block 4k+1 |
33 # | CTR block 4k+10| AES block 4k+6 | GHASH block 4k+2 |
36 # | CTR block 4k+11| AES block 4k+7 | GHASH block 4k+3 |
47 # CTR block:
56 # Do AES encryption/decryption on CTR block X and EOR it with input block X. Take 256 bytes key below for example.
296 fmov $ctr1d, $ctr96_b64x @ CTR block 1
303 rev $ctr32w, $rctr32w @ CTR block 1
304 add $rctr32w, $rctr32w, #1 @ CTR block 1
305 fmov $ctr3d, $ctr96_b64x @ CTR block 3
307 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 1
310 fmov $ctr1.d[1], $ctr32x @ CTR block 1
311 rev $ctr32w, $rctr32w @ CTR block 2
313 fmov $ctr2d, $ctr96_b64x @ CTR block 2
314 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 2
315 add $rctr32w, $rctr32w, #1 @ CTR block 2
317 fmov $ctr2.d[1], $ctr32x @ CTR block 2
318 rev $ctr32w, $rctr32w @ CTR block 3
320 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 3
323 add $rctr32w, $rctr32w, #1 @ CTR block 3
324 fmov $ctr3.d[1], $ctr32x @ CTR block 3
475 rev $ctr32w, $rctr32w @ CTR block 4
478 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4
481 fmov $ctr0d, $ctr96_b64x @ CTR block 4
482 add $rctr32w, $rctr32w, #1 @ CTR block 4
484 fmov $ctr0.d[1], $ctr32x @ CTR block 4
485 rev $ctr32w, $rctr32w @ CTR block 5
488 fmov $ctr1d, $ctr96_b64x @ CTR block 5
489 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 5
491 add $rctr32w, $rctr32w, #1 @ CTR block 5
493 fmov $ctr1.d[1], $ctr32x @ CTR block 5
496 rev $ctr32w, $rctr32w @ CTR block 6
500 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 6
502 add $rctr32w, $rctr32w, #1 @ CTR block 6
506 fmov $ctr2d, $ctr96_b64x @ CTR block 6
509 fmov $ctr2.d[1], $ctr32x @ CTR block 6
510 rev $ctr32w, $rctr32w @ CTR block 7
513 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 7
529 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+3
535 add $rctr32w, $rctr32w, #1 @ CTR block 4k+3
536 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+3
558 rev $ctr32w, $rctr32w @ CTR block 4k+8
562 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+8
565 add $rctr32w, $rctr32w, #1 @ CTR block 4k+8
696 fmov $ctr0d, $ctr96_b64x @ CTR block 4k+8
699 fmov $ctr0.d[1], $ctr32x @ CTR block 4k+8
700 rev $ctr32w, $rctr32w @ CTR block 4k+9
706 add $rctr32w, $rctr32w, #1 @ CTR block 4k+9
707 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+9
708 fmov $ctr1d, $ctr96_b64x @ CTR block 4k+9
711 fmov $ctr1.d[1], $ctr32x @ CTR block 4k+9
712 rev $ctr32w, $rctr32w @ CTR block 4k+10
717 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+10
720 add $rctr32w, $rctr32w, #1 @ CTR block 4k+10
722 fmov $ctr2d, $ctr96_b64x @ CTR block 4k+10
727 fmov $ctr2.d[1], $ctr32x @ CTR block 4k+10
729 rev $ctr32w, $rctr32w @ CTR block 4k+11
731 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+11
740 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+3
744 add $rctr32w, $rctr32w, #1 @ CTR block 4k+3
745 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+3
1179 fmov $ctr2d, $ctr96_b64x @ CTR block 2
1185 fmov $ctr1d, $ctr96_b64x @ CTR block 1
1189 rev $ctr32w, $rctr32w @ CTR block 1
1191 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 1
1193 add $rctr32w, $rctr32w, #1 @ CTR block 1
1195 fmov $ctr1.d[1], $ctr32x @ CTR block 1
1196 rev $ctr32w, $rctr32w @ CTR block 2
1197 add $rctr32w, $rctr32w, #1 @ CTR block 2
1200 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 2
1202 fmov $ctr2.d[1], $ctr32x @ CTR block 2
1203 rev $ctr32w, $rctr32w @ CTR block 3
1205 fmov $ctr3d, $ctr96_b64x @ CTR block 3
1206 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 3
1207 add $rctr32w, $rctr32w, #1 @ CTR block 3
1209 fmov $ctr3.d[1], $ctr32x @ CTR block 3
1325 rev $ctr32w, $rctr32w @ CTR block 4
1327 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4
1328 add $rctr32w, $rctr32w, #1 @ CTR block 4
1341 fmov $ctr0d, $ctr96_b64x @ CTR block 4
1343 fmov $ctr0.d[1], $ctr32x @ CTR block 4
1344 rev $ctr32w, $rctr32w @ CTR block 5
1349 fmov $ctr1d, $ctr96_b64x @ CTR block 5
1350 add $rctr32w, $rctr32w, #1 @ CTR block 5
1351 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 5
1353 fmov $ctr1.d[1], $ctr32x @ CTR block 5
1354 rev $ctr32w, $rctr32w @ CTR block 6
1355 add $rctr32w, $rctr32w, #1 @ CTR block 6
1357 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 6
1387 fmov $ctr2d, $ctr96_b64x @ CTR block 4k+6
1390 fmov $ctr2.d[1], $ctr32x @ CTR block 4k+6
1391 rev $ctr32w, $rctr32w @ CTR block 4k+7
1402 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+7
1405 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+7
1409 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+7
1500 add $rctr32w, $rctr32w, #1 @ CTR block 4k+7
1515 rev $ctr32w, $rctr32w @ CTR block 4k+8
1522 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+8
1535 add $rctr32w, $rctr32w, #1 @ CTR block 4k+8
1552 fmov $ctr0d, $ctr96_b64x @ CTR block 4k+8
1555 fmov $ctr0.d[1], $ctr32x @ CTR block 4k+8
1556 rev $ctr32w, $rctr32w @ CTR block 4k+9
1559 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+9
1575 add $rctr32w, $rctr32w, #1 @ CTR block 4k+9
1578 fmov $ctr1d, $ctr96_b64x @ CTR block 4k+9
1583 fmov $ctr1.d[1], $ctr32x @ CTR block 4k+9
1585 rev $ctr32w, $rctr32w @ CTR block 4k+10
1586 add $rctr32w, $rctr32w, #1 @ CTR block 4k+10
1600 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+10
1615 fmov $ctr2d, $ctr96_b64x @ CTR block 4k+6
1619 fmov $ctr2.d[1], $ctr32x @ CTR block 4k+6
1621 rev $ctr32w, $rctr32w @ CTR block 4k+7
1633 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+7
1637 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+7
1640 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+7
1773 add $rctr32w, $rctr32w, #1 @ CTR block 4k+7
2137 fmov $ctr3d, $ctr96_b64x @ CTR block 3
2139 rev $ctr32w, $rctr32w @ CTR block 1
2140 add $rctr32w, $rctr32w, #1 @ CTR block 1
2141 fmov $ctr1d, $ctr96_b64x @ CTR block 1
2143 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 1
2146 fmov $ctr1.d[1], $ctr32x @ CTR block 1
2147 rev $ctr32w, $rctr32w @ CTR block 2
2148 add $rctr32w, $rctr32w, #1 @ CTR block 2
2150 fmov $ctr2d, $ctr96_b64x @ CTR block 2
2151 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 2
2153 fmov $ctr2.d[1], $ctr32x @ CTR block 2
2154 rev $ctr32w, $rctr32w @ CTR block 3
2156 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 3
2159 fmov $ctr3.d[1], $ctr32x @ CTR block 3
2292 add $rctr32w, $rctr32w, #1 @ CTR block 3
2297 rev $ctr32w, $rctr32w @ CTR block 4
2303 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4
2342 add $rctr32w, $rctr32w, #1 @ CTR block 4
2344 fmov $ctr0d, $ctr96_b64x @ CTR block 4
2346 fmov $ctr0.d[1], $ctr32x @ CTR block 4
2347 rev $ctr32w, $rctr32w @ CTR block 5
2349 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 5
2350 add $rctr32w, $rctr32w, #1 @ CTR block 5
2358 fmov $ctr1d, $ctr96_b64x @ CTR block 5
2363 fmov $ctr1.d[1], $ctr32x @ CTR block 5
2364 rev $ctr32w, $rctr32w @ CTR block 6
2366 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 6
2368 add $rctr32w, $rctr32w, #1 @ CTR block 6
2370 fmov $ctr2d, $ctr96_b64x @ CTR block 6
2372 fmov $ctr2.d[1], $ctr32x @ CTR block 6
2373 rev $ctr32w, $rctr32w @ CTR block 7
2375 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 7
2393 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+3
2397 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+3
2465 add $rctr32w, $rctr32w, #1 @ CTR block 4k+3
2478 rev $ctr32w, $rctr32w @ CTR block 4k+8
2481 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+8
2538 add $rctr32w, $rctr32w, #1 @ CTR block 4k+8
2573 fmov $ctr0d, $ctr96_b64x @ CTR block 4k+8
2576 fmov $ctr0.d[1], $ctr32x @ CTR block 4k+8
2577 rev $ctr32w, $rctr32w @ CTR block 4k+9
2584 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+9
2587 add $rctr32w, $rctr32w, #1 @ CTR block 4k+9
2588 fmov $ctr1d, $ctr96_b64x @ CTR block 4k+9
2591 fmov $ctr1.d[1], $ctr32x @ CTR block 4k+9
2592 rev $ctr32w, $rctr32w @ CTR block 4k+10
2594 add $rctr32w, $rctr32w, #1 @ CTR block 4k+10
2596 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+10
2603 fmov $ctr2d, $ctr96_b64x @ CTR block 4k+10
2606 fmov $ctr2.d[1], $ctr32x @ CTR block 4k+10
2607 rev $ctr32w, $rctr32w @ CTR block 4k+11
2610 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+11
2620 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+3
2622 add $rctr32w, $rctr32w, #1 @ CTR block 4k+3
2629 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+3
3070 fmov $ctr3d, $ctr96_b64x @ CTR block 3
3073 fmov $ctr1d, $ctr96_b64x @ CTR block 1
3079 rev $ctr32w, $rctr32w @ CTR block 1
3081 add $rctr32w, $rctr32w, #1 @ CTR block 1
3082 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 1
3085 fmov $ctr1.d[1], $ctr32x @ CTR block 1
3086 rev $ctr32w, $rctr32w @ CTR block 2
3087 add $rctr32w, $rctr32w, #1 @ CTR block 2
3089 fmov $ctr2d, $ctr96_b64x @ CTR block 2
3090 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 2
3092 fmov $ctr2.d[1], $ctr32x @ CTR block 2
3093 rev $ctr32w, $rctr32w @ CTR block 3
3096 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 3
3098 fmov $ctr3.d[1], $ctr32x @ CTR block 3
3147 add $rctr32w, $rctr32w, #1 @ CTR block 3
3233 rev $ctr32w, $rctr32w @ CTR block 4
3241 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4
3242 add $rctr32w, $rctr32w, #1 @ CTR block 4
3247 fmov $ctr0d, $ctr96_b64x @ CTR block 4
3255 fmov $ctr0.d[1], $ctr32x @ CTR block 4
3256 rev $ctr32w, $rctr32w @ CTR block 5
3258 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 5
3259 fmov $ctr1d, $ctr96_b64x @ CTR block 5
3264 add $rctr32w, $rctr32w, #1 @ CTR block 5
3265 fmov $ctr1.d[1], $ctr32x @ CTR block 5
3270 rev $ctr32w, $rctr32w @ CTR block 6
3276 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 6
3280 add $rctr32w, $rctr32w, #1 @ CTR block 6
3296 fmov $ctr2d, $ctr96_b64x @ CTR block 4k+6
3302 fmov $ctr2.d[1], $ctr32x @ CTR block 4k+6
3311 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+7
3316 rev $ctr32w, $rctr32w @ CTR block 4k+7
3319 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+7
3321 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+7
3440 add $rctr32w, $rctr32w, #1 @ CTR block 4k+7
3450 rev $ctr32w, $rctr32w @ CTR block 4k+8
3468 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+8
3485 fmov $ctr0d, $ctr96_b64x @ CTR block 4k+8
3486 add $rctr32w, $rctr32w, #1 @ CTR block 4k+8
3490 fmov $ctr0.d[1], $ctr32x @ CTR block 4k+8
3491 rev $ctr32w, $rctr32w @ CTR block 4k+9
3497 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+9
3500 fmov $ctr1d, $ctr96_b64x @ CTR block 4k+9
3501 add $rctr32w, $rctr32w, #1 @ CTR block 4k+9
3506 fmov $ctr1.d[1], $ctr32x @ CTR block 4k+9
3507 rev $ctr32w, $rctr32w @ CTR block 4k+10
3519 add $rctr32w, $rctr32w, #1 @ CTR block 4k+10
3521 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+10
3539 fmov $ctr2d, $ctr96_b64x @ CTR block 4k+6
3549 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+7
3555 fmov $ctr2.d[1], $ctr32x @ CTR block 4k+6
3556 rev $ctr32w, $rctr32w @ CTR block 4k+7
3558 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+7
3567 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+7
3595 add $rctr32w, $rctr32w, #1 @ CTR block 4k+7
4079 fmov $ctr2d, $ctr96_b64x @ CTR block 2
4084 fmov $ctr1d, $ctr96_b64x @ CTR block 1
4089 rev $ctr32w, $rctr32w @ CTR block 1
4090 fmov $ctr3d, $ctr96_b64x @ CTR block 3
4092 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 1
4093 add $rctr32w, $rctr32w, #1 @ CTR block 1
4096 fmov $ctr1.d[1], $ctr32x @ CTR block 1
4097 rev $ctr32w, $rctr32w @ CTR block 2
4098 add $rctr32w, $rctr32w, #1 @ CTR block 2
4100 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 2
4103 fmov $ctr2.d[1], $ctr32x @ CTR block 2
4104 rev $ctr32w, $rctr32w @ CTR block 3
4107 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 3
4109 fmov $ctr3.d[1], $ctr32x @ CTR block 3
4151 add $rctr32w, $rctr32w, #1 @ CTR block 3
4257 rev $ctr32w, $rctr32w @ CTR block 4
4293 add $rctr32w, $rctr32w, #1 @ CTR block 4
4295 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4
4302 fmov $ctr0d, $ctr96_b64x @ CTR block 4
4304 fmov $ctr0.d[1], $ctr32x @ CTR block 4
4305 rev $ctr32w, $rctr32w @ CTR block 5
4306 add $rctr32w, $rctr32w, #1 @ CTR block 5
4309 fmov $ctr1d, $ctr96_b64x @ CTR block 5
4310 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 5
4312 fmov $ctr1.d[1], $ctr32x @ CTR block 5
4313 rev $ctr32w, $rctr32w @ CTR block 6
4317 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 6
4322 add $rctr32w, $rctr32w, #1 @ CTR block 6
4323 fmov $ctr2d, $ctr96_b64x @ CTR block 6
4325 fmov $ctr2.d[1], $ctr32x @ CTR block 6
4327 rev $ctr32w, $rctr32w @ CTR block 7
4329 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 7
4340 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+3
4346 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+3
4494 add $rctr32w, $rctr32w, #1 @ CTR block 4k+3
4503 rev $ctr32w, $rctr32w @ CTR block 4k+8
4516 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+8
4526 add $rctr32w, $rctr32w, #1 @ CTR block 4k+8
4545 fmov $ctr0d, $ctr96_b64x @ CTR block 4k+8
4547 fmov $ctr0.d[1], $ctr32x @ CTR block 4k+8
4548 rev $ctr32w, $rctr32w @ CTR block 4k+9
4549 add $rctr32w, $rctr32w, #1 @ CTR block 4k+9
4552 fmov $ctr1d, $ctr96_b64x @ CTR block 4k+9
4553 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+9
4556 fmov $ctr1.d[1], $ctr32x @ CTR block 4k+9
4559 rev $ctr32w, $rctr32w @ CTR block 4k+10
4562 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+10
4568 add $rctr32w, $rctr32w, #1 @ CTR block 4k+10
4572 fmov $ctr2d, $ctr96_b64x @ CTR block 4k+10
4575 fmov $ctr2.d[1], $ctr32x @ CTR block 4k+10
4576 rev $ctr32w, $rctr32w @ CTR block 4k+11
4579 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+11
4590 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+3
4595 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+3
4654 add $rctr32w, $rctr32w, #1 @ CTR block 4k+3
5070 fmov $ctr3d, $ctr96_b64x @ CTR block 3
5072 rev $ctr32w, $rctr32w @ CTR block 1
5073 add $rctr32w, $rctr32w, #1 @ CTR block 1
5074 fmov $ctr1d, $ctr96_b64x @ CTR block 1
5076 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 1
5079 fmov $ctr1.d[1], $ctr32x @ CTR block 1
5080 rev $ctr32w, $rctr32w @ CTR block 2
5081 add $rctr32w, $rctr32w, #1 @ CTR block 2
5083 fmov $ctr2d, $ctr96_b64x @ CTR block 2
5084 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 2
5086 fmov $ctr2.d[1], $ctr32x @ CTR block 2
5087 rev $ctr32w, $rctr32w @ CTR block 3
5089 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 3
5092 fmov $ctr3.d[1], $ctr32x @ CTR block 3
5093 add $rctr32w, $rctr32w, #1 @ CTR block 3
5249 rev $ctr32w, $rctr32w @ CTR block 4
5261 add $rctr32w, $rctr32w, #1 @ CTR block 4
5263 fmov $ctr0d, $ctr96_b64x @ CTR block 4
5264 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4
5266 fmov $ctr0.d[1], $ctr32x @ CTR block 4
5267 rev $ctr32w, $rctr32w @ CTR block 5
5268 add $rctr32w, $rctr32w, #1 @ CTR block 5
5272 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 5
5283 fmov $ctr1d, $ctr96_b64x @ CTR block 5
5287 fmov $ctr1.d[1], $ctr32x @ CTR block 5
5288 rev $ctr32w, $rctr32w @ CTR block 6
5289 add $rctr32w, $rctr32w, #1 @ CTR block 6
5295 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 6
5316 fmov $ctr2d, $ctr96_b64x @ CTR block 4k+6
5318 fmov $ctr2.d[1], $ctr32x @ CTR block 4k+6
5320 rev $ctr32w, $rctr32w @ CTR block 4k+7
5330 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+7
5333 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+7
5336 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+7
5388 add $rctr32w, $rctr32w, #1 @ CTR block 4k+7
5407 rev $ctr32w, $rctr32w @ CTR block 4k+8
5413 add $rctr32w, $rctr32w, #1 @ CTR block 4k+8
5435 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+8
5506 fmov $ctr0d, $ctr96_b64x @ CTR block 4k+8
5509 fmov $ctr0.d[1], $ctr32x @ CTR block 4k+8
5513 rev $ctr32w, $rctr32w @ CTR block 4k+9
5516 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+9
5519 add $rctr32w, $rctr32w, #1 @ CTR block 4k+9
5536 fmov $ctr1d, $ctr96_b64x @ CTR block 4k+9
5539 fmov $ctr1.d[1], $ctr32x @ CTR block 4k+9
5540 rev $ctr32w, $rctr32w @ CTR block 4k+10
5541 add $rctr32w, $rctr32w, #1 @ CTR block 4k+10
5544 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+10
5573 fmov $ctr2d, $ctr96_b64x @ CTR block 4k+6
5575 fmov $ctr2.d[1], $ctr32x @ CTR block 4k+6
5576 rev $ctr32w, $rctr32w @ CTR block 4k+7
5580 orr $ctr32x, $ctr96_t32x, $ctr32x, lsl #32 @ CTR block 4k+7
5588 fmov $ctr3d, $ctr96_b64x @ CTR block 4k+7
5591 fmov $ctr3.d[1], $ctr32x @ CTR block 4k+7
5732 add $rctr32w, $rctr32w, #1 @ CTR block 4k+7