Lines Matching refs:r10
188 ## Fills register %r10 -> .aes_consts (so you can -fPIC)
197 li r10, 0xd0
205 lvx $invhi, r12, r10
206 li r10, 0x110
213 lvx $sbot, r12, r10
214 li r10, 0x150
218 lvx $sb2t, r12, r10
234 ## Clobbers %xmm1-%xmm6, %r9, %r10, %r11, %rax
246 addi r10, r11, 0x40
259 lvx v1, r12, r11 # vmovdqa -0x40(%r11,%r10), %xmm1 # .Lk_mc_forward[]
267 lvx v4, r12, r10 # vmovdqa (%r11,%r10), %xmm4 # .Lk_mc_backward[]
268 addi r10, r11, 0x40
298 addi r10, r11, 0x80
299 # vmovdqa -0x60(%r10), %xmm4 # 3 : sbou .Lk_sbo
300 # vmovdqa -0x50(%r10), %xmm0 # 0 : sbot .Lk_sbo+16
302 lvx v1, r12, r10 # vmovdqa 0x40(%r11,%r10), %xmm1 # .Lk_sr[]
315 li r10,`15+6*$SIZE_T`
319 stvx v20,r10,$sp
320 addi r10,r10,32
323 stvx v22,r10,$sp
324 addi r10,r10,32
327 stvx v24,r10,$sp
328 addi r10,r10,32
331 stvx v26,r10,$sp
332 addi r10,r10,32
335 stvx v28,r10,$sp
336 addi r10,r10,32
339 stvx v30,r10,$sp
375 li r10,`15+6*$SIZE_T`
379 lvx v20,r10,$sp
380 addi r10,r10,32
383 lvx v22,r10,$sp
384 addi r10,r10,32
387 lvx v24,r10,$sp
388 addi r10,r10,32
391 lvx v26,r10,$sp
392 addi r10,r10,32
395 lvx v28,r10,$sp
396 addi r10,r10,32
399 lvx v30,r10,$sp
414 li r10, 0xd0
422 lvx $invhi, r12, r10
423 li r10, 0x190
430 lvx $sbot, r12, r10
431 li r10, 0x1d0
438 lvx $sbdt, r12, r10
439 li r10, 0x210
443 lvx $sbet, r12, r10
476 # vmovdqa -0x20(%r10),%xmm4 # 4 : sb9u
477 # vmovdqa -0x10(%r10),%xmm1 # 0 : sb9t
483 # vmovdqa 0x00(%r10),%xmm4 # 4 : sbdu
485 # vmovdqa 0x10(%r10),%xmm1 # 0 : sbdt
491 # vmovdqa 0x20(%r10), %xmm4 # 4 : sbbu
493 # vmovdqa 0x30(%r10), %xmm1 # 0 : sbbt
499 # vmovdqa 0x40(%r10), %xmm4 # 4 : sbeu
501 # vmovdqa 0x50(%r10), %xmm1 # 0 : sbet
530 addi r10, r11, 0x80
531 # vmovdqa 0x60(%r10), %xmm4 # 3 : sbou
533 # vmovdqa 0x70(%r10), %xmm1 # 0 : sbot
534 lvx v2, r12, r10 # vmovdqa -0x160(%r11), %xmm2 # .Lk_sr-.Lk_dsbd=-0x160
547 li r10,`15+6*$SIZE_T`
551 stvx v20,r10,$sp
552 addi r10,r10,32
555 stvx v22,r10,$sp
556 addi r10,r10,32
559 stvx v24,r10,$sp
560 addi r10,r10,32
563 stvx v26,r10,$sp
564 addi r10,r10,32
567 stvx v28,r10,$sp
568 addi r10,r10,32
571 stvx v30,r10,$sp
607 li r10,`15+6*$SIZE_T`
611 lvx v20,r10,$sp
612 addi r10,r10,32
615 lvx v22,r10,$sp
616 addi r10,r10,32
619 lvx v24,r10,$sp
620 addi r10,r10,32
623 lvx v26,r10,$sp
624 addi r10,r10,32
627 lvx v28,r10,$sp
628 addi r10,r10,32
631 lvx v30,r10,$sp
648 li r10,`15+6*$SIZE_T`
651 stvx v20,r10,$sp
652 addi r10,r10,32
655 stvx v22,r10,$sp
656 addi r10,r10,32
659 stvx v24,r10,$sp
660 addi r10,r10,32
663 stvx v26,r10,$sp
664 addi r10,r10,32
667 stvx v28,r10,$sp
668 addi r10,r10,32
671 stvx v30,r10,$sp
820 li r10, 4
826 stvewx v24, r10, r31
831 li r10,`15+6*$SIZE_T`
833 lvx v20,r10,$sp
834 addi r10,r10,32
837 lvx v22,r10,$sp
838 addi r10,r10,32
841 lvx v24,r10,$sp
842 addi r10,r10,32
845 lvx v26,r10,$sp
846 addi r10,r10,32
849 lvx v28,r10,$sp
850 addi r10,r10,32
853 lvx v30,r10,$sp
886 li r10, 0xd0
894 lvx $invhi, r12, r10
895 li r10, 0x130
903 lvx v15, r12, r10
904 li r10, 0x250
912 lvx v19, r12, r10
913 li r10, 0x290
919 lvx v23, r12, r10
953 li r10, 8
964 stvewx $outhead, r10, $out
965 addi r10, r12, 0x80 # lea .Lk_sr(%rip),%r10
973 addi r10, r12, 0x80 # lea .Lk_sr(%rip),%r10
975 lvx v1, r8, r10 # vmovdqa (%r8,%r10), %xmm1
977 li r10, 8
990 stvewx $outhead, r10, $out
991 addi r10, r12, 0x80 # lea .Lk_sr(%rip),%r10
1112 lvx v1, r8, r10 # vmovdqa (%r8,%r10),%xmm1
1125 li r10, 4
1131 stvewx v0, r10, $out
1147 li r10, 4
1153 stvewx v0, r10, r9
1326 lvx v1, r8, r10 # vmovdqa (%r8,%r10), %xmm1
1374 lvx v1, r8, r10 # vmovdqa (%r8,%r10), %xmm1
1397 li r10,`15+6*$SIZE_T`
1401 stvx v20,r10,$sp
1402 addi r10,r10,32
1405 stvx v22,r10,$sp
1406 addi r10,r10,32
1409 stvx v24,r10,$sp
1410 addi r10,r10,32
1413 stvx v26,r10,$sp
1414 addi r10,r10,32
1417 stvx v28,r10,$sp
1418 addi r10,r10,32
1421 stvx v30,r10,$sp
1437 li r10,`15+6*$SIZE_T`
1442 lvx v20,r10,$sp
1443 addi r10,r10,32
1446 lvx v22,r10,$sp
1447 addi r10,r10,32
1450 lvx v24,r10,$sp
1451 addi r10,r10,32
1454 lvx v26,r10,$sp
1455 addi r10,r10,32
1458 lvx v28,r10,$sp
1459 addi r10,r10,32
1462 lvx v30,r10,$sp
1475 li r10,`15+6*$SIZE_T`
1479 stvx v20,r10,$sp
1480 addi r10,r10,32
1483 stvx v22,r10,$sp
1484 addi r10,r10,32
1487 stvx v24,r10,$sp
1488 addi r10,r10,32
1491 stvx v26,r10,$sp
1492 addi r10,r10,32
1495 stvx v28,r10,$sp
1496 addi r10,r10,32
1499 stvx v30,r10,$sp
1520 li r10,`15+6*$SIZE_T`
1525 lvx v20,r10,$sp
1526 addi r10,r10,32
1529 lvx v22,r10,$sp
1530 addi r10,r10,32
1533 lvx v24,r10,$sp
1534 addi r10,r10,32
1537 lvx v26,r10,$sp
1538 addi r10,r10,32
1541 lvx v28,r10,$sp
1542 addi r10,r10,32
1545 lvx v30,r10,$sp