Lines Matching defs:slot
47 kStack, // fill a register from a stack slot.
48 kLowHalfStack, // fill a register from the low half of a stack slot.
49 kHighHalfStack // fill a register from the high half of a stack slot.
434 // No free register; make this a stack slot.
538 int GetSafepointIndexForStackSlot(const VarState& slot) {
539 // index = 0 is for the stack slot at 'fp + kFixedFrameSizeAboveFp -
540 // kSystemPointerSize', the location of the current stack slot is 'fp -
541 // slot.offset()'. The index we need is therefore '(fp +
542 // kFixedFrameSizeAboveFp - kSystemPointerSize) - (fp - slot.offset())' =
543 // 'slot.offset() + kFixedFrameSizeAboveFp - kSystemPointerSize'.
544 // Concretely, the index of the first stack slot is '4'.
545 return (slot.offset() + StandardFrameConstants::kFixedFrameSizeAboveFp -
554 for (const auto& slot : stack_state) {
555 if (!is_reference(slot.kind())) continue;
557 if (spill_location == SpillLocation::kTopOfStack && slot.is_reg()) {
561 spills->set(slot.reg());
564 DCHECK_IMPLIES(slot.is_reg(), spill_location == SpillLocation::kStackSlots);
566 slots->push_back(GetSafepointIndexForStackSlot(slot));
572 for (const auto& slot : stack_state) {
573 if (is_reference(slot.kind())) {
574 DCHECK(slot.is_stack());
575 safepoint.DefineTaggedStackSlot(GetSafepointIndexForStackSlot(slot));
582 for (const auto& slot : stack_state) {
583 if (!is_reference(slot.kind())) continue;
584 if (slot.is_stack()) {
585 safepoint.DefineTaggedStackSlot(GetSafepointIndexForStackSlot(slot));
587 DCHECK(slot.is_reg());
588 safepoint.DefineTaggedRegister(slot.reg().gp().code());
599 // that the offset of the first spill slot is kSystemPointerSize and not
625 LiftoffRegister LiftoffAssembler::LoadToRegister(VarState slot,
627 if (slot.is_reg()) return slot.reg();
628 LiftoffRegister reg = GetUnusedRegister(reg_class_for(slot.kind()), pinned);
629 if (slot.is_const()) {
630 LoadConstant(reg, slot.constant());
632 DCHECK(slot.is_stack());
633 Fill(reg, slot.offset(), slot.kind());
638 LiftoffRegister LiftoffAssembler::LoadI64HalfIntoRegister(VarState slot,
640 if (slot.is_reg()) {
641 return half == kLowWord ? slot.reg().low() : slot.reg().high();
644 if (slot.is_stack()) {
645 FillI64Half(dst.gp(), slot.offset(), half);
648 DCHECK(slot.is_const());
650 static_cast<int32_t>(half == kLowWord ? slot.constant().to_i64()
651 : slot.constant().to_i64() >> 32);
659 VarState& slot = cache_state_.stack_state.end()[-1 - index];
660 if (slot.is_reg()) {
661 return slot.reg();
663 LiftoffRegister reg = LoadToRegister(slot, pinned);
665 slot.MakeRegister(reg);
672 VarState slot = cache_state_.stack_state.back();
674 if (slot.is_reg()) {
675 cache_state_.dec_used(slot.reg());
691 VarState& slot = cache_state_.stack_state.end()[-1 - i];
692 if (slot.is_stack()) continue;
693 RegClass rc = reg_class_for(slot.kind());
694 if (slot.is_reg()) {
695 if (cache_state_.get_use_count(slot.reg()) > 1) {
699 pinned.set(slot.reg());
701 Move(dst_reg, slot.reg(), slot.kind());
702 cache_state_.dec_used(slot.reg());
704 slot.MakeRegister(dst_reg);
709 LoadConstant(reg, slot.constant());
710 slot.MakeRegister(reg);
722 for (VarState& slot : slots) {
723 if (!slot.is_const()) continue;
724 RegClass rc = reg_class_for(slot.kind());
727 LoadConstant(reg, slot.constant());
729 slot.MakeRegister(reg);
731 Spill(slot.offset(), slot.constant());
732 slot.MakeStack();
868 void LiftoffAssembler::Spill(VarState* slot) {
869 switch (slot->loc()) {
873 Spill(slot->offset(), slot->reg(), slot->kind());
874 cache_state_.dec_used(slot->reg());
877 Spill(slot->offset(), slot->constant());
880 slot->MakeStack();
891 auto& slot = cache_state_.stack_state[i];
892 if (!slot.is_reg()) continue;
893 Spill(slot.offset(), slot.reg(), slot.kind());
894 slot.MakeStack();
952 const VarState& slot = slots[param];
953 const uint32_t stack_offset = slot.offset();
970 stack_transfers->LoadI64HalfIntoRegister(reg, slot, stack_offset,
973 stack_transfers->LoadIntoRegister(reg, slot, stack_offset);
978 stack_slots->Add(slot, stack_offset, half, param_offset);
1108 // Get slot offset relative to the stack pointer.
1202 VarState& slot = slots[i];
1204 ? LoadI64HalfIntoRegister(slot, half)
1205 : LoadToRegister(slot, {});
1228 VarState& slot = slots[i];
1230 stack_transfers.LoadI64HalfIntoRegister(reg, slot, slot.offset(),
1233 stack_transfers.LoadIntoRegister(reg, slot, slot.offset());
1339 auto* slot = &cache_state_.stack_state[idx];
1340 if (!slot->is_reg() || !slot->reg().overlaps(reg)) continue;
1341 if (slot->reg().is_pair()) {
1344 cache_state_.dec_used(slot->reg().low());
1345 cache_state_.dec_used(slot->reg().high());
1346 cache_state_.last_spilled_regs.set(slot->reg().low());
1347 cache_state_.last_spilled_regs.set(slot->reg().high());
1349 Spill(slot->offset(), slot->reg(), slot->kind());
1350 slot->MakeStack();
1367 std::ostream& operator<<(std::ostream& os, VarState slot) {
1368 os << name(slot.kind()) << ":";
1369 switch (slot.loc()) {
1371 return os << "s0x" << std::hex << slot.offset() << std::dec;
1373 return os << slot.reg();
1375 return os << "c" << slot.i32_const();