Lines Matching refs:instr
73 void PrintRs1(Instruction* instr);
74 void PrintRs2(Instruction* instr);
75 void PrintRd(Instruction* instr);
76 void PrintUimm(Instruction* instr);
77 void PrintVs1(Instruction* instr);
78 void PrintVs2(Instruction* instr);
79 void PrintVd(Instruction* instr);
80 void PrintFRs1(Instruction* instr);
81 void PrintFRs2(Instruction* instr);
82 void PrintFRs3(Instruction* instr);
83 void PrintFRd(Instruction* instr);
84 void PrintImm12(Instruction* instr);
85 void PrintImm12X(Instruction* instr);
86 void PrintImm20U(Instruction* instr);
87 void PrintImm20J(Instruction* instr);
88 void PrintShamt(Instruction* instr);
89 void PrintShamt32(Instruction* instr);
90 void PrintRvcImm6(Instruction* instr);
91 void PrintRvcImm6U(Instruction* instr);
92 void PrintRvcImm6Addi16sp(Instruction* instr);
93 void PrintRvcShamt(Instruction* instr);
94 void PrintRvcImm6Ldsp(Instruction* instr);
95 void PrintRvcImm6Lwsp(Instruction* instr);
96 void PrintRvcImm6Sdsp(Instruction* instr);
97 void PrintRvcImm6Swsp(Instruction* instr);
98 void PrintRvcImm5W(Instruction* instr);
99 void PrintRvcImm5D(Instruction* instr);
100 void PrintRvcImm8Addi4spn(Instruction* instr);
101 void PrintRvcImm11CJ(Instruction* instr);
102 void PrintRvcImm8B(Instruction* instr);
103 void PrintRvvVm(Instruction* instr);
104 void PrintAcquireRelease(Instruction* instr);
105 void PrintBranchOffset(Instruction* instr);
106 void PrintStoreOffset(Instruction* instr);
107 void PrintCSRReg(Instruction* instr);
108 void PrintRvvSEW(Instruction* instr);
109 void PrintRvvLMUL(Instruction* instr);
110 void PrintRvvSimm5(Instruction* instr);
111 void PrintRvvUimm5(Instruction* instr);
112 void PrintRoundingMode(Instruction* instr);
113 void PrintMemoryOrder(Instruction* instr, bool is_pred);
116 void DecodeRType(Instruction* instr);
117 void DecodeR4Type(Instruction* instr);
118 void DecodeRAType(Instruction* instr);
119 void DecodeRFPType(Instruction* instr);
120 void DecodeIType(Instruction* instr);
121 void DecodeSType(Instruction* instr);
122 void DecodeBType(Instruction* instr);
123 void DecodeUType(Instruction* instr);
124 void DecodeJType(Instruction* instr);
125 void DecodeCRType(Instruction* instr);
126 void DecodeCAType(Instruction* instr);
127 void DecodeCIType(Instruction* instr);
128 void DecodeCIWType(Instruction* instr);
129 void DecodeCSSType(Instruction* instr);
130 void DecodeCLType(Instruction* instr);
131 void DecodeCSType(Instruction* instr);
132 void DecodeCJType(Instruction* instr);
133 void DecodeCBType(Instruction* instr);
135 void DecodeVType(Instruction* instr);
136 void DecodeRvvIVV(Instruction* instr);
137 void DecodeRvvFVV(Instruction* instr);
138 void DecodeRvvFVF(Instruction* instr);
139 void DecodeRvvIVI(Instruction* instr);
140 void DecodeRvvIVX(Instruction* instr);
141 void DecodeRvvVL(Instruction* instr);
142 void DecodeRvvVS(Instruction* instr);
143 void DecodeRvvMVV(Instruction* instr);
144 void DecodeRvvMVX(Instruction* instr);
146 void PrintInstructionName(Instruction* instr);
148 void PrintTarget(Instruction* instr);
151 int FormatRegister(Instruction* instr, const char* option);
152 int FormatFPURegisterOrRoundMode(Instruction* instr, const char* option);
153 int FormatRvcRegister(Instruction* instr, const char* option);
154 int FormatRvcImm(Instruction* instr, const char* option);
155 int FormatOption(Instruction* instr, const char* option);
156 void Format(Instruction* instr, const char* format);
157 void Unknown(Instruction* instr);
159 int switch_sew(Instruction* instr);
160 int switch_nf(Instruction* instr);
192 void Decoder::PrintRs1(Instruction* instr) {
193 int reg = instr->Rs1Value();
197 void Decoder::PrintRs2(Instruction* instr) {
198 int reg = instr->Rs2Value();
202 void Decoder::PrintRd(Instruction* instr) {
203 int reg = instr->RdValue();
207 void Decoder::PrintUimm(Instruction* instr) {
208 int val = instr->Rs1Value();
212 void Decoder::PrintVs1(Instruction* instr) {
213 int reg = instr->Vs1Value();
217 void Decoder::PrintVs2(Instruction* instr) {
218 int reg = instr->Vs2Value();
222 void Decoder::PrintVd(Instruction* instr) {
223 int reg = instr->VdValue();
232 void Decoder::PrintFRs1(Instruction* instr) {
233 int reg = instr->Rs1Value();
237 void Decoder::PrintFRs2(Instruction* instr) {
238 int reg = instr->Rs2Value();
242 void Decoder::PrintFRs3(Instruction* instr) {
243 int reg = instr->Rs3Value();
247 void Decoder::PrintFRd(Instruction* instr) {
248 int reg = instr->RdValue();
252 void Decoder::PrintImm12X(Instruction* instr) {
253 int32_t imm = instr->Imm12Value();
257 void Decoder::PrintImm12(Instruction* instr) {
258 int32_t imm = instr->Imm12Value();
262 void Decoder::PrintTarget(Instruction* instr) {
263 if (Assembler::IsJalr(instr->InstructionBits())) {
264 if (Assembler::IsAuipc((instr - 4)->InstructionBits()) &&
265 (instr - 4)->RdValue() == instr->Rs1Value()) {
266 int32_t imm = Assembler::BrachlongOffset((instr - 4)->InstructionBits(),
267 instr->InstructionBits());
269 converter_.NameOfAddress(reinterpret_cast<byte*>(instr - 4) + imm);
277 void Decoder::PrintBranchOffset(Instruction* instr) {
278 int32_t imm = instr->BranchOffset();
280 converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + imm);
285 void Decoder::PrintStoreOffset(Instruction* instr) {
286 int32_t imm = instr->StoreOffset();
290 void Decoder::PrintRvvSEW(Instruction* instr) {
291 const char* sew = instr->RvvSEW();
295 void Decoder::PrintRvvLMUL(Instruction* instr) {
296 const char* lmul = instr->RvvLMUL();
300 void Decoder::PrintRvvSimm5(Instruction* instr) {
301 const int simm5 = instr->RvvSimm5();
305 void Decoder::PrintRvvUimm5(Instruction* instr) {
306 const uint32_t uimm5 = instr->RvvUimm5();
310 void Decoder::PrintImm20U(Instruction* instr) {
311 int32_t imm = instr->Imm20UValue();
315 void Decoder::PrintImm20J(Instruction* instr) {
316 int32_t imm = instr->Imm20JValue();
318 converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + imm);
323 void Decoder::PrintShamt(Instruction* instr) {
324 int32_t imm = instr->Shamt();
328 void Decoder::PrintShamt32(Instruction* instr) {
329 int32_t imm = instr->Shamt32();
333 void Decoder::PrintRvcImm6(Instruction* instr) {
334 int32_t imm = instr->RvcImm6Value();
338 void Decoder::PrintRvcImm6U(Instruction* instr) {
339 int32_t imm = instr->RvcImm6Value() & 0xFFFFF;
343 void Decoder::PrintRvcImm6Addi16sp(Instruction* instr) {
344 int32_t imm = instr->RvcImm6Addi16spValue();
348 void Decoder::PrintRvcShamt(Instruction* instr) {
349 int32_t imm = instr->RvcShamt6();
353 void Decoder::PrintRvcImm6Ldsp(Instruction* instr) {
354 int32_t imm = instr->RvcImm6LdspValue();
358 void Decoder::PrintRvcImm6Lwsp(Instruction* instr) {
359 int32_t imm = instr->RvcImm6LwspValue();
363 void Decoder::PrintRvcImm6Swsp(Instruction* instr) {
364 int32_t imm = instr->RvcImm6SwspValue();
368 void Decoder::PrintRvcImm6Sdsp(Instruction* instr) {
369 int32_t imm = instr->RvcImm6SdspValue();
373 void Decoder::PrintRvcImm5W(Instruction* instr) {
374 int32_t imm = instr->RvcImm5WValue();
378 void Decoder::PrintRvcImm5D(Instruction* instr) {
379 int32_t imm = instr->RvcImm5DValue();
383 void Decoder::PrintRvcImm8Addi4spn(Instruction* instr) {
384 int32_t imm = instr->RvcImm8Addi4spnValue();
388 void Decoder::PrintRvcImm11CJ(Instruction* instr) {
389 int32_t imm = instr->RvcImm11CJValue();
393 void Decoder::PrintRvcImm8B(Instruction* instr) {
394 int32_t imm = instr->RvcImm8BValue();
398 void Decoder::PrintRvvVm(Instruction* instr) {
399 uint8_t imm = instr->RvvVM();
405 void Decoder::PrintAcquireRelease(Instruction* instr) {
406 bool aq = instr->AqValue();
407 bool rl = instr->RlValue();
419 void Decoder::PrintCSRReg(Instruction* instr) {
420 int32_t csr_reg = instr->CsrValue();
457 void Decoder::PrintRoundingMode(Instruction* instr) {
458 int frm = instr->RoundMode();
486 void Decoder::PrintMemoryOrder(Instruction* instr, bool is_pred) {
487 int memOrder = instr->MemoryOrder(is_pred);
506 void Decoder::PrintInstructionName(Instruction* instr) {}
510 int Decoder::FormatRegister(Instruction* instr, const char* format) {
514 int reg = instr->Rs1Value();
518 int reg = instr->Rs2Value();
524 int reg = instr->RdValue();
533 int Decoder::FormatFPURegisterOrRoundMode(Instruction* instr,
538 int reg = instr->Rs1Value();
542 int reg = instr->Rs2Value();
546 int reg = instr->Rs3Value();
552 int reg = instr->RdValue();
557 PrintRoundingMode(instr);
565 int Decoder::FormatRvcRegister(Instruction* instr, const char* format) {
571 int reg = instr->RvcRs1sValue();
579 int reg = instr->RvcRs1Value();
588 int reg = instr->RvcRs2sValue();
596 int reg = instr->RvcRs2Value();
606 int reg = instr->RvcRdValue();
619 int Decoder::FormatRvcImm(Instruction* instr, const char* format) {
625 PrintRvcImm6U(instr);
630 PrintRvcImm6Addi16sp(instr);
638 PrintRvcImm6Ldsp(instr);
644 PrintRvcImm6Lwsp(instr);
652 PrintRvcImm6Swsp(instr);
656 PrintRvcImm6Sdsp(instr);
661 PrintRvcImm6(instr);
667 PrintRvcImm5W(instr);
671 PrintRvcImm5D(instr);
679 PrintRvcImm8Addi4spn(instr);
683 PrintRvcImm8B(instr);
691 PrintRvcImm11CJ(instr);
704 int Decoder::FormatOption(Instruction* instr, const char* format) {
708 return FormatRvcRegister(instr, format);
710 return FormatRvcImm(instr, format);
713 PrintRvcShamt(instr);
721 PrintCSRReg(instr);
732 PrintImm12X(instr);
735 PrintImm12(instr);
743 PrintImm20U(instr);
747 PrintImm20J(instr);
757 PrintBranchOffset(instr);
761 PrintStoreOffset(instr);
767 return FormatRegister(instr, format);
770 return FormatFPURegisterOrRoundMode(instr, format);
773 PrintAcquireRelease(instr);
778 PrintMemoryOrder(instr, true);
784 PrintShamt32(instr);
788 PrintShamt(instr);
792 PrintMemoryOrder(instr, false);
796 PrintRvvSEW(instr);
800 PrintRvvSimm5(instr);
808 PrintVd(instr);
812 PrintVs1(instr);
816 PrintVs2(instr);
820 PrintRvvVm(instr);
826 PrintRvvLMUL(instr);
831 PrintRvvUimm5(instr);
835 PrintUimm(instr);
841 PrintTarget(instr);
851 void Decoder::Format(Instruction* instr, const char* format) {
855 format += FormatOption(instr, format);
864 // For currently unimplemented decodings the disassembler calls Unknown(instr)
866 void Decoder::Unknown(Instruction* instr) { Format(instr, "unknown"); }
869 void Decoder::DecodeRType(Instruction* instr) {
870 switch (instr->InstructionBits() & kRTypeMask) {
872 Format(instr, "add 'rd, 'rs1, 'rs2");
875 if (instr->Rs1Value() == zero_reg.code())
876 Format(instr, "neg 'rd, 'rs2");
878 Format(instr, "sub 'rd, 'rs1, 'rs2");
881 Format(instr, "sll 'rd, 'rs1, 'rs2");
884 if (instr->Rs2Value() == zero_reg.code())
885 Format(instr, "sltz 'rd, 'rs1");
886 else if (instr->Rs1Value() == zero_reg.code())
887 Format(instr, "sgtz 'rd, 'rs2");
889 Format(instr, "slt 'rd, 'rs1, 'rs2");
892 if (instr->Rs1Value() == zero_reg.code())
893 Format(instr, "snez 'rd, 'rs2");
895 Format(instr, "sltu 'rd, 'rs1, 'rs2");
898 Format(instr, "xor 'rd, 'rs1, 'rs2");
901 Format(instr, "srl 'rd, 'rs1, 'rs2");
904 Format(instr, "sra 'rd, 'rs1, 'rs2");
907 Format(instr, "or 'rd, 'rs1, 'rs2");
910 Format(instr, "and 'rd, 'rs1, 'rs2");
914 Format(instr, "addw 'rd, 'rs1, 'rs2");
917 if (instr->Rs1Value() == zero_reg.code())
918 Format(instr, "negw 'rd, 'rs2");
920 Format(instr, "subw 'rd, 'rs1, 'rs2");
923 Format(instr, "sllw 'rd, 'rs1, 'rs2");
926 Format(instr, "srlw 'rd, 'rs1, 'rs2");
929 Format(instr, "sraw 'rd, 'rs1, 'rs2");
934 Format(instr, "mul 'rd, 'rs1, 'rs2");
937 Format(instr, "mulh 'rd, 'rs1, 'rs2");
940 Format(instr, "mulhsu 'rd, 'rs1, 'rs2");
943 Format(instr, "mulhu 'rd, 'rs1, 'rs2");
946 Format(instr, "div 'rd, 'rs1, 'rs2");
949 Format(instr, "divu 'rd, 'rs1, 'rs2");
952 Format(instr, "rem 'rd, 'rs1, 'rs2");
955 Format(instr, "remu 'rd, 'rs1, 'rs2");
959 Format(instr, "mulw 'rd, 'rs1, 'rs2");
962 Format(instr, "divw 'rd, 'rs1, 'rs2");
965 Format(instr, "divuw 'rd, 'rs1, 'rs2");
968 Format(instr, "remw 'rd, 'rs1, 'rs2");
971 Format(instr, "remuw 'rd, 'rs1, 'rs2");
976 switch (instr->BaseOpcode()) {
978 DecodeRAType(instr);
981 DecodeRFPType(instr);
990 void Decoder::DecodeRAType(Instruction* instr) {
995 switch (instr->InstructionBits() & kRATypeMask) {
997 Format(instr, "lr.w'a 'rd, ('rs1)");
1000 Format(instr, "sc.w'a 'rd, 'rs2, ('rs1)");
1003 Format(instr, "amoswap.w'a 'rd, 'rs2, ('rs1)");
1006 Format(instr, "amoadd.w'a 'rd, 'rs2, ('rs1)");
1009 Format(instr, "amoxor.w'a 'rd, 'rs2, ('rs1)");
1012 Format(instr, "amoand.w'a 'rd, 'rs2, ('rs1)");
1015 Format(instr, "amoor.w'a 'rd, 'rs2, ('rs1)");
1018 Format(instr, "amomin.w'a 'rd, 'rs2, ('rs1)");
1021 Format(instr, "amomax.w'a 'rd, 'rs2, ('rs1)");
1024 Format(instr, "amominu.w'a 'rd, 'rs2, ('rs1)");
1027 Format(instr, "amomaxu.w'a 'rd, 'rs2, ('rs1)");
1031 Format(instr, "lr.d'a 'rd, ('rs1)");
1034 Format(instr, "sc.d'a 'rd, 'rs2, ('rs1)");
1037 Format(instr, "amoswap.d'a 'rd, 'rs2, ('rs1)");
1040 Format(instr, "amoadd.d'a 'rd, 'rs2, ('rs1)");
1043 Format(instr, "amoxor.d'a 'rd, 'rs2, ('rs1)");
1046 Format(instr, "amoand.d'a 'rd, 'rs2, ('rs1)");
1049 Format(instr, "amoor.d'a 'rd, 'rs2, ('rs1)");
1052 Format(instr, "amomin.d'a 'rd, 'rs2, ('rs1)");
1055 Format(instr, "amoswap.d'a 'rd, 'rs2, ('rs1)");
1058 Format(instr, "amominu.d'a 'rd, 'rs2, ('rs1)");
1061 Format(instr, "amomaxu.d'a 'rd, 'rs2, ('rs1)");
1071 void Decoder::DecodeRFPType(Instruction* instr) {
1075 switch (instr->InstructionBits() & kRFPTypeMask) {
1078 Format(instr, "fadd.s 'fd, 'fs1, 'fs2");
1081 Format(instr, "fsub.s 'fd, 'fs1, 'fs2");
1084 Format(instr, "fmul.s 'fd, 'fs1, 'fs2");
1087 Format(instr, "fdiv.s 'fd, 'fs1, 'fs2");
1090 Format(instr, "fsqrt.s 'fd, 'fs1");
1093 switch (instr->Funct3Value()) {
1095 if (instr->Rs1Value() == instr->Rs2Value())
1096 Format(instr, "fmv.s 'fd, 'fs1");
1098 Format(instr, "fsgnj.s 'fd, 'fs1, 'fs2");
1101 if (instr->Rs1Value() == instr->Rs2Value())
1102 Format(instr, "fneg.s 'fd, 'fs1");
1104 Format(instr, "fsgnjn.s 'fd, 'fs1, 'fs2");
1107 if (instr->Rs1Value() == instr->Rs2Value())
1108 Format(instr, "fabs.s 'fd, 'fs1");
1110 Format(instr, "fsgnjx.s 'fd, 'fs1, 'fs2");
1118 switch (instr->Funct3Value()) {
1120 Format(instr, "fmin.s 'fd, 'fs1, 'fs2");
1123 Format(instr, "fmax.s 'fd, 'fs1, 'fs2");
1131 switch (instr->Rs2Value()) {
1133 Format(instr, "fcvt.w.s ['frm] 'rd, 'fs1");
1136 Format(instr, "fcvt.wu.s ['frm] 'rd, 'fs1");
1140 Format(instr, "fcvt.l.s ['frm] 'rd, 'fs1");
1143 Format(instr, "fcvt.lu.s ['frm] 'rd, 'fs1");
1152 if (instr->Rs2Value() != 0b00000) {
1155 switch (instr->Funct3Value()) {
1157 Format(instr, "fmv.x.w 'rd, 'fs1");
1160 Format(instr, "fclass.s 'rd, 'fs1");
1168 switch (instr->Funct3Value()) {
1170 Format(instr, "feq.s 'rd, 'fs1, 'fs2");
1173 Format(instr, "flt.s 'rd, 'fs1, 'fs2");
1176 Format(instr, "fle.s 'rd, 'fs1, 'fs2");
1184 switch (instr->Rs2Value()) {
1186 Format(instr, "fcvt.s.w 'fd, 'rs1");
1189 Format(instr, "fcvt.s.wu 'fd, 'rs1");
1193 Format(instr, "fcvt.s.l 'fd, 'rs1");
1196 Format(instr, "fcvt.s.lu 'fd, 'rs1");
1206 if (instr->Funct3Value() == 0b000) {
1207 Format(instr, "fmv.w.x 'fd, 'rs1");
1215 Format(instr, "fadd.d 'fd, 'fs1, 'fs2");
1218 Format(instr, "fsub.d 'fd, 'fs1, 'fs2");
1221 Format(instr, "fmul.d 'fd, 'fs1, 'fs2");
1224 Format(instr, "fdiv.d 'fd, 'fs1, 'fs2");
1227 if (instr->Rs2Value() == 0b00000) {
1228 Format(instr, "fsqrt.d 'fd, 'fs1");
1235 switch (instr->Funct3Value()) {
1237 if (instr->Rs1Value() == instr->Rs2Value())
1238 Format(instr, "fmv.d 'fd, 'fs1");
1240 Format(instr, "fsgnj.d 'fd, 'fs1, 'fs2");
1243 if (instr->Rs1Value() == instr->Rs2Value())
1244 Format(instr, "fneg.d 'fd, 'fs1");
1246 Format(instr, "fsgnjn.d 'fd, 'fs1, 'fs2");
1249 if (instr->Rs1Value() == instr->Rs2Value())
1250 Format(instr, "fabs.d 'fd, 'fs1");
1252 Format(instr, "fsgnjx.d 'fd, 'fs1, 'fs2");
1260 switch (instr->Funct3Value()) {
1262 Format(instr, "fmin.d 'fd, 'fs1, 'fs2");
1265 Format(instr, "fmax.d 'fd, 'fs1, 'fs2");
1273 if (instr->Rs2Value() == 0b00001) {
1274 Format(instr, "fcvt.s.d ['frm] 'fd, 'rs1");
1281 if (instr->Rs2Value() == 0b00000) {
1282 Format(instr, "fcvt.d.s 'fd, 'fs1");
1289 switch (instr->Funct3Value()) {
1291 Format(instr, "feq.d 'rd, 'fs1, 'fs2");
1294 Format(instr, "flt.d 'rd, 'fs1, 'fs2");
1297 Format(instr, "fle.d 'rd, 'fs1, 'fs2");
1305 if (instr->Rs2Value() != 0b00000) {
1309 switch (instr->Funct3Value()) {
1311 Format(instr, "fclass.d 'rd, 'fs1");
1315 Format(instr, "fmv.x.d 'rd, 'fs1");
1324 switch (instr->Rs2Value()) {
1326 Format(instr, "fcvt.w.d ['frm] 'rd, 'fs1");
1329 Format(instr, "fcvt.wu.d ['frm] 'rd, 'fs1");
1333 Format(instr, "fcvt.l.d ['frm] 'rd, 'fs1");
1336 Format(instr, "fcvt.lu.d ['frm] 'rd, 'fs1");
1345 switch (instr->Rs2Value()) {
1347 Format(instr, "fcvt.d.w 'fd, 'rs1");
1350 Format(instr, "fcvt.d.wu 'fd, 'rs1");
1354 Format(instr, "fcvt.d.l 'fd, 'rs1");
1357 Format(instr, "fcvt.d.lu 'fd, 'rs1");
1367 if (instr->Funct3Value() == 0b000 && instr->Rs2Value() == 0b00000) {
1368 Format(instr, "fmv.d.x 'fd, 'rs1");
1381 void Decoder::DecodeR4Type(Instruction* instr) {
1382 switch (instr->InstructionBits() & kR4TypeMask) {
1385 Format(instr, "fmadd.s 'fd, 'fs1, 'fs2, 'fs3");
1388 Format(instr, "fmsub.s 'fd, 'fs1, 'fs2, 'fs3");
1391 Format(instr, "fnmsub.s 'fd, 'fs1, 'fs2, 'fs3");
1394 Format(instr, "fnmadd.s 'fd, 'fs1, 'fs2, 'fs3");
1398 Format(instr, "fmadd.d 'fd, 'fs1, 'fs2, 'fs3");
1401 Format(instr, "fmsub.d 'fd, 'fs1, 'fs2, 'fs3");
1404 Format(instr, "fnmsub.d 'fd, 'fs1, 'fs2, 'fs3");
1407 Format(instr, "fnmadd.d 'fd, 'fs1, 'fs2, 'fs3");
1414 void Decoder::DecodeIType(Instruction* instr) {
1415 if (instr->vl_vs_width() != -1) {
1416 DecodeRvvVL(instr);
1418 switch (instr->InstructionBits() & kITypeMask) {
1420 if (instr->RdValue() == zero_reg.code() &&
1421 instr->Rs1Value() == ra.code() && instr->Imm12Value() == 0)
1422 Format(instr, "ret");
1423 else if (instr->RdValue() == zero_reg.code() &&
1424 instr->Imm12Value() == 0)
1425 Format(instr, "jr 'rs1");
1426 else if (instr->RdValue() == ra.code() && instr->Imm12Value() == 0)
1427 Format(instr, "jalr 'rs1");
1429 Format(instr, "jalr 'rd, 'imm12('rs1)");
1432 Format(instr, "lb 'rd, 'imm12('rs1)");
1435 Format(instr, "lh 'rd, 'imm12('rs1)");
1438 Format(instr, "lw 'rd, 'imm12('rs1)");
1441 Format(instr, "lbu 'rd, 'imm12('rs1)");
1444 Format(instr, "lhu 'rd, 'imm12('rs1)");
1448 Format(instr, "lwu 'rd, 'imm12('rs1)");
1451 Format(instr, "ld 'rd, 'imm12('rs1)");
1455 if (instr->Imm12Value() == 0) {
1456 if (instr->RdValue() == zero_reg.code() &&
1457 instr->Rs1Value() == zero_reg.code())
1458 Format(instr, "nop");
1460 Format(instr, "mv 'rd, 'rs1");
1461 } else if (instr->Rs1Value() == zero_reg.code()) {
1462 Format(instr, "li 'rd, 'imm12");
1464 Format(instr, "addi 'rd, 'rs1, 'imm12");
1468 Format(instr, "slti 'rd, 'rs1, 'imm12");
1471 if (instr->Imm12Value() == 1)
1472 Format(instr, "seqz 'rd, 'rs1");
1474 Format(instr, "sltiu 'rd, 'rs1, 'imm12");
1477 if (instr->Imm12Value() == -1)
1478 Format(instr, "not 'rd, 'rs1");
1480 Format(instr, "xori 'rd, 'rs1, 'imm12x");
1483 Format(instr, "ori 'rd, 'rs1, 'imm12x");
1486 Format(instr, "andi 'rd, 'rs1, 'imm12x");
1489 Format(instr, "slli 'rd, 'rs1, 's64");
1492 if (!instr->IsArithShift()) {
1493 Format(instr, "srli 'rd, 'rs1, 's64");
1495 Format(instr, "srai 'rd, 'rs1, 's64");
1501 if (instr->Imm12Value() == 0)
1502 Format(instr, "sext.w 'rd, 'rs1");
1504 Format(instr, "addiw 'rd, 'rs1, 'imm12");
1507 Format(instr, "slliw 'rd, 'rs1, 's32");
1510 if (!instr->IsArithShift()) {
1511 Format(instr, "srliw 'rd, 'rs1, 's32");
1513 Format(instr, "sraiw 'rd, 'rs1, 's32");
1519 if (instr->MemoryOrder(true) == PSIORW &&
1520 instr->MemoryOrder(false) == PSIORW)
1521 Format(instr, "fence");
1523 Format(instr, "fence 'pre, 'suc");
1526 if (instr->Imm12Value() == 0) { // ECALL
1527 Format(instr, "ecall");
1528 } else if (instr->Imm12Value() == 1) { // EBREAK
1529 Format(instr, "ebreak");
1537 Format(instr, "fence.i");
1542 if (instr->CsrValue() == csr_fcsr) {
1543 if (instr->RdValue() == zero_reg.code())
1544 Format(instr, "fscsr 'rs1");
1546 Format(instr, "fscsr 'rd, 'rs1");
1547 } else if (instr->CsrValue() == csr_frm) {
1548 if (instr->RdValue() == zero_reg.code())
1549 Format(instr, "fsrm 'rs1");
1551 Format(instr, "fsrm 'rd, 'rs1");
1552 } else if (instr->CsrValue() == csr_fflags) {
1553 if (instr->RdValue() == zero_reg.code())
1554 Format(instr, "fsflags 'rs1");
1556 Format(instr, "fsflags 'rd, 'rs1");
1557 } else if (instr->RdValue() == zero_reg.code()) {
1558 Format(instr, "csrw 'csr, 'rs1");
1560 Format(instr, "csrrw 'rd, 'csr, 'rs1");
1564 if (instr->Rs1Value() == zero_reg.code()) {
1565 switch (instr->CsrValue()) {
1567 Format(instr, "rdinstret 'rd");
1570 Format(instr, "rdinstreth 'rd");
1573 Format(instr, "rdtime 'rd");
1576 Format(instr, "rdtimeh 'rd");
1579 Format(instr, "rdcycle 'rd");
1582 Format(instr, "rdcycleh 'rd");
1585 Format(instr, "frflags 'rd");
1588 Format(instr, "frrm 'rd");
1591 Format(instr, "frcsr 'rd");
1596 } else if (instr->Rs1Value() == zero_reg.code()) {
1597 Format(instr, "csrr 'rd, 'csr");
1598 } else if (instr->RdValue() == zero_reg.code()) {
1599 Format(instr, "csrs 'csr, 'rs1");
1601 Format(instr, "csrrs 'rd, 'csr, 'rs1");
1605 if (instr->RdValue() == zero_reg.code())
1606 Format(instr, "csrc 'csr, 'rs1");
1608 Format(instr, "csrrc 'rd, 'csr, 'rs1");
1611 if (instr->RdValue() == zero_reg.code())
1612 Format(instr, "csrwi 'csr, 'uimm");
1614 Format(instr, "csrrwi 'rd, 'csr, 'uimm");
1617 if (instr->RdValue() == zero_reg.code())
1618 Format(instr, "csrsi 'csr, 'uimm");
1620 Format(instr, "csrrsi 'rd, 'csr, 'uimm");
1623 if (instr->RdValue() == zero_reg.code())
1624 Format(instr, "csrci 'csr, 'uimm");
1626 Format(instr, "csrrci 'rd, 'csr, 'uimm");
1630 Format(instr, "flw 'fd, 'imm12('rs1)");
1634 Format(instr, "fld 'fd, 'imm12('rs1)");
1642 void Decoder::DecodeSType(Instruction* instr) {
1643 if (instr->vl_vs_width() != -1) {
1644 DecodeRvvVS(instr);
1646 switch (instr->InstructionBits() & kSTypeMask) {
1648 Format(instr, "sb 'rs2, 'offS('rs1)");
1651 Format(instr, "sh 'rs2, 'offS('rs1)");
1654 Format(instr, "sw 'rs2, 'offS('rs1)");
1658 Format(instr, "sd 'rs2, 'offS('rs1)");
1663 Format(instr, "fsw 'fs2, 'offS('rs1)");
1667 Format(instr, "fsd 'fs2, 'offS('rs1)");
1674 void Decoder::DecodeBType(Instruction* instr) {
1675 switch (instr->InstructionBits() & kBTypeMask) {
1677 Format(instr, "beq 'rs1, 'rs2, 'offB");
1680 Format(instr, "bne 'rs1, 'rs2, 'offB");
1683 Format(instr, "blt 'rs1, 'rs2, 'offB");
1686 Format(instr, "bge 'rs1, 'rs2, 'offB");
1689 Format(instr, "bltu 'rs1, 'rs2, 'offB");
1692 Format(instr, "bgeu 'rs1, 'rs2, 'offB");
1698 void Decoder::DecodeUType(Instruction* instr) {
1700 switch (instr->BaseOpcodeFieldRaw()) {
1702 Format(instr, "lui 'rd, 'imm20U");
1705 Format(instr, "auipc 'rd, 'imm20U");
1712 void Decoder::DecodeJType(Instruction* instr) {
1714 switch (instr->BaseOpcodeValue()) {
1716 if (instr->RdValue() == zero_reg.code())
1717 Format(instr, "j 'imm20J");
1718 else if (instr->RdValue() == ra.code())
1719 Format(instr, "jal 'imm20J");
1721 Format(instr, "jal 'rd, 'imm20J");
1728 void Decoder::DecodeCRType(Instruction* instr) {
1729 switch (instr->RvcFunct4Value()) {
1731 if (instr->RvcRs1Value() != 0 && instr->RvcRs2Value() == 0)
1732 Format(instr, "jr 'Crs1");
1733 else if (instr->RvcRdValue() != 0 && instr->RvcRs2Value() != 0)
1734 Format(instr, "mv 'Crd, 'Crs2");
1739 if (instr->RvcRs1Value() == 0 && instr->RvcRs2Value() == 0)
1740 Format(instr, "ebreak");
1741 else if (instr->RvcRdValue() != 0 && instr->RvcRs2Value() == 0)
1742 Format(instr, "jalr 'Crs1");
1743 else if (instr->RvcRdValue() != 0 && instr->RvcRs2Value() != 0)
1744 Format(instr, "add 'Crd, 'Crd, 'Crs2");
1753 void Decoder::DecodeCAType(Instruction* instr) {
1754 switch (instr->InstructionBits() & kCATypeMask) {
1756 Format(instr, "sub 'Crs1s, 'Crs1s, 'Crs2s");
1759 Format(instr, "xor 'Crs1s, 'Crs1s, 'Crs2s");
1762 Format(instr, "or 'Crs1s, 'Crs1s, 'Crs2s");
1765 Format(instr, "and 'Crs1s, 'Crs1s, 'Crs2s");
1768 Format(instr, "subw 'Crs1s, 'Crs1s, 'Crs2s");
1771 Format(instr, "addw 'Crs1s, 'Crs1s, 'Crs2s");
1778 void Decoder::DecodeCIType(Instruction* instr) {
1779 switch (instr->RvcOpcode()) {
1781 if (instr->RvcRdValue() == 0)
1782 Format(instr, "nop");
1784 Format(instr, "addi 'Crd, 'Crd, 'Cimm6");
1787 Format(instr, "addiw 'Crd, 'Crd, 'Cimm6");
1790 Format(instr, "li 'Crd, 'Cimm6");
1793 if (instr->RvcRdValue() == 2)
1794 Format(instr, "addi sp, sp, 'Cimm6Addi16sp");
1795 else if (instr->RvcRdValue() != 0 && instr->RvcRdValue() != 2)
1796 Format(instr, "lui 'Crd, 'Cimm6U");
1801 Format(instr, "slli 'Crd, 'Crd, 'Cshamt");
1804 Format(instr, "fld 'Cfd, 'Cimm6Ldsp(sp)");
1807 Format(instr, "lw 'Crd, 'Cimm6Lwsp(sp)");
1810 Format(instr, "ld 'Crd, 'Cimm6Ldsp(sp)");
1817 void Decoder::DecodeCIWType(Instruction* instr) {
1818 switch (instr->RvcOpcode()) {
1820 Format(instr, "addi 'Crs2s, sp, 'Cimm8Addi4spn");
1827 void Decoder::DecodeCSSType(Instruction* instr) {
1828 switch (instr->RvcOpcode()) {
1830 Format(instr, "sw 'Crs2, 'Cimm6Swsp(sp)");
1833 Format(instr, "sd 'Crs2, 'Cimm6Sdsp(sp)");
1836 Format(instr, "fsd 'Cfs2, 'Cimm6Sdsp(sp)");
1843 void Decoder::DecodeCLType(Instruction* instr) {
1844 switch (instr->RvcOpcode()) {
1846 Format(instr, "fld 'Cfs2s, 'Cimm5D('Crs1s)");
1849 Format(instr, "lw 'Crs2s, 'Cimm5W('Crs1s)");
1852 Format(instr, "ld 'Crs2s, 'Cimm5D('Crs1s)");
1859 void Decoder::DecodeCSType(Instruction* instr) {
1860 switch (instr->RvcOpcode()) {
1862 Format(instr, "fsd 'Cfs2s, 'Cimm5D('Crs1s)");
1865 Format(instr, "sw 'Crs2s, 'Cimm5W('Crs1s)");
1868 Format(instr, "sd 'Crs2s, 'Cimm5D('Crs1s)");
1875 void Decoder::DecodeCJType(Instruction* instr) {
1876 switch (instr->RvcOpcode()) {
1878 Format(instr, "j 'Cimm11CJ");
1885 void Decoder::DecodeCBType(Instruction* instr) {
1886 switch (instr->RvcOpcode()) {
1888 Format(instr, "bnez 'Crs1s, x0, 'Cimm8B");
1891 Format(instr, "beqz 'Crs1s, x0, 'Cimm8B");
1894 if (instr->RvcFunct2BValue() == 0b00)
1895 Format(instr, "srli 'Crs1s, 'Crs1s, 'Cshamt");
1896 else if (instr->RvcFunct2BValue() == 0b01)
1897 Format(instr, "srai 'Crs1s, 'Crs1s, 'Cshamt");
1898 else if (instr->RvcFunct2BValue() == 0b10)
1899 Format(instr, "andi 'Crs1s, 'Crs1s, 'Cimm6");
1908 void Decoder::DecodeRvvIVV(Instruction* instr) {
1909 DCHECK_EQ(instr->InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_IVV);
1910 switch (instr->InstructionBits() & kVTypeMask) {
1912 Format(instr, "vadd.vv 'vd, 'vs2, 'vs1'vm");
1915 Format(instr, "vsadd.vv 'vd, 'vs2, 'vs1'vm");
1918 Format(instr, "vsaddu.vv 'vd, 'vs2, 'vs1'vm");
1921 Format(instr, "vsub.vv 'vd, 'vs2, 'vs1'vm");
1924 Format(instr, "vssub.vv 'vd, 'vs2, 'vs1'vm");
1927 Format(instr, "vssubu.vv 'vd, 'vs2, 'vs1'vm");
1930 Format(instr, "vmin.vv 'vd, 'vs2, 'vs1'vm");
1933 Format(instr, "vminu.vv 'vd, 'vs2, 'vs1'vm");
1936 Format(instr, "vmax.vv 'vd, 'vs2, 'vs1'vm");
1939 Format(instr, "vmaxu.vv 'vd, 'vs2, 'vs1'vm");
1942 Format(instr, "vand.vv 'vd, 'vs2, 'vs1'vm");
1945 Format(instr, "vor.vv 'vd, 'vs2, 'vs1'vm");
1948 Format(instr, "vxor.vv 'vd, 'vs2, 'vs1'vm");
1951 Format(instr, "vrgather.vv 'vd, 'vs2, 'vs1'vm");
1954 Format(instr, "vmseq.vv 'vd, 'vs2, 'vs1'vm");
1957 Format(instr, "vmsne.vv 'vd, 'vs2, 'vs1'vm");
1960 Format(instr, "vmslt.vv 'vd, 'vs2, 'vs1'vm");
1963 Format(instr, "vmsltu.vv 'vd, 'vs2, 'vs1'vm");
1966 Format(instr, "vmsle.vv 'vd, 'vs2, 'vs1'vm");
1969 Format(instr, "vmsleu.vv 'vd, 'vs2, 'vs1'vm");
1972 if (instr->RvvVM()) {
1973 Format(instr, "vmv.vv 'vd, 'vs1");
1975 Format(instr, "vmerge.vvm 'vd, 'vs2, 'vs1, v0");
1979 if (!instr->RvvVM()) {
1980 Format(instr, "vadc.vvm 'vd, 'vs2, 'vs1");
1986 if (!instr->RvvVM()) {
1987 Format(instr, "vmadc.vvm 'vd, 'vs2, 'vs1");
1993 Format(instr, "vnclip.wv 'vd, 'vs2, 'vs1");
1996 Format(instr, "vnclipu.wv 'vd, 'vs2, 'vs1");
1999 Format(instr, "vsll.vv 'vd, 'vs2, 'vs1");
2002 Format(instr, "vsrl.vv 'vd, 'vs2, 'vs1");
2005 Format(instr, "vsra.vv 'vd, 'vs2, 'vs1");
2008 Format(instr, "vsmul.vv 'vd, 'vs2, 'vs1");
2016 void Decoder::DecodeRvvIVI(Instruction* instr) {
2017 DCHECK_EQ(instr->InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_IVI);
2018 switch (instr->InstructionBits() & kVTypeMask) {
2020 Format(instr, "vadd.vi 'vd, 'vs2, 'simm5'vm");
2023 Format(instr, "vsadd.vi 'vd, 'vs2, 'simm5'vm");
2026 Format(instr, "vsaddu.vi 'vd, 'vs2, 'simm5'vm");
2029 Format(instr, "vrsub.vi 'vd, 'vs2, 'simm5'vm");
2032 Format(instr, "vand.vi 'vd, 'vs2, 'simm5'vm");
2035 Format(instr, "vor.vi 'vd, 'vs2, 'simm5'vm");
2038 Format(instr, "vxor.vi 'vd, 'vs2, 'simm5'vm");
2041 Format(instr, "vrgather.vi 'vd, 'vs2, 'simm5'vm");
2044 if (instr->RvvVM()) {
2045 Format(instr, "vmv.vi 'vd, 'simm5");
2047 Format(instr, "vmerge.vim 'vd, 'vs2, 'simm5, v0");
2051 Format(instr, "vmseq.vi 'vd, 'vs2, 'simm5'vm");
2054 Format(instr, "vmsne.vi 'vd, 'vs2, 'simm5'vm");
2057 Format(instr, "vmsleu.vi 'vd, 'vs2, 'simm5'vm");
2060 Format(instr, "vmsle.vi 'vd, 'vs2, 'simm5'vm");
2063 Format(instr, "vmsgtu.vi 'vd, 'vs2, 'simm5'vm");
2066 Format(instr, "vmsgt.vi 'vd, 'vs2, 'simm5'vm");
2069 Format(instr, "vslidedown.vi 'vd, 'vs2, 'uimm5'vm");
2072 Format(instr, "vslideup.vi 'vd, 'vs2, 'uimm5'vm");
2075 Format(instr, "vsrl.vi 'vd, 'vs2, 'uimm5'vm");
2078 Format(instr, "vsra.vi 'vd, 'vs2, 'uimm5'vm");
2081 Format(instr, "vsll.vi 'vd, 'vs2, 'uimm5'vm");
2084 if (!instr->RvvVM()) {
2085 Format(instr, "vadc.vim 'vd, 'vs2, 'uimm5");
2091 if (!instr->RvvVM()) {
2092 Format(instr, "vmadc.vim 'vd, 'vs2, 'uimm5");
2098 Format(instr, "vnclip.wi 'vd, 'vs2, 'uimm5");
2101 Format(instr, "vnclipu.wi 'vd, 'vs2, 'uimm5");
2109 void Decoder::DecodeRvvIVX(Instruction* instr) {
2110 DCHECK_EQ(instr->InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_IVX);
2111 switch (instr->InstructionBits() & kVTypeMask) {
2113 Format(instr, "vadd.vx 'vd, 'vs2, 'rs1'vm");
2116 Format(instr, "vsadd.vx 'vd, 'vs2, 'rs1'vm");
2119 Format(instr, "vsaddu.vx 'vd, 'vs2, 'rs1'vm");
2122 Format(instr, "vsub.vx 'vd, 'vs2, 'rs1'vm");
2125 Format(instr, "vssub.vx 'vd, 'vs2, 'rs1'vm");
2128 Format(instr, "vrsub.vx 'vd, 'vs2, 'rs1'vm");
2131 Format(instr, "vmin.vx 'vd, 'vs2, 'rs1'vm");
2134 Format(instr, "vminu.vx 'vd, 'vs2, 'rs1'vm");
2137 Format(instr, "vmax.vx 'vd, 'vs2, 'rs1'vm");
2140 Format(instr, "vmaxu.vx 'vd, 'vs2, 'rs1'vm");
2143 Format(instr, "vand.vx 'vd, 'vs2, 'rs1'vm");
2146 Format(instr, "vor.vx 'vd, 'vs2, 'rs1'vm");
2149 Format(instr, "vxor.vx 'vd, 'vs2, 'rs1'vm");
2152 Format(instr, "vrgather.vx 'vd, 'vs2, 'rs1'vm");
2155 if (instr->RvvVM()) {
2156 Format(instr, "vmv.vx 'vd, 'rs1");
2158 Format(instr, "vmerge.vxm 'vd, 'vs2, 'rs1, v0");
2162 Format(instr, "vmseq.vx 'vd, 'vs2, 'rs1'vm");
2165 Format(instr, "vmsne.vx 'vd, 'vs2, 'rs1'vm");
2168 Format(instr, "vmslt.vx 'vd, 'vs2, 'rs1'vm");
2171 Format(instr, "vmsltu.vx 'vd, 'vs2, 'rs1'vm");
2174 Format(instr, "vmsle.vx 'vd, 'vs2, 'rs1'vm");
2177 Format(instr, "vmsleu.vx 'vd, 'vs2, 'rs1'vm");
2180 Format(instr, "vmsgt.vx 'vd, 'vs2, 'rs1'vm");
2183 Format(instr, "vmsgtu.vx 'vd, 'vs2, 'rs1'vm");
2186 Format(instr, "vslidedown.vx 'vd, 'vs2, 'rs1'vm");
2189 if (!instr->RvvVM()) {
2190 Format(instr, "vadc.vxm 'vd, 'vs2, 'rs1");
2196 if (!instr->RvvVM()) {
2197 Format(instr, "vmadc.vxm 'vd, 'vs2, 'rs1");
2203 Format(instr, "vsll.vx 'vd, 'vs2, 'rs1");
2206 Format(instr, "vsrl.vx 'vd, 'vs2, 'rs1");
2209 Format(instr, "vsra.vx 'vd, 'vs2, 'rs1");
2212 Format(instr, "vnclip.wx 'vd, 'vs2, 'rs1");
2215 Format(instr, "vnclipu.wx 'vd, 'vs2, 'rs1");
2218 Format(instr, "vsmul.vx 'vd, 'vs2, 'vs1");
2226 void Decoder::DecodeRvvMVV(Instruction* instr) {
2227 DCHECK_EQ(instr->InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_MVV);
2228 switch (instr->InstructionBits() & kVTypeMask) {
2230 if (instr->Vs1Value() == VID_V) {
2231 Format(instr, "vid.v 'rd, 'vs2'vm");
2238 if (instr->Vs1Value() == 0x0) {
2239 Format(instr, "vmv.x.s 'rd, 'vs2");
2240 } else if (instr->Vs1Value() == 0b10001) {
2241 Format(instr, "vfirst.m 'rd, 'vs2");
2242 } else if (instr->Vs1Value() == 0b10000) {
2243 Format(instr, "vcpop.m 'rd, 'vs2");
2249 Format(instr, "vredmaxu.vs 'vd, 'vs2, 'vs1'vm");
2252 Format(instr, "vredmax.vs 'vd, 'vs2, 'vs1'vm");
2255 Format(instr, "vredmin.vs 'vd, 'vs2, 'vs1'vm");
2258 Format(instr, "vredminu.vs 'vd, 'vs2, 'vs1'vm");
2261 if (instr->Vs1Value() == 0b00010) {
2262 Format(instr, "vzext.vf8 'vd, 'vs2'vm");
2263 } else if (instr->Vs1Value() == 0b00011) {
2264 Format(instr, "vsext.vf8 'vd, 'vs2'vm");
2265 } else if (instr->Vs1Value() == 0b00100) {
2266 Format(instr, "vzext.vf4 'vd, 'vs2'vm");
2267 } else if (instr->Vs1Value() == 0b00101) {
2268 Format(instr, "vsext.vf4 'vd, 'vs2'vm");
2269 } else if (instr->Vs1Value() == 0b00110) {
2270 Format(instr, "vzext.vf2 'vd, 'vs2'vm");
2271 } else if (instr->Vs1Value() == 0b00111) {
2272 Format(instr, "vsext.vf2 'vd, 'vs2'vm");
2278 Format(instr, "vwmul.vv 'vd, 'vs2, 'vs1'vm");
2281 Format(instr, "vwmulu.vv 'vd, 'vs2, 'vs1'vm");
2284 Format(instr, "vmul.vv 'vd, 'vs2, 'vs1'vm");
2287 Format(instr, "vmulhu.vv 'vd, 'vs2, 'vs1'vm");
2290 Format(instr, "vdiv.vv 'vd, 'vs2, 'vs1'vm");
2293 Format(instr, "vdivu.vv 'vd, 'vs2, 'vs1'vm");
2296 Format(instr, "vwaddu.vv 'vd, 'vs2, 'vs1'vm");
2299 Format(instr, "vwadd.vv 'vd, 'vs2, 'vs1'vm");
2302 Format(instr, "vcompress.vm 'vd, 'vs2, 'vs1'vm");
2310 void Decoder::DecodeRvvMVX(Instruction* instr) {
2311 DCHECK_EQ(instr->InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_MVX);
2312 switch (instr->InstructionBits() & kVTypeMask) {
2314 if (instr->Vs2Value() == 0x0) {
2315 Format(instr, "vmv.s.x 'vd, 'rs1");
2321 Format(instr, "vwmul.vx 'vd, 'vs2, 'rs1'vm");
2324 Format(instr, "vwmulu.vx 'vd, 'vs2, 'rs1'vm");
2327 Format(instr, "vmul.vx 'vd, 'vs2, 'rs1'vm");
2330 Format(instr, "vmulhu.vx 'vd, 'vs2, 'rs1'vm");
2333 Format(instr, "vdiv.vx 'vd, 'vs2, 'rs1'vm");
2336 Format(instr, "vdivu.vx 'vd, 'vs2, 'rs1'vm");
2339 Format(instr, "vwaddu.wx 'vd, 'vs2, 'rs1'vm");
2342 Format(instr, "vwaddu.vx 'vd, 'vs2, 'rs1'vm");
2345 Format(instr, "vwadd.vx 'vd, 'vs2, 'rs1'vm");
2353 void Decoder::DecodeRvvFVV(Instruction* instr) {
2354 DCHECK_EQ(instr->InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_FVV);
2355 switch (instr->InstructionBits() & kVTypeMask) {
2357 switch (instr->Vs1Value()) {
2359 Format(instr, "vfcvt.xu.f.v 'vd, 'vs2'vm");
2362 Format(instr, "vfcvt.x.f.v 'vd, 'vs2'vm");
2365 Format(instr, "vfncvt.f.f.w 'vd, 'vs2'vm");
2368 Format(instr, "vfncvt.x.f.w 'vd, 'vs2'vm");
2371 Format(instr, "vfncvt.xu.f.w 'vd, 'vs2'vm");
2374 Format(instr, "vfcvt.f.x.v 'vd, 'vs2'vm");
2377 Format(instr, "vfcvt.f.xu.v 'vd, 'vs2'vm");
2380 Format(instr, "vfwcvt.xu.f.v 'vd, 'vs2'vm");
2383 Format(instr, "vfwcvt.x.f.v 'vd, 'vs2'vm");
2386 Format(instr, "vfwcvt.f.x.v 'vd, 'vs2'vm");
2389 Format(instr, "vfwcvt.f.xu.v 'vd, 'vs2'vm");
2392 Format(instr, "vfwcvt.f.f.v 'vd, 'vs2'vm");
2400 switch (instr->Vs1Value()) {
2402 Format(instr, "vfclass.v 'vd, 'vs2'vm");
2405 Format(instr, "vfsqrt.v 'vd, 'vs2'vm");
2408 Format(instr, "vfrsqrt7.v 'vd, 'vs2'vm");
2411 Format(instr, "vfrec7.v 'vd, 'vs2'vm");
2418 Format(instr, "vmfeq.vv 'vd, 'vs2, 'vs1'vm");
2421 Format(instr, "vmfne.vv 'vd, 'vs2, 'vs1'vm");
2424 Format(instr, "vmflt.vv 'vd, 'vs2, 'vs1'vm");
2427 Format(instr, "vmfle.vv 'vd, 'vs2, 'vs1'vm");
2430 Format(instr, "vfmax.vv 'vd, 'vs2, 'vs1'vm");
2433 Format(instr, "vfredmax.vs 'vd, 'vs2, 'vs1'vm");
2436 Format(instr, "vfmin.vv 'vd, 'vs2, 'vs1'vm");
2439 Format(instr, "vfsgnj.vv 'vd, 'vs2, 'vs1'vm");
2442 if (instr->Vs1Value() == instr->Vs2Value()) {
2443 Format(instr, "vneg.vv 'vd, 'vs1'vm");
2445 Format(instr, "vfsgnjn.vv 'vd, 'vs2, 'vs1'vm");
2449 if (instr->Vs1Value() == instr->Vs2Value()) {
2450 Format(instr, "vabs.vv 'vd, 'vs1'vm");
2452 Format(instr, "vfsgnjn.vv 'vd, 'vs2, 'vs1'vm");
2456 Format(instr, "vfadd.vv 'vd, 'vs2, 'vs1'vm");
2459 Format(instr, "vfsub.vv 'vd, 'vs2, 'vs1'vm");
2462 Format(instr, "vfdiv.vv 'vd, 'vs2, 'vs1'vm");
2465 Format(instr, "vfmul.vv 'vd, 'vs2, 'vs1'vm");
2468 Format(instr, "vfmadd.vv 'vd, 'vs1, 'vs2'vm");
2471 Format(instr, "vfnmadd.vv 'vd, 'vs1, 'vs2'vm");
2474 Format(instr, "vfmsub.vv 'vd, 'vs1, 'vs2'vm");
2477 Format(instr, "vfnmsub.vv 'vd, 'vs1, 'vs2'vm");
2480 Format(instr, "vfmacc.vv 'vd, 'vs1, 'vs2'vm");
2483 Format(instr, "vfnmacc.vv 'vd, 'vs1, 'vs2'vm");
2486 Format(instr, "vfmsac.vv 'vd, 'vs1, 'vs2'vm");
2489 Format(instr, "vfnmsac.vv 'vd, 'vs1, 'vs2'vm");
2492 if (instr->Vs1Value() == 0x0) {
2493 Format(instr, "vfmv.f.s 'fd, 'vs2");
2499 Format(instr, "vfwadd.vv 'vd, 'vs2, 'vs1'vm");
2502 Format(instr, "vfwsub.vv 'vd, 'vs2, 'vs1'vm");
2505 Format(instr, "vfwadd.wv 'vd, 'vs2, 'vs1'vm");
2508 Format(instr, "vfwsub.wv 'vd, 'vs2, 'vs1'vm");
2511 Format(instr, "vfwredusum.vs 'vd, 'vs2, 'vs1'vm");
2514 Format(instr, "vfwredosum.vs 'vd, 'vs2, 'vs1'vm");
2517 Format(instr, "vfwmul.vv 'vd, 'vs2, 'vs1'vm");
2520 Format(instr, "vfwmacc.vv 'vd, 'vs1, 'vs2'vm");
2523 Format(instr, "vfwnmacc.vv 'vd, 'vs1, 'vs2'vm");
2526 Format(instr, "vfwmsac.vv 'vd, 'vs1, 'vs2'vm");
2529 Format(instr, "vfwnmsac.vv 'vd, 'vs1, 'vs2'vm");
2537 void Decoder::DecodeRvvFVF(Instruction* instr) {
2538 DCHECK_EQ(instr->InstructionBits() & (kBaseOpcodeMask | kFunct3Mask), OP_FVF);
2539 switch (instr->InstructionBits() & kVTypeMask) {
2541 Format(instr, "vfsgnj.vf 'vd, 'vs2, 'fs1'vm");
2544 Format(instr, "vfsgnjn.vf 'vd, 'vs2, 'fs1'vm");
2547 Format(instr, "vfsgnjn.vf 'vd, 'vs2, 'fs1'vm");
2550 Format(instr, "vfmv.v.f 'vd, 'fs1");
2553 Format(instr, "vfmadd.vf 'vd, 'fs1, 'vs2'vm");
2556 Format(instr, "vfnmadd.vf 'vd, 'fs1, 'vs2'vm");
2559 Format(instr, "vfmsub.vf 'vd, 'fs1, 'vs2'vm");
2562 Format(instr, "vfnmsub.vf 'vd, 'fs1, 'vs2'vm");
2565 Format(instr, "vfmacc.vf 'vd, 'fs1, 'vs2'vm");
2568 Format(instr, "vfnmacc.vf 'vd, 'fs1, 'vs2'vm");
2571 Format(instr, "vfmsac.vf 'vd, 'fs1, 'vs2'vm");
2574 Format(instr, "vfnmsac.vf 'vd, 'fs1, 'vs2'vm");
2577 Format(instr, "vfwadd.vf 'vd, 'vs2, 'fs1'vm");
2580 Format(instr, "vfwsub.vf 'vd, 'vs2, 'fs1'vm");
2583 Format(instr, "vfwadd.wf 'vd, 'vs2, 'fs1'vm");
2586 Format(instr, "vfwsub.wf 'vd, 'vs2, 'fs1'vm");
2589 Format(instr, "vfwmul.vf 'vd, 'vs2, 'fs1'vm");
2592 Format(instr, "vfwmacc.vf 'vd, 'fs1, 'vs2'vm");
2595 Format(instr, "vfwnmacc.vf 'vd, 'fs1, 'vs2'vm");
2598 Format(instr, "vfwmsac.vf 'vd, 'fs1, 'vs2'vm");
2601 Format(instr, "vfwnmsac.vf 'vd, 'fs1, 'vs2'vm");
2609 void Decoder::DecodeVType(Instruction* instr) {
2610 switch (instr->InstructionBits() & (kBaseOpcodeMask | kFunct3Mask)) {
2612 DecodeRvvIVV(instr);
2615 DecodeRvvFVV(instr);
2618 DecodeRvvMVV(instr);
2621 DecodeRvvIVI(instr);
2624 DecodeRvvIVX(instr);
2627 DecodeRvvFVF(instr);
2630 DecodeRvvMVX(instr);
2633 switch (instr->InstructionBits() &
2636 Format(instr, "vsetvli 'rd, 'rs1, 'sew, 'lmul");
2639 if (!(instr->InstructionBits() & 0x40000000)) {
2640 Format(instr, "vsetvl 'rd, 'rs1, 'rs2");
2642 Format(instr, "vsetivli 'rd, 'uimm, 'sew, 'lmul");
2650 int Decoder::switch_nf(Instruction* instr) {
2652 switch (instr->InstructionBits() & kRvvNfMask) {
2677 void Decoder::DecodeRvvVL(Instruction* instr) {
2680 instr->InstructionBits() & (kRvvMopMask | kRvvNfMask | kBaseOpcodeMask);
2681 // switch (instr->InstructionBits() &
2684 if (!(instr->InstructionBits() & (kRvvRs2Mask))) {
2686 instr->vl_vs_width());
2687 Format(instr, str);
2690 instr->vl_vs_width());
2691 Format(instr, str);
2695 instr->vl_vs_width());
2696 Format(instr, str);
2700 instr->vl_vs_width());
2701 Format(instr, str);
2706 if (!(instr->InstructionBits() & (kRvvRs2Mask))) {
2708 switch_nf(instr), instr->vl_vs_width());
2711 switch_nf(instr), instr->vl_vs_width());
2713 Format(instr, str);
2719 switch_nf(instr), instr->vl_vs_width());
2720 Format(instr, str);
2726 switch_nf(instr), instr->vl_vs_width());
2727 Format(instr, str);
2731 int Decoder::switch_sew(Instruction* instr) {
2733 if ((instr->InstructionBits() & kBaseOpcodeMask) != LOAD_FP &&
2734 (instr->InstructionBits() & kBaseOpcodeMask) != STORE_FP)
2736 switch (instr->InstructionBits() & (kRvvWidthMask | kRvvMewMask)) {
2768 void Decoder::DecodeRvvVS(Instruction* instr) {
2771 instr->InstructionBits() & (kRvvMopMask | kRvvNfMask | kBaseOpcodeMask);
2774 instr->vl_vs_width());
2775 Format(instr, str);
2778 instr->vl_vs_width());
2779 Format(instr, str);
2782 instr->vl_vs_width());
2783 Format(instr, str);
2786 instr->vl_vs_width());
2787 Format(instr, str);
2793 switch_nf(instr), instr->vl_vs_width());
2794 Format(instr, str);
2800 switch_nf(instr), instr->vl_vs_width());
2801 Format(instr, str);
2807 switch_nf(instr), instr->vl_vs_width());
2808 Format(instr, str);
2817 Instruction* instr = Instruction::At(instr_ptr);
2820 "%08x ", instr->InstructionBits());
2821 switch (instr->InstructionType()) {
2823 DecodeRType(instr);
2826 DecodeR4Type(instr);
2829 DecodeIType(instr);
2832 DecodeSType(instr);
2835 DecodeBType(instr);
2838 DecodeUType(instr);
2841 DecodeJType(instr);
2844 DecodeCRType(instr);
2847 DecodeCAType(instr);
2850 DecodeCJType(instr);
2853 DecodeCIType(instr);
2856 DecodeCIWType(instr);
2859 DecodeCSSType(instr);
2862 DecodeCLType(instr);
2865 DecodeCSType(instr);
2868 DecodeCBType(instr);
2871 DecodeVType(instr);
2874 Format(instr, "UNSUPPORTED");
2877 return instr->InstructionSize();