Lines Matching defs:instr

78   int FormatVFPRegister(Instruction* instr, const char* format,
80 void PrintMovwMovt(Instruction* instr);
81 int FormatVFPinstruction(Instruction* instr, const char* format);
82 void PrintCondition(Instruction* instr);
83 void PrintShiftRm(Instruction* instr);
84 void PrintShiftImm(Instruction* instr);
85 void PrintShiftSat(Instruction* instr);
86 void PrintPU(Instruction* instr);
90 int FormatRegister(Instruction* instr, const char* option);
93 int FormatOption(Instruction* instr, const char* option);
94 void Format(Instruction* instr, const char* format);
95 void Unknown(Instruction* instr);
101 void DecodeType01(Instruction* instr);
102 void DecodeType2(Instruction* instr);
103 void DecodeType3(Instruction* instr);
104 void DecodeType4(Instruction* instr);
105 void DecodeType5(Instruction* instr);
106 void DecodeType6(Instruction* instr);
108 int DecodeType7(Instruction* instr);
110 void DecodeTypeCP15(Instruction* instr);
112 void DecodeTypeVFP(Instruction* instr);
113 void DecodeType6CoprocessorIns(Instruction* instr);
115 void DecodeSpecialCondition(Instruction* instr);
118 void DecodeFloatingPointDataProcessing(Instruction* instr);
120 void DecodeUnconditional(Instruction* instr);
122 void DecodeAdvancedSIMDDataProcessing(Instruction* instr);
125 void DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr);
127 void DecodeMemoryHintsAndBarriers(Instruction* instr);
129 void DecodeAdvancedSIMDElementOrStructureLoadStore(Instruction* instr);
131 void DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instruction* instr);
132 void DecodeVCMP(Instruction* instr);
133 void DecodeVCVTBetweenDoubleAndSingle(Instruction* instr);
134 void DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr);
135 void DecodeVmovImmediate(Instruction* instr);
167 void Decoder::PrintCondition(Instruction* instr) {
168 Print(cond_names[instr->ConditionValue()]);
194 void Decoder::PrintShiftRm(Instruction* instr) {
195 ShiftOp shift = instr->ShiftField();
196 int shift_index = instr->ShiftValue();
197 int shift_amount = instr->ShiftAmountValue();
198 int rm = instr->RmValue();
202 if ((instr->RegShiftValue() == 0) && (shift == LSL) && (shift_amount == 0)) {
206 if (instr->RegShiftValue() == 0) {
218 int rs = instr->RsValue();
227 void Decoder::PrintShiftImm(Instruction* instr) {
228 int rotate = instr->RotateValue() * 2;
229 int immed8 = instr->Immed8Value();
235 void Decoder::PrintShiftSat(Instruction* instr) {
236 int shift = instr->Bits(11, 7);
240 shift_names[instr->Bit(6) * 2], instr->Bits(11, 7));
245 void Decoder::PrintPU(Instruction* instr) {
246 switch (instr->PUField()) {
294 int Decoder::FormatRegister(Instruction* instr, const char* format) {
297 int reg = instr->RnValue();
301 int reg = instr->RdValue();
305 int reg = instr->RsValue();
309 int reg = instr->RmValue();
313 int reg = instr->RtValue();
319 int rlist = instr->RlistValue();
341 int Decoder::FormatVFPRegister(Instruction* instr, const char* format,
346 reg = instr->VFPNRegValue(precision);
348 reg = instr->VFPMRegValue(precision);
350 if ((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) &&
351 (instr->Bits(11, 9) == 0x5) && (instr->Bit(4) == 0x1)) {
353 reg = instr->Bits(19, 16) | (instr->Bit(7) << 4);
355 reg = instr->VFPDRegValue(precision);
360 int immed8 = instr->Immed8Value();
381 int Decoder::FormatVFPinstruction(Instruction* instr, const char* format) {
421 void Decoder::PrintMovwMovt(Instruction* instr) {
422 int imm = instr->ImmedMovwMovtValue();
423 int rd = instr->RdValue();
434 int Decoder::FormatOption(Instruction* instr, const char* format) {
437 if (instr->Bit(21) == 0) {
445 if (instr->HasB()) {
452 PrintCondition(instr);
456 double d = instr->DoubleImmedVmov().get_scalar();
462 uint32_t lsbit = instr->Bits(11, 7);
463 uint32_t width = instr->Bits(20, 16) + 1;
464 if (instr->Bit(21) == 0) {
476 if (instr->HasH()) {
493 instr->Bits(width + lsb - 1, lsb));
497 if (instr->HasLink()) {
505 PrintMovwMovt(instr);
510 if (instr->HasL()) {
513 if ((instr->Bits(27, 25) == 0) && (instr->Bit(20) == 0) &&
514 (instr->Bits(7, 6) == 3) && (instr->Bit(4) == 1)) {
515 if (instr->Bit(5) == 1) {
529 reinterpret_cast<byte*>(instr->InstructionBits() & 0x0FFFFFFF);
539 instr->Offset12Value());
546 (instr->Bits(19, 8) << 4) + instr->Bits(3, 0));
551 int offs8 = (instr->ImmedHValue() << 4) | instr->ImmedLValue();
558 PrintPU(instr);
562 return FormatRegister(instr, format);
568 if (instr->TypeValue() == 0) {
569 PrintShiftRm(instr);
571 DCHECK_EQ(instr->TypeValue(), 1);
572 PrintShiftImm(instr);
577 PrintShiftSat(instr);
581 PrintShiftRm(instr);
586 PrintSoftwareInterrupt(instr->SvcValue());
591 if (instr->HasSign()) {
599 int sz = 8 << (format[4] == '2' ? instr->Bits(19, 18)
600 : instr->Bits(21, 20));
609 int mask = instr->Bits(19, 16);
618 if (instr->Bit(22) == 0) {
627 if (instr->HasS()) {
634 int off = (static_cast<uint32_t>(instr->SImmed24Value()) << 2) + 8u;
637 converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + off));
653 if (instr->Bit(22) == 0) {
661 return FormatVFPinstruction(instr, format);
665 int offset = instr->Offset12Value();
666 byte* pc = reinterpret_cast<byte*>(instr) + Instruction::kPcLoadDelta;
668 switch (instr->PUField()) {
687 return FormatVFPRegister(instr, format, kSinglePrecision);
689 return FormatVFPRegister(instr, format, kDoublePrecision);
691 return FormatVFPRegister(instr, format, kSimd128Precision);
693 if (instr->HasW()) {
708 void Decoder::Format(Instruction* instr, const char* format) {
712 format += FormatOption(instr, format);
725 Unknown(instr); \
729 // For currently unimplemented decodings the disassembler calls Unknown(instr)
731 void Decoder::Unknown(Instruction* instr) { Format(instr, "unknown"); }
733 void Decoder::DecodeType01(Instruction* instr) {
734 int type = instr->TypeValue();
735 if ((type == 0) && instr->IsSpecialType0()) {
737 if (instr->Bits(7, 4) == 9) {
738 if (instr->Bit(24) == 0) {
740 if (instr->Bit(23) == 0) {
741 if (instr->Bit(21) == 0) {
745 Format(instr, "mul'cond's 'rn, 'rm, 'rs");
747 if (instr->Bit(22) == 0) {
752 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
758 Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
768 Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs");
771 if (instr->Bits(24, 23) == 3) {
772 if (instr->Bit(20) == 1) {
774 switch (instr->Bits(22, 21)) {
776 Format(instr, "ldrex'cond 'rt, ['rn]");
779 Format(instr, "ldrexd'cond 'rt, ['rn]");
782 Format(instr, "ldrexb'cond 'rt, ['rn]");
785 Format(instr, "ldrexh'cond 'rt, ['rn]");
794 switch (instr->Bits(22, 21)) {
796 Format(instr, "strex'cond 'rd, 'rm, ['rn]");
799 Format(instr, "strexd'cond 'rd, 'rm, ['rn]");
802 Format(instr, "strexb'cond 'rd, 'rm, ['rn]");
805 Format(instr, "strexh'cond 'rd, 'rm, ['rn]");
812 Unknown(instr); // not used by V8
815 } else if ((instr->Bit(20) == 0) && ((instr->Bits(7, 4) & 0xD) == 0xD)) {
817 switch (instr->PUField()) {
819 if (instr->Bit(22) == 0) {
820 Format(instr, "'memop'cond's 'rd, ['rn], -'rm");
822 Format(instr, "'memop'cond's 'rd, ['rn], #-'off8");
827 if (instr->Bit(22) == 0) {
828 Format(instr, "'memop'cond's 'rd, ['rn], +'rm");
830 Format(instr, "'memop'cond's 'rd, ['rn], #+'off8");
835 if (instr->Bit(22) == 0) {
836 Format(instr, "'memop'cond's 'rd, ['rn, -'rm]'w");
838 Format(instr, "'memop'cond's 'rd, ['rn, #-'off8]'w");
843 if (instr->Bit(22) == 0) {
844 Format(instr, "'memop'cond's 'rd, ['rn, +'rm]'w");
846 Format(instr, "'memop'cond's 'rd, ['rn, #+'off8]'w");
857 switch (instr->PUField()) {
859 if (instr->Bit(22) == 0) {
860 Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
862 Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
867 if (instr->Bit(22) == 0) {
868 Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
870 Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
875 if (instr->Bit(22) == 0) {
876 Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
878 Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
883 if (instr->Bit(22) == 0) {
884 Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
886 Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
897 } else if ((type == 0) && instr->IsMiscType0()) {
898 if ((instr->Bits(27, 23) == 2) && (instr->Bits(21, 20) == 2) &&
899 (instr->Bits(15, 4) == 0xF00)) {
900 Format(instr, "msr'cond 'spec_reg'spec_reg_fields, 'rm");
901 } else if ((instr->Bits(27, 23) == 2) && (instr->Bits(21, 20) == 0) &&
902 (instr->Bits(11, 0) == 0)) {
903 Format(instr, "mrs'cond 'rd, 'spec_reg");
904 } else if (instr->Bits(22, 21) == 1) {
905 switch (instr->BitField(7, 4)) {
907 Format(instr, "bx'cond 'rm");
910 Format(instr, "blx'cond 'rm");
913 Format(instr, "bkpt 'off0to3and8to19");
916 Unknown(instr); // not used by V8
919 } else if (instr->Bits(22, 21) == 3) {
920 switch (instr->BitField(7, 4)) {
922 Format(instr, "clz'cond 'rd, 'rm");
925 Unknown(instr); // not used by V8
929 Unknown(instr); // not used by V8
931 } else if ((type == 1) && instr->IsNopLikeType1()) {
932 if (instr->BitField(7, 0) == 0) {
933 Format(instr, "nop'cond");
934 } else if (instr->BitField(7, 0) == 20) {
935 Format(instr, "csdb");
937 Unknown(instr); // Not used in V8.
940 switch (instr->OpcodeField()) {
942 Format(instr, "and'cond's 'rd, 'rn, 'shift_op");
946 Format(instr, "eor'cond's 'rd, 'rn, 'shift_op");
950 Format(instr, "sub'cond's 'rd, 'rn, 'shift_op");
954 Format(instr, "rsb'cond's 'rd, 'rn, 'shift_op");
958 Format(instr, "add'cond's 'rd, 'rn, 'shift_op");
962 Format(instr, "adc'cond's 'rd, 'rn, 'shift_op");
966 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_op");
970 Format(instr, "rsc'cond's 'rd, 'rn, 'shift_op");
974 if (instr->HasS()) {
975 Format(instr, "tst'cond 'rn, 'shift_op");
977 Format(instr, "movw'cond 'mw");
982 if (instr->HasS()) {
983 Format(instr, "teq'cond 'rn, 'shift_op");
992 if (instr->HasS()) {
993 Format(instr, "cmp'cond 'rn, 'shift_op");
995 Format(instr, "movt'cond 'mw");
1000 if (instr->HasS()) {
1001 Format(instr, "cmn'cond 'rn, 'shift_op");
1010 Format(instr, "orr'cond's 'rd, 'rn, 'shift_op");
1014 Format(instr, "mov'cond's 'rd, 'shift_op");
1018 Format(instr, "bic'cond's 'rd, 'rn, 'shift_op");
1022 Format(instr, "mvn'cond's 'rd, 'shift_op");
1033 void Decoder::DecodeType2(Instruction* instr) {
1034 switch (instr->PUField()) {
1036 if (instr->HasW()) {
1037 Unknown(instr); // not used in V8
1040 Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
1044 if (instr->HasW()) {
1045 Unknown(instr); // not used in V8
1048 Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
1052 if (instr->HasL() && (instr->RnValue() == kPCRegister)) {
1053 Format(instr, "'memop'cond'b 'rd, [pc, #-'off12]'w (addr 'A)");
1055 Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
1060 if (instr->HasL() && (instr->RnValue() == kPCRegister)) {
1061 Format(instr, "'memop'cond'b 'rd, [pc, #+'off12]'w (addr 'A)");
1063 Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
1074 void Decoder::DecodeType3(Instruction* instr) {
1075 switch (instr->PUField()) {
1077 VERIFY(!instr->HasW());
1078 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
1082 if (instr->Bit(4) == 0) {
1083 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
1085 if (instr->Bit(5) == 0) {
1086 switch (instr->Bits(22, 21)) {
1088 if (instr->Bit(20) == 0) {
1089 if (instr->Bit(6) == 0) {
1090 Format(instr, "pkhbt'cond 'rd, 'rn, 'rm, lsl #'imm05@07");
1092 if (instr->Bits(11, 7) == 0) {
1093 Format(instr, "pkhtb'cond 'rd, 'rn, 'rm, asr #32");
1095 Format(instr, "pkhtb'cond 'rd, 'rn, 'rm, asr #'imm05@07");
1107 Format(instr, "usat 'rd, #'imm05@16, 'rm'shift_sat");
1111 switch (instr->Bits(22, 21)) {
1115 if (instr->Bits(9, 6) == 1) {
1116 if (instr->Bit(20) == 0) {
1117 if (instr->Bits(19, 16) == 0xF) {
1118 switch (instr->Bits(11, 10)) {
1120 Format(instr, "sxtb'cond 'rd, 'rm");
1123 Format(instr, "sxtb'cond 'rd, 'rm, ror #8");
1126 Format(instr, "sxtb'cond 'rd, 'rm, ror #16");
1129 Format(instr, "sxtb'cond 'rd, 'rm, ror #24");
1133 switch (instr->Bits(11, 10)) {
1135 Format(instr, "sxtab'cond 'rd, 'rn, 'rm");
1138 Format(instr, "sxtab'cond 'rd, 'rn, 'rm, ror #8");
1141 Format(instr, "sxtab'cond 'rd, 'rn, 'rm, ror #16");
1144 Format(instr, "sxtab'cond 'rd, 'rn, 'rm, ror #24");
1149 if (instr->Bits(19, 16) == 0xF) {
1150 switch (instr->Bits(11, 10)) {
1152 Format(instr, "sxth'cond 'rd, 'rm");
1155 Format(instr, "sxth'cond 'rd, 'rm, ror #8");
1158 Format(instr, "sxth'cond 'rd, 'rm, ror #16");
1161 Format(instr, "sxth'cond 'rd, 'rm, ror #24");
1165 switch (instr->Bits(11, 10)) {
1167 Format(instr, "sxtah'cond 'rd, 'rn, 'rm");
1170 Format(instr, "sxtah'cond 'rd, 'rn, 'rm, ror #8");
1173 Format(instr, "sxtah'cond 'rd, 'rn, 'rm, ror #16");
1176 Format(instr, "sxtah'cond 'rd, 'rn, 'rm, ror #24");
1181 } else if (instr->Bits(27, 16) == 0x6BF &&
1182 instr->Bits(11, 4) == 0xF3) {
1183 Format(instr, "rev'cond 'rd, 'rm");
1189 if ((instr->Bit(20) == 0) && (instr->Bits(9, 6) == 1)) {
1190 if (instr->Bits(19, 16) == 0xF) {
1191 switch (instr->Bits(11, 10)) {
1193 Format(instr, "uxtb16'cond 'rd, 'rm");
1196 Format(instr, "uxtb16'cond 'rd, 'rm, ror #8");
1199 Format(instr, "uxtb16'cond 'rd, 'rm, ror #16");
1202 Format(instr, "uxtb16'cond 'rd, 'rm, ror #24");
1213 if ((instr->Bits(9, 6) == 1)) {
1214 if ((instr->Bit(20) == 0)) {
1215 if (instr->Bits(19, 16) == 0xF) {
1216 switch (instr->Bits(11, 10)) {
1218 Format(instr, "uxtb'cond 'rd, 'rm");
1221 Format(instr, "uxtb'cond 'rd, 'rm, ror #8");
1224 Format(instr, "uxtb'cond 'rd, 'rm, ror #16");
1227 Format(instr, "uxtb'cond 'rd, 'rm, ror #24");
1231 switch (instr->Bits(11, 10)) {
1233 Format(instr, "uxtab'cond 'rd, 'rn, 'rm");
1236 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #8");
1239 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #16");
1242 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #24");
1247 if (instr->Bits(19, 16) == 0xF) {
1248 switch (instr->Bits(11, 10)) {
1250 Format(instr, "uxth'cond 'rd, 'rm");
1253 Format(instr, "uxth'cond 'rd, 'rm, ror #8");
1256 Format(instr, "uxth'cond 'rd, 'rm, ror #16");
1259 Format(instr, "uxth'cond 'rd, 'rm, ror #24");
1263 switch (instr->Bits(11, 10)) {
1265 Format(instr, "uxtah'cond 'rd, 'rn, 'rm");
1268 Format(instr, "uxtah'cond 'rd, 'rn, 'rm, ror #8");
1271 Format(instr, "uxtah'cond 'rd, 'rn, 'rm, ror #16");
1274 Format(instr, "uxtah'cond 'rd, 'rn, 'rm, ror #24");
1281 if ((instr->Bits(20, 16) == 0x1F) &&
1282 (instr->Bits(11, 4) == 0xF3)) {
1283 Format(instr, "rbit'cond 'rd, 'rm");
1295 if (instr->Bits(22, 20) == 0x5) {
1296 if (instr->Bits(7, 4) == 0x1) {
1297 if (instr->Bits(15, 12) == 0xF) {
1298 Format(instr, "smmul'cond 'rn, 'rm, 'rs");
1301 Format(instr, "smmla'cond 'rn, 'rm, 'rs, 'rd");
1306 if (instr->Bits(5, 4) == 0x1) {
1307 if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) {
1308 if (instr->Bit(21) == 0x1) {
1310 Format(instr, "udiv'cond'b 'rn, 'rm, 'rs");
1313 Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs");
1318 Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
1322 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
1323 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
1324 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
1327 if (instr->Bit(22)) {
1328 Format(instr, "ubfx'cond 'rd, 'rm, 'f");
1330 Format(instr, "sbfx'cond 'rd, 'rm, 'f");
1335 } else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) {
1336 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
1337 uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16));
1339 if (instr->RmValue() == 15) {
1340 Format(instr, "bfc'cond 'rd, 'f");
1342 Format(instr, "bfi'cond 'rd, 'rm, 'f");
1348 Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
1359 void Decoder::DecodeType4(Instruction* instr) {
1360 if (instr->Bit(22) != 0) {
1362 Unknown(instr);
1364 if (instr->HasL()) {
1365 Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
1367 Format(instr, "stm'cond'pu 'rn'w, 'rlist");
1372 void Decoder::DecodeType5(Instruction* instr) {
1373 Format(instr, "b'l'cond 'target");
1376 void Decoder::DecodeType6(Instruction* instr) {
1377 DecodeType6CoprocessorIns(instr);
1380 int Decoder::DecodeType7(Instruction* instr) {
1381 if (instr->Bit(24) == 1) {
1382 if (instr->SvcValue() >= kStopCode) {
1383 Format(instr, "stop'cond 'svc");
1385 Format(instr, "svc'cond 'svc");
1388 switch (instr->CoprocessorValue()) {
1391 DecodeTypeVFP(instr);
1394 DecodeTypeCP15(instr);
1397 Unknown(instr);
1404 // void Decoder::DecodeTypeVFP(Instruction* instr)
1435 void Decoder::DecodeTypeVFP(Instruction* instr) {
1436 VERIFY((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0));
1437 VERIFY(instr->Bits(11, 9) == 0x5);
1439 if (instr->Bit(4) == 0) {
1440 if (instr->Opc1Value() == 0x7) {
1442 if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x1)) {
1444 if (instr->SzValue() == 0x1) {
1445 Format(instr, "vmov'cond.f64 'Dd, 'Dm");
1447 Format(instr, "vmov'cond.f32 'Sd, 'Sm");
1449 } else if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x3)) {
1451 if (instr->SzValue() == 0x1) {
1452 Format(instr, "vabs'cond.f64 'Dd, 'Dm");
1454 Format(instr, "vabs'cond.f32 'Sd, 'Sm");
1456 } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) {
1458 if (instr->SzValue() == 0x1) {
1459 Format(instr, "vneg'cond.f64 'Dd, 'Dm");
1461 Format(instr, "vneg'cond.f32 'Sd, 'Sm");
1463 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) {
1464 DecodeVCVTBetweenDoubleAndSingle(instr);
1465 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) {
1466 DecodeVCVTBetweenFloatingPointAndInteger(instr);
1467 } else if ((instr->Opc2Value() == 0xA) && (instr->Opc3Value() == 0x3) &&
1468 (instr->Bit(8) == 1)) {
1470 int fraction_bits = 32 - ((instr->Bits(3, 0) << 1) | instr->Bit(5));
1471 Format(instr, "vcvt'cond.f64.s32 'Dd, 'Dd");
1474 } else if (((instr->Opc2Value() >> 1) == 0x6) &&
1475 (instr->Opc3Value() & 0x1)) {
1476 DecodeVCVTBetweenFloatingPointAndInteger(instr);
1477 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
1478 (instr->Opc3Value() & 0x1)) {
1479 DecodeVCMP(instr);
1480 } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) {
1481 if (instr->SzValue() == 0x1) {
1482 Format(instr, "vsqrt'cond.f64 'Dd, 'Dm");
1484 Format(instr, "vsqrt'cond.f32 'Sd, 'Sm");
1486 } else if (instr->Opc3Value() == 0x0) {
1487 if (instr->SzValue() == 0x1) {
1488 Format(instr, "vmov'cond.f64 'Dd, 'd");
1490 Format(instr, "vmov'cond.f32 'Sd, 'd");
1492 } else if (((instr->Opc2Value() == 0x6)) && instr->Opc3Value() == 0x3) {
1494 if (instr->SzValue() == 0x1) {
1495 Format(instr, "vrintz'cond.f64.f64 'Dd, 'Dm");
1497 Format(instr, "vrintz'cond.f32.f32 'Sd, 'Sm");
1500 Unknown(instr); // Not used by V8.
1502 } else if (instr->Opc1Value() == 0x3) {
1503 if (instr->SzValue() == 0x1) {
1504 if (instr->Opc3Value() & 0x1) {
1505 Format(instr, "vsub'cond.f64 'Dd, 'Dn, 'Dm");
1507 Format(instr, "vadd'cond.f64 'Dd, 'Dn, 'Dm");
1510 if (instr->Opc3Value() & 0x1) {
1511 Format(instr, "vsub'cond.f32 'Sd, 'Sn, 'Sm");
1513 Format(instr, "vadd'cond.f32 'Sd, 'Sn, 'Sm");
1516 } else if ((instr->Opc1Value() == 0x2) && !(instr->Opc3Value() & 0x1)) {
1517 if (instr->SzValue() == 0x1) {
1518 Format(instr, "vmul'cond.f64 'Dd, 'Dn, 'Dm");
1520 Format(instr, "vmul'cond.f32 'Sd, 'Sn, 'Sm");
1522 } else if ((instr->Opc1Value() == 0x0) && !(instr->Opc3Value() & 0x1)) {
1523 if (instr->SzValue() == 0x1) {
1524 Format(instr, "vmla'cond.f64 'Dd, 'Dn, 'Dm");
1526 Format(instr, "vmla'cond.f32 'Sd, 'Sn, 'Sm");
1528 } else if ((instr->Opc1Value() == 0x0) && (instr->Opc3Value() & 0x1)) {
1529 if (instr->SzValue() == 0x1) {
1530 Format(instr, "vmls'cond.f64 'Dd, 'Dn, 'Dm");
1532 Format(instr, "vmls'cond.f32 'Sd, 'Sn, 'Sm");
1534 } else if ((instr->Opc1Value() == 0x4) && !(instr->Opc3Value() & 0x1)) {
1535 if (instr->SzValue() == 0x1) {
1536 Format(instr, "vdiv'cond.f64 'Dd, 'Dn, 'Dm");
1538 Format(instr, "vdiv'cond.f32 'Sd, 'Sn, 'Sm");
1541 Unknown(instr); // Not used by V8.
1544 if ((instr->VCValue() == 0x0) && (instr->VAValue() == 0x0)) {
1545 DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr);
1546 } else if ((instr->VLValue() == 0x0) && (instr->VCValue() == 0x1)) {
1547 const char* rt_name = converter_.NameOfCPURegister(instr->RtValue());
1548 if (instr->Bit(23) == 0) {
1549 int opc1_opc2 = (instr->Bits(22, 21) << 2) | instr->Bits(6, 5);
1552 if (instr->Bit(21) == 0x0) {
1553 Format(instr, "vmov'cond.32 'Dd[0], 'rt");
1555 Format(instr, "vmov'cond.32 'Dd[1], 'rt");
1558 int vd = instr->VFPNRegValue(kDoublePrecision);
1572 Unknown(instr);
1577 if (instr->Bit(5) != 0) {
1579 } else if (instr->Bit(22) != 0) {
1582 int Vd = instr->VFPNRegValue(kSimd128Precision);
1586 } else if ((instr->VLValue() == 0x1) && (instr->VCValue() == 0x1)) {
1587 int opc1_opc2 = (instr->Bits(22, 21) << 2) | instr->Bits(6, 5);
1590 if (instr->Bit(21) == 0x0) {
1591 Format(instr, "vmov'cond.32 'rt, 'Dd[0]");
1593 Format(instr, "vmov'cond.32 'rt, 'Dd[1]");
1596 char sign = instr->Bit(23) != 0 ? 'u' : 's';
1597 const char* rt_name = converter_.NameOfCPURegister(instr->RtValue());
1598 int vn = instr->VFPNRegValue(kDoublePrecision);
1612 Unknown(instr);
1615 } else if ((instr->VCValue() == 0x0) && (instr->VAValue() == 0x7) &&
1616 (instr->Bits(19, 16) == 0x1)) {
1617 if (instr->VLValue() == 0) {
1618 if (instr->Bits(15, 12) == 0xF) {
1619 Format(instr, "vmsr'cond FPSCR, APSR");
1621 Format(instr, "vmsr'cond FPSCR, 'rt");
1624 if (instr->Bits(15, 12) == 0xF) {
1625 Format(instr, "vmrs'cond APSR, FPSCR");
1627 Format(instr, "vmrs'cond 'rt, FPSCR");
1631 Unknown(instr); // Not used by V8.
1636 void Decoder::DecodeTypeCP15(Instruction* instr) {
1637 VERIFY((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0));
1638 VERIFY(instr->CoprocessorValue() == 15);
1640 if (instr->Bit(4) == 1) {
1641 int crn = instr->Bits(19, 16);
1642 int crm = instr->Bits(3, 0);
1643 int opc1 = instr->Bits(23, 21);
1644 int opc2 = instr->Bits(7, 5);
1649 Format(instr, "mcr'cond (CP15DMB)");
1651 Format(instr, "mcr'cond (CP15DSB)");
1653 Format(instr, "mcr'cond (CP15ISB)");
1655 Unknown(instr);
1658 Unknown(instr);
1661 Unknown(instr);
1666 Instruction* instr) {
1667 VERIFY((instr->Bit(4) == 1) && (instr->VCValue() == 0x0) &&
1668 (instr->VAValue() == 0x0));
1670 bool to_arm_register = (instr->VLValue() == 0x1);
1673 Format(instr, "vmov'cond 'rt, 'Sn");
1675 Format(instr, "vmov'cond 'Sn, 'rt");
1679 void Decoder::DecodeVCMP(Instruction* instr) {
1680 VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
1681 VERIFY(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
1682 (instr->Opc3Value() & 0x1));
1685 bool dp_operation = (instr->SzValue() == 1);
1686 bool raise_exception_for_qnan = (instr->Bit(7) == 0x1);
1689 if (instr->Opc2Value() == 0x4) {
1690 Format(instr, "vcmp'cond.f64 'Dd, 'Dm");
1691 } else if (instr->Opc2Value() == 0x5) {
1692 Format(instr, "vcmp'cond.f64 'Dd, #0.0");
1694 Unknown(instr); // invalid
1697 if (instr->Opc2Value() == 0x4) {
1698 Format(instr, "vcmp'cond.f32 'Sd, 'Sm");
1699 } else if (instr->Opc2Value() == 0x5) {
1700 Format(instr, "vcmp'cond.f32 'Sd, #0.0");
1702 Unknown(instr); // invalid
1705 Unknown(instr); // Not used by V8.
1709 void Decoder::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
1710 VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
1711 VERIFY((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
1713 bool double_to_single = (instr->SzValue() == 1);
1716 Format(instr, "vcvt'cond.f32.f64 'Sd, 'Dm");
1718 Format(instr, "vcvt'cond.f64.f32 'Dd, 'Sm");
1722 void Decoder::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
1723 VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
1724 VERIFY(((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) ||
1725 (((instr->Opc2Value() >> 1) == 0x6) && (instr->Opc3Value() & 0x1)));
1727 bool to_integer = (instr->Bit(18) == 1);
1728 bool dp_operation = (instr->SzValue() == 1);
1730 bool unsigned_integer = (instr->Bit(16) == 0);
1734 Format(instr, "vcvt'cond.u32.f64 'Sd, 'Dm");
1736 Format(instr, "vcvt'cond.s32.f64 'Sd, 'Dm");
1740 Format(instr, "vcvt'cond.u32.f32 'Sd, 'Sm");
1742 Format(instr, "vcvt'cond.s32.f32 'Sd, 'Sm");
1746 bool unsigned_integer = (instr->Bit(7) == 0);
1750 Format(instr, "vcvt'cond.f64.u32 'Dd, 'Sm");
1752 Format(instr, "vcvt'cond.f64.s32 'Dd, 'Sm");
1756 Format(instr, "vcvt'cond.f32.u32 'Sd, 'Sm");
1758 Format(instr, "vcvt'cond.f32.s32 'Sd, 'Sm");
1764 void Decoder::DecodeVmovImmediate(Instruction* instr) {
1765 byte cmode = instr->Bits(11, 8);
1766 int vd = instr->VFPDRegValue(kSimd128Precision);
1767 int a = instr->Bit(24);
1768 int bcd = instr->Bits(18, 16);
1769 int efgh = instr->Bits(3, 0);
1784 Unknown(instr);
1793 void Decoder::DecodeType6CoprocessorIns(Instruction* instr) {
1794 VERIFY(instr->TypeValue() == 6);
1796 if (instr->CoprocessorValue() == 0xA) {
1797 switch (instr->OpcodeValue()) {
1800 if (instr->HasL()) {
1801 Format(instr, "vldr'cond 'Sd, ['rn - 4*'imm08@00]");
1803 Format(instr, "vstr'cond 'Sd, ['rn - 4*'imm08@00]");
1808 if (instr->HasL()) {
1809 Format(instr, "vldr'cond 'Sd, ['rn + 4*'imm08@00]");
1811 Format(instr, "vstr'cond 'Sd, ['rn + 4*'imm08@00]");
1820 bool to_vfp_register = (instr->VLValue() == 0x1);
1822 Format(instr, "vldm'cond'pu 'rn'w, {'Sd-'Sd+}");
1824 Format(instr, "vstm'cond'pu 'rn'w, {'Sd-'Sd+}");
1829 Unknown(instr); // Not used by V8.
1831 } else if (instr->CoprocessorValue() == 0xB) {
1832 switch (instr->OpcodeValue()) {
1835 if (instr->Bits(7, 6) != 0 || instr->Bit(4) != 1) {
1836 Unknown(instr); // Not used by V8.
1837 } else if (instr->HasL()) {
1838 Format(instr, "vmov'cond 'rt, 'rn, 'Dm");
1840 Format(instr, "vmov'cond 'Dm, 'rt, 'rn");
1845 if (instr->HasL()) {
1846 Format(instr, "vldr'cond 'Dd, ['rn - 4*'imm08@00]");
1848 Format(instr, "vstr'cond 'Dd, ['rn - 4*'imm08@00]");
1853 if (instr->HasL()) {
1854 Format(instr, "vldr'cond 'Dd, ['rn + 4*'imm08@00]");
1856 Format(instr, "vstr'cond 'Dd, ['rn + 4*'imm08@00]");
1865 bool to_vfp_register = (instr->VLValue() == 0x1);
1867 Format(instr, "vldm'cond'pu 'rn'w, {'Dd-'Dd+}");
1869 Format(instr, "vstm'cond'pu 'rn'w, {'Dd-'Dd+}");
1874 Unknown(instr); // Not used by V8.
1877 Unknown(instr); // Not used by V8.
1886 void Decoder::DecodeSpecialCondition(Instruction* instr) {
1887 int op0 = instr->Bits(25, 24);
1888 int op1 = instr->Bits(11, 9);
1889 int op2 = instr->Bit(4);
1891 if (instr->Bit(27) == 0) {
1892 DecodeUnconditional(instr);
1893 } else if ((instr->Bits(27, 26) == 0b11) && (op0 == 0b10) &&
1895 DecodeFloatingPointDataProcessing(instr);
1897 Unknown(instr);
1901 void Decoder::DecodeFloatingPointDataProcessing(Instruction* instr) {
1903 int op0 = instr->Bits(23, 20);
1904 int op1 = instr->Bits(19, 16);
1905 int op2 = instr->Bits(9, 8);
1906 int op3 = instr->Bit(6);
1910 bool dp_operation = (instr->SzValue() == 1);
1911 switch (instr->Bits(21, 20)) {
1914 Format(instr, "vseleq.f64 'Dd, 'Dn, 'Dm");
1916 Format(instr, "vseleq.f32 'Sd, 'Sn, 'Sm");
1921 Format(instr, "vselvs.f64 'Dd, 'Dn, 'Dm");
1923 Format(instr, "vselvs.f32 'Sd, 'Sn, 'Sm");
1928 Format(instr, "vselge.f64 'Dd, 'Dn, 'Dm");
1930 Format(instr, "vselge.f32 'Sd, 'Sn, 'Sm");
1935 Format(instr, "vselgt.f64 'Dd, 'Dn, 'Dm");
1937 Format(instr, "vselgt.f32 'Sd, 'Sn, 'Sm");
1943 } else if (instr->Opc1Value() == 0x4 && op2) {
1946 if (instr->SzValue() == 0x1) {
1947 if (instr->Bit(6) == 0x1) {
1948 Format(instr, "vminnm.f64 'Dd, 'Dn, 'Dm");
1950 Format(instr, "vmaxnm.f64 'Dd, 'Dn, 'Dm");
1953 if (instr->Bit(6) == 0x1) {
1954 Format(instr, "vminnm.f32 'Sd, 'Sn, 'Sm");
1956 Format(instr, "vmaxnm.f32 'Sd, 'Sn, 'Sm");
1959 } else if (instr->Opc1Value() == 0x7 && (op1 >> 3) && op2 && op3) {
1962 bool dp_operation = (instr->SzValue() == 1);
1963 int rounding_mode = instr->Bits(17, 16);
1967 Format(instr, "vrinta.f64.f64 'Dd, 'Dm");
1969 Format(instr, "vrinta.f32.f32 'Sd, 'Sm");
1974 Format(instr, "vrintn.f64.f64 'Dd, 'Dm");
1976 Format(instr, "vrintn.f32.f32 'Sd, 'Sm");
1981 Format(instr, "vrintp.f64.f64 'Dd, 'Dm");
1983 Format(instr, "vrintp.f32.f32 'Sd, 'Sm");
1988 Format(instr, "vrintm.f64.f64 'Dd, 'Dm");
1990 Format(instr, "vrintm.f32.f32 'Sd, 'Sm");
1997 Unknown(instr);
2003 void Decoder::DecodeUnconditional(Instruction* instr) {
2005 int op0 = instr->Bits(26, 25);
2006 int op1 = instr->Bit(20);
2014 DecodeAdvancedSIMDDataProcessing(instr);
2016 DecodeMemoryHintsAndBarriers(instr);
2018 DecodeAdvancedSIMDElementOrStructureLoadStore(instr);
2020 Unknown(instr);
2024 void Decoder::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
2025 int op0 = instr->Bit(23);
2026 int op1 = instr->Bit(4);
2030 if (instr->Bit(6) == 0) {
2031 Vm = instr->VFPMRegValue(kDoublePrecision);
2032 Vn = instr->VFPNRegValue(kDoublePrecision);
2034 Vm = instr->VFPMRegValue(kSimd128Precision);
2035 Vn = instr->VFPNRegValue(kSimd128Precision);
2038 int u = instr->Bit(24);
2039 int opc = instr->Bits(11, 8);
2040 int q = instr->Bit(6);
2041 int sz = instr->Bits(21, 20);
2044 Format(instr, "vqadd.s'size3 'Qd, 'Qn, 'Qm");
2047 Format(instr, "vmov 'Qd, 'Qm");
2049 Format(instr, "vorr 'Qd, 'Qn, 'Qm");
2052 Format(instr, "vbic 'Qd, 'Qn, 'Qm");
2054 Format(instr, "vand 'Qd, 'Qn, 'Qm");
2056 Format(instr, "vqsub.s'size3 'Qd, 'Qn, 'Qm");
2058 Format(instr, "vcge.s'size3 'Qd, 'Qn, 'Qm");
2060 Format(instr, "vcgt.s'size3 'Qd, 'Qn, 'Qm");
2062 Format(instr, "vshl.s'size3 'Qd, 'Qm, 'Qn");
2064 Format(instr, "vmin.s'size3 'Qd, 'Qn, 'Qm");
2066 Format(instr, "vmax.s'size3 'Qd, 'Qn, 'Qm");
2068 Format(instr, "vtst.i'size3 'Qd, 'Qn, 'Qm");
2070 Format(instr, "vadd.i'size3 'Qd, 'Qn, 'Qm");
2072 Format(instr, "vmul.i'size3 'Qd, 'Qn, 'Qm");
2074 Format(instr, "vpmin.s'size3 'Dd, 'Dn, 'Dm");
2076 Format(instr, "vpmax.s'size3 'Dd, 'Dn, 'Dm");
2078 Format(instr, "vqrdmulh.s'size3 'Qd, 'Qn, 'Qm");
2080 Format(instr, "vpadd.i'size3 'Dd, 'Dn, 'Dm");
2082 Format(instr, "vadd.f32 'Qd, 'Qn, 'Qm");
2084 Format(instr, "vsub.f32 'Qd, 'Qn, 'Qm");
2086 Format(instr, "vceq.f32 'Qd, 'Qn, 'Qm");
2088 Format(instr, "vrecps.f32 'Qd, 'Qn, 'Qm");
2090 Format(instr, "vrsqrts.f32 'Qd, 'Qn, 'Qm");
2092 Format(instr, "vmax.f32 'Qd, 'Qn, 'Qm");
2094 Format(instr, "vmin.f32 'Qd, 'Qn, 'Qm");
2096 Format(instr, "vqadd.u'size3 'Qd, 'Qn, 'Qm");
2098 Format(instr, "vbsl 'Qd, 'Qn, 'Qm");
2100 Format(instr, "veor 'Qd, 'Qn, 'Qm");
2102 Format(instr, "veor 'Dd, 'Dn, 'Dm");
2104 Format(instr, "vrhadd.u'size3 'Qd, 'Qn, 'Qm");
2106 Format(instr, "vqsub.u'size3 'Qd, 'Qn, 'Qm");
2108 Format(instr, "vcge.u'size3 'Qd, 'Qn, 'Qm");
2110 Format(instr, "vcgt.u'size3 'Qd, 'Qn, 'Qm");
2112 Format(instr, "vshl.u'size3 'Qd, 'Qm, 'Qn");
2114 Format(instr, "vmin.u'size3 'Qd, 'Qn, 'Qm");
2116 Format(instr, "vmax.u'size3 'Qd, 'Qn, 'Qm");
2118 Format(instr, "vceq.i'size3 'Qd, 'Qn, 'Qm");
2120 Format(instr, "vsub.i'size3 'Qd, 'Qn, 'Qm");
2122 Format(instr, "vpmin.u'size3 'Dd, 'Dn, 'Dm");
2124 Format(instr, "vpmax.u'size3 'Dd, 'Dn, 'Dm");
2126 Format(instr, "vmul.f32 'Qd, 'Qn, 'Qm");
2128 Format(instr, "vpadd.f32 'Dd, 'Dn, 'Dm");
2130 Format(instr, "vcge.f32 'Qd, 'Qn, 'Qm");
2132 Format(instr, "vcgt.f32 'Qd, 'Qn, 'Qm");
2134 Unknown(instr);
2137 DecodeAdvancedSIMDTwoOrThreeRegisters(instr);
2140 if (instr->Bits(21, 19) == 0 && instr->Bit(7) == 0) {
2142 DecodeVmovImmediate(instr);
2145 int u = instr->Bit(24);
2146 int imm3H = instr->Bits(21, 19);
2147 int imm3L = instr->Bits(18, 16);
2148 int opc = instr->Bits(11, 8);
2149 int l = instr->Bit(7);
2150 int q = instr->Bit(6);
2155 int imm7 = (l << 6) | instr->Bits(21, 16);
2159 int Vd = instr->VFPDRegValue(kSimd128Precision);
2160 int Vm = instr->VFPMRegValue(kSimd128Precision);
2165 int Vd = instr->VFPDRegValue(kDoublePrecision);
2166 int Vm = instr->VFPMRegValue(kDoublePrecision);
2174 int imm7 = (l << 6) | instr->Bits(21, 16);
2178 int Vd = instr->VFPDRegValue(kSimd128Precision);
2179 int Vm = instr->VFPMRegValue(kSimd128Precision);
2184 int Vd = instr->VFPDRegValue(kDoublePrecision);
2185 int Vm = instr->VFPMRegValue(kDoublePrecision);
2192 if ((instr->VdValue() & 1) != 0) Unknown(instr);
2193 int Vd = instr->VFPDRegValue(kSimd128Precision);
2194 int Vm = instr->VFPMRegValue(kDoublePrecision);
2195 int imm3H = instr->Bits(21, 19);
2201 int imm7 = (l << 6) | instr->Bits(21, 16);
2204 int Vd = instr->VFPDRegValue(kSimd128Precision);
2205 int Vm = instr->VFPMRegValue(kSimd128Precision);
2212 int imm7 = (l << 6) | instr->Bits(21, 16);
2216 if (instr->Bit(8) == 1) {
2223 int Vd = instr->VFPDRegValue(kDoublePrecision);
2224 int Vm = instr->VFPMRegValue(kDoublePrecision);
2231 Unknown(instr);
2235 void Decoder::DecodeAdvancedSIMDTwoOrThreeRegisters(Instruction* instr) {
2237 int op0 = instr->Bit(24);
2238 int op1 = instr->Bits(21, 20);
2239 int op2 = instr->Bits(11, 10);
2240 int op3 = instr->Bit(6);
2243 int imm4 = instr->Bits(11, 8);
2244 int Vd = instr->VFPDRegValue(kSimd128Precision);
2245 int Vm = instr->VFPMRegValue(kSimd128Precision);
2246 int Vn = instr->VFPNRegValue(kSimd128Precision);
2252 int size = instr->Bits(19, 18);
2253 int opc1 = instr->Bits(17, 16);
2254 int opc2 = instr->Bits(10, 7);
2255 int q = instr->Bit(6);
2256 int Vd = instr->VFPDRegValue(q ? kSimd128Precision : kDoublePrecision);
2257 int Vm = instr->VFPMRegValue(q ? kSimd128Precision : kDoublePrecision);
2261 int op = kBitsPerByte << (static_cast<int>(Neon64) - instr->Bits(8, 7));
2267 Format(instr, q ? "vpadal.s'size2 'Qd, 'Qm" : "vpadal.s'size2 'Dd, 'Dm");
2269 Format(instr, q ? "vpadal.u'size2 'Qd, 'Qm" : "vpadal.u'size2 'Dd, 'Dm");
2271 Format(instr, q ? "vpaddl.s'size2 'Qd, 'Qm" : "vpaddl.s'size2 'Dd, 'Dm");
2273 Format(instr, q ? "vpaddl.u'size2 'Qd, 'Qm" : "vpaddl.u'size2 'Dd, 'Dm");
2275 Format(instr, q ? "vswp 'Qd, 'Qm" : "vswp 'Dd, 'Dm");
2278 Format(instr, q ? "vcnt.8 'Qd, 'Qm" : "vcnt.8 'Dd, 'Dm");
2280 Format(instr, "vmvn 'Qd, 'Qm");
2283 Format(instr,
2287 Format(instr,
2290 Format(instr, q ? "vabs.s'size2 'Qd, 'Qm" : "vabs.s.'size2 'Dd, 'Dm");
2292 Format(instr, q ? "vabs.f'size2 'Qd, 'Qm" : "vabs.f.'size2 'Dd, 'Dm");
2294 Format(instr, q ? "vneg.s'size2 'Qd, 'Qm" : "vneg.s.'size2 'Dd, 'Dm");
2296 Format(instr, q ? "vneg.f'size2 'Qd, 'Qm" : "vneg.f.'size2 'Dd, 'Dm");
2298 Format(instr, q ? "vtrn.'size2 'Qd, 'Qm" : "vtrn.'size2 'Dd, 'Dm");
2300 Format(instr, q ? "vuzp.'size2 'Qd, 'Qm" : "vuzp.'size2 'Dd, 'Dm");
2302 Format(instr, q ? "vzip.'size2 'Qd, 'Qm" : "vzip.'size2 'Dd, 'Dm");
2305 int Vd = instr->VFPDRegValue(kDoublePrecision);
2306 int Vm = instr->VFPMRegValue(kSimd128Precision);
2307 int op = instr->Bits(7, 6);
2314 Format(instr, q ? "vrintn.f32 'Qd, 'Qm" : "vrintn.f32 'Dd, 'Dm");
2316 Format(instr, q ? "vrintz.f32 'Qd, 'Qm" : "vrintz.f32 'Dd, 'Dm");
2318 Format(instr, q ? "vrintm.f32 'Qd, 'Qm" : "vrintm.f32 'Qd, 'Qm");
2320 Format(instr, q ? "vrintp.f32 'Qd, 'Qm" : "vrintp.f32 'Qd, 'Qm");
2322 Format(instr, "vrecpe.f32 'Qd, 'Qm");
2324 Format(instr, "vrsqrte.f32 'Qd, 'Qm");
2327 int op = instr->Bits(8, 7);
2347 int Vd = instr->VFPDRegValue(kDoublePrecision);
2348 int Vn = instr->VFPNRegValue(kDoublePrecision);
2349 int Vm = instr->VFPMRegValue(kDoublePrecision);
2350 int len = instr->Bits(9, 8);
2354 instr->Bit(6) == 0 ? "vtbl.8" : "vtbx.8", Vd);
2360 if (instr->Bits(9, 7) == 0) {
2362 int Vm = instr->VFPMRegValue(kDoublePrecision);
2363 int imm4 = instr->Bits(19, 16);
2375 if (instr->Bit(6) == 0) {
2376 int Vd = instr->VFPDRegValue(kDoublePrecision);
2381 int Vd = instr->VFPDRegValue(kSimd128Precision);
2387 Unknown(instr);
2391 int u = instr->Bit(24);
2392 int opc = instr->Bits(11, 8);
2394 Format(instr,
2397 Format(instr,
2402 Unknown(instr);
2404 Unknown(instr);
2408 void Decoder::DecodeMemoryHintsAndBarriers(Instruction* instr) {
2409 int op0 = instr->Bits(25, 21);
2412 int option = instr->Bits(3, 0);
2413 switch (instr->Bits(7, 4)) {
2430 Unknown(instr);
2432 } else if ((op0 & 0b10001) == 0b00000 && !instr->Bit(4)) {
2434 const char* rn_name = converter_.NameOfCPURegister(instr->Bits(19, 16));
2435 int offset = instr->Bits(11, 0);
2439 } else if (instr->Bit(23) == 0) {
2447 Unknown(instr);
2452 Instruction* instr) {
2453 int op0 = instr->Bit(23);
2454 int op1 = instr->Bits(11, 10);
2455 int l = instr->Bit(21);
2456 int n = instr->Bits(9, 8);
2457 int Vd = instr->VFPDRegValue(kDoublePrecision);
2458 int Rn = instr->VnValue();
2459 int Rm = instr->VmValue();
2463 int itype = instr->Bits(11, 8);
2466 int size = instr->Bits(7, 6);
2467 int align = instr->Bits(5, 4);
2475 Unknown(instr);
2481 int size = instr->Bits(7, 6);
2483 int type = instr->Bit(5) ? nlt_2 : nlt_1;
2487 DCHECK_EQ(0, instr->Bit(4)); // Alignment not supported.
2491 Unknown(instr);
2496 int index_align = instr->Bits(7, 4);
2508 Unknown(instr);
2511 Unknown(instr);
2533 Instruction* instr = Instruction::At(reinterpret_cast<Address>(instr_ptr));
2536 "%08x ", instr->InstructionBits());
2537 if (instr->ConditionField() == kSpecialCondition) {
2538 DecodeSpecialCondition(instr);
2548 switch (instr->TypeValue()) {
2551 DecodeType01(instr);
2555 DecodeType2(instr);
2559 DecodeType3(instr);
2563 DecodeType4(instr);
2567 DecodeType5(instr);
2571 DecodeType6(instr);
2575 return DecodeType7(instr);