Lines Matching refs:src2
934 void vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2,
936 void vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2,
940 void vinstr(byte op, Reg1 dst, Reg2 src1, Op src2, SIMDPrefix pp,
993 void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
994 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
996 void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \
997 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
1002 void v##instruction(YMMRegister dst, YMMRegister src1, YMMRegister src2) { \
1003 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX); \
1005 void v##instruction(YMMRegister dst, YMMRegister src1, Operand src2) { \
1006 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX); \
1014 void v##instruction(YMMRegister dst, YMMRegister src1, YMMRegister src2) { \
1015 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1017 void v##instruction(YMMRegister dst, YMMRegister src1, Operand src2) { \
1018 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1027 void v##instruction(YMMRegister dst, YMMRegister src1, XMMRegister src2) { \
1028 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1030 void v##instruction(YMMRegister dst, YMMRegister src1, Operand src2) { \
1031 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1134 void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
1135 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
1137 void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \
1138 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
1140 void v##instruction(YMMRegister dst, YMMRegister src1, YMMRegister src2) { \
1141 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0, \
1144 void v##instruction(YMMRegister dst, YMMRegister src1, Operand src2) { \
1145 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0, \
1172 void vpblendvb(XMMRegister dst, XMMRegister src1, XMMRegister src2,
1174 vinstr(0x4C, dst, src1, src2, k66, k0F3A, kW0);
1178 void vpblendvb(YMMRegister dst, YMMRegister src1, YMMRegister src2,
1180 vinstr(0x4C, dst, src1, src2, k66, k0F3A, kW0, AVX2);
1185 void vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2,
1187 vinstr(0x4A, dst, src1, src2, k66, k0F3A, kW0);
1191 void vblendvps(YMMRegister dst, YMMRegister src1, YMMRegister src2,
1193 vinstr(0x4A, dst, src1, src2, k66, k0F3A, kW0, AVX);
1198 void vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2,
1200 vinstr(0x4B, dst, src1, src2, k66, k0F3A, kW0);
1204 void vblendvpd(YMMRegister dst, YMMRegister src1, YMMRegister src2,
1206 vinstr(0x4B, dst, src1, src2, k66, k0F3A, kW0, AVX);
1371 void fma_instr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2,
1373 void fma_instr(byte op, XMMRegister dst, XMMRegister src1, Operand src2,
1377 void instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
1378 fma_instr(0x##opcode, dst, src1, src2, k##length, k##prefix, \
1381 void instr(XMMRegister dst, XMMRegister src1, Operand src2) { \
1382 fma_instr(0x##opcode, dst, src1, src2, k##length, k##prefix, \
1395 void vmovsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1396 vsd(0x10, dst, src1, src2);
1411 void vmovlps(XMMRegister dst, XMMRegister src1, Operand src2);
1414 void vmovhps(XMMRegister dst, XMMRegister src1, Operand src2);
1418 void v##instr(XMMRegister dst, XMMRegister src2) { \
1419 vps(0x##opcode, dst, xmm0, src2); \
1421 void v##instr(XMMRegister dst, Operand src2) { \
1422 vps(0x##opcode, dst, xmm0, src2); \
1424 void v##instr(YMMRegister dst, YMMRegister src2) { \
1425 vps(0x##opcode, dst, ymm0, src2); \
1427 void v##instr(YMMRegister dst, Operand src2) { \
1428 vps(0x##opcode, dst, ymm0, src2); \
1434 void v##instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
1435 vps(0x##opcode, dst, src1, src2); \
1437 void v##instr(XMMRegister dst, XMMRegister src1, Operand src2) { \
1438 vps(0x##opcode, dst, src1, src2); \
1440 void v##instr(YMMRegister dst, YMMRegister src1, YMMRegister src2) { \
1441 vps(0x##opcode, dst, src1, src2); \
1443 void v##instr(YMMRegister dst, YMMRegister src1, Operand src2) { \
1444 vps(0x##opcode, dst, src1, src2); \
1450 void instr(SIMDRegister dst, SIMDRegister src1, SIMDRegister src2) { \
1451 impl(opcode, dst, src1, src2); \
1453 void instr(SIMDRegister dst, SIMDRegister src1, Operand src2) { \
1454 impl(opcode, dst, src1, src2); \
1461 void v##instr(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
1462 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kWIG); \
1464 void v##instr(XMMRegister dst, XMMRegister src1, Operand src2) { \
1465 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kWIG); \
1482 void vmovlhps(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1483 vinstr(0x16, dst, src1, src2, kNoPrefix, k0F, kWIG);
1485 void vmovhlps(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1486 vinstr(0x12, dst, src1, src2, kNoPrefix, k0F, kWIG);
1494 void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Register src2) {
1495 XMMRegister isrc2 = XMMRegister::from_code(src2.code());
1498 void vcvtlsi2sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1499 vinstr(0x2a, dst, src1, src2, kF2, k0F, kW0);
1501 void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, Register src2) {
1502 XMMRegister isrc2 = XMMRegister::from_code(src2.code());
1505 void vcvtlsi2ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1506 vinstr(0x2a, dst, src1, src2, kF3, k0F, kW0);
1508 void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, Register src2) {
1509 XMMRegister isrc2 = XMMRegister::from_code(src2.code());
1512 void vcvtqsi2ss(XMMRegister dst, XMMRegister src1, Operand src2) {
1513 vinstr(0x2a, dst, src1, src2, kF3, k0F, kW1);
1515 void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Register src2) {
1516 XMMRegister isrc2 = XMMRegister::from_code(src2.code());
1519 void vcvtqsi2sd(XMMRegister dst, XMMRegister src1, Operand src2) {
1520 vinstr(0x2a, dst, src1, src2, kF2, k0F, kW1);
1558 void vroundss(XMMRegister dst, XMMRegister src1, XMMRegister src2,
1560 vinstr(0x0a, dst, src1, src2, k66, k0F3A, kWIG);
1563 void vroundss(XMMRegister dst, XMMRegister src1, Operand src2,
1565 vinstr(0x0a, dst, src1, src2, k66, k0F3A, kWIG);
1568 void vroundsd(XMMRegister dst, XMMRegister src1, XMMRegister src2,
1570 vinstr(0x0b, dst, src1, src2, k66, k0F3A, kWIG);
1573 void vroundsd(XMMRegister dst, XMMRegister src1, Operand src2,
1575 vinstr(0x0b, dst, src1, src2, k66, k0F3A, kWIG);
1596 void vsd(byte op, Reg dst, Reg src1, Op src2) {
1597 vinstr(op, dst, src1, src2, kF2, k0F, kWIG, AVX);
1600 void vmovss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1601 vss(0x10, dst, src1, src2);
1607 void vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
1608 void vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
1610 void vshufps(XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) {
1611 vps(0xC6, dst, src1, src2, imm8);
1613 void vshufps(YMMRegister dst, YMMRegister src1, YMMRegister src2, byte imm8) {
1614 vps(0xC6, dst, src1, src2, imm8);
1650 void vcmpps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int8_t cmp) {
1651 vps(0xC2, dst, src1, src2);
1654 void vcmpps(YMMRegister dst, YMMRegister src1, YMMRegister src2, int8_t cmp) {
1655 vps(0xC2, dst, src1, src2);
1658 void vcmpps(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp) {
1659 vps(0xC2, dst, src1, src2);
1662 void vcmpps(YMMRegister dst, YMMRegister src1, Operand src2, int8_t cmp) {
1663 vps(0xC2, dst, src1, src2);
1666 void vcmppd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int8_t cmp) {
1667 vpd(0xC2, dst, src1, src2);
1670 void vcmppd(YMMRegister dst, YMMRegister src1, YMMRegister src2, int8_t cmp) {
1671 vpd(0xC2, dst, src1, src2);
1674 void vcmppd(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp) {
1675 vpd(0xC2, dst, src1, src2);
1678 void vcmppd(YMMRegister dst, YMMRegister src1, Operand src2, int8_t cmp) {
1679 vpd(0xC2, dst, src1, src2);
1683 void instr##ps(SIMDRegister dst, SIMDRegister src1, SIMDRegister src2) { \
1684 vcmpps(dst, src1, src2, imm8); \
1686 void instr##ps(SIMDRegister dst, SIMDRegister src1, Operand src2) { \
1687 vcmpps(dst, src1, src2, imm8); \
1689 void instr##pd(SIMDRegister dst, SIMDRegister src1, SIMDRegister src2) { \
1690 vcmppd(dst, src1, src2, imm8); \
1692 void instr##pd(SIMDRegister dst, SIMDRegister src1, Operand src2) { \
1693 vcmppd(dst, src1, src2, imm8); \
1718 void vinsertps(XMMRegister dst, XMMRegister src1, XMMRegister src2,
1720 vinstr(0x21, dst, src1, src2, k66, k0F3A, kWIG);
1723 void vinsertps(XMMRegister dst, XMMRegister src1, Operand src2, byte imm8) {
1724 vinstr(0x21, dst, src1, src2, k66, k0F3A, kWIG);
1732 void vpinsrb(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) {
1733 XMMRegister isrc = XMMRegister::from_code(src2.code());
1737 void vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
1738 vinstr(0x20, dst, src1, src2, k66, k0F3A, kW0);
1741 void vpinsrw(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) {
1742 XMMRegister isrc = XMMRegister::from_code(src2.code());
1746 void vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
1747 vinstr(0xc4, dst, src1, src2, k66, k0F, kW0);
1750 void vpinsrd(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) {
1751 XMMRegister isrc = XMMRegister::from_code(src2.code());
1755 void vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
1756 vinstr(0x22, dst, src1, src2, k66, k0F3A, kW0);
1759 void vpinsrq(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) {
1760 XMMRegister isrc = XMMRegister::from_code(src2.code());
1764 void vpinsrq(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
1765 vinstr(0x22, dst, src1, src2, k66, k0F3A, kW1);
1818 void vpblendw(XMMRegister dst, XMMRegister src1, XMMRegister src2,
1820 vinstr(0x0E, dst, src1, src2, k66, k0F3A, kWIG);
1823 void vpblendw(YMMRegister dst, YMMRegister src1, YMMRegister src2,
1825 vinstr(0x0E, dst, src1, src2, k66, k0F3A, kWIG);
1828 void vpblendw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t mask) {
1829 vinstr(0x0E, dst, src1, src2, k66, k0F3A, kWIG);
1832 void vpblendw(YMMRegister dst, YMMRegister src1, Operand src2, uint8_t mask) {
1833 vinstr(0x0E, dst, src1, src2, k66, k0F3A, kWIG);
1837 void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2,
1839 vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG);
1842 void vpalignr(YMMRegister dst, YMMRegister src1, YMMRegister src2,
1844 vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG);
1847 void vpalignr(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) {
1848 vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG);
1851 void vpalignr(YMMRegister dst, YMMRegister src1, Operand src2, uint8_t imm8) {
1852 vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG);
1856 void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
1857 void vps(byte op, YMMRegister dst, YMMRegister src1, YMMRegister src2);
1858 void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
1859 void vps(byte op, YMMRegister dst, YMMRegister src1, Operand src2);
1860 void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2,
1862 void vps(byte op, YMMRegister dst, YMMRegister src1, YMMRegister src2,
1864 void vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
1865 void vpd(byte op, YMMRegister dst, YMMRegister src1, YMMRegister src2);
1866 void vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
1867 void vpd(byte op, YMMRegister dst, YMMRegister src1, Operand src2);
1880 void andnq(Register dst, Register src1, Register src2) {
1881 bmi1q(0xf2, dst, src1, src2);
1883 void andnq(Register dst, Register src1, Operand src2) {
1884 bmi1q(0xf2, dst, src1, src2);
1886 void andnl(Register dst, Register src1, Register src2) {
1887 bmi1l(0xf2, dst, src1, src2);
1889 void andnl(Register dst, Register src1, Operand src2) {
1890 bmi1l(0xf2, dst, src1, src2);
1892 void bextrq(Register dst, Register src1, Register src2) {
1893 bmi1q(0xf7, dst, src2, src1);
1895 void bextrq(Register dst, Operand src1, Register src2) {
1896 bmi1q(0xf7, dst, src2, src1);
1898 void bextrl(Register dst, Register src1, Register src2) {
1899 bmi1l(0xf7, dst, src2, src1);
1901 void bextrl(Register dst, Operand src1, Register src2) {
1902 bmi1l(0xf7, dst, src2, src1);
1931 void bzhiq(Register dst, Register src1, Register src2) {
1932 bmi2q(kNoPrefix, 0xf5, dst, src2, src1);
1934 void bzhiq(Register dst, Operand src1, Register src2) {
1935 bmi2q(kNoPrefix, 0xf5, dst, src2, src1);
1937 void bzhil(Register dst, Register src1, Register src2) {
1938 bmi2l(kNoPrefix, 0xf5, dst, src2, src1);
1940 void bzhil(Register dst, Operand src1, Register src2) {
1941 bmi2l(kNoPrefix, 0xf5, dst, src2, src1);
1955 void pdepq(Register dst, Register src1, Register src2) {
1956 bmi2q(kF2, 0xf5, dst, src1, src2);
1958 void pdepq(Register dst, Register src1, Operand src2) {
1959 bmi2q(kF2, 0xf5, dst, src1, src2);
1961 void pdepl(Register dst, Register src1, Register src2) {
1962 bmi2l(kF2, 0xf5, dst, src1, src2);
1964 void pdepl(Register dst, Register src1, Operand src2) {
1965 bmi2l(kF2, 0xf5, dst, src1, src2);
1967 void pextq(Register dst, Register src1, Register src2) {
1968 bmi2q(kF3, 0xf5, dst, src1, src2);
1970 void pextq(Register dst, Register src1, Operand src2) {
1971 bmi2q(kF3, 0xf5, dst, src1, src2);
1973 void pextl(Register dst, Register src1, Register src2) {
1974 bmi2l(kF3, 0xf5, dst, src1, src2);
1976 void pextl(Register dst, Register src1, Operand src2) {
1977 bmi2l(kF3, 0xf5, dst, src1, src2);
1979 void sarxq(Register dst, Register src1, Register src2) {
1980 bmi2q(kF3, 0xf7, dst, src2, src1);
1982 void sarxq(Register dst, Operand src1, Register src2) {
1983 bmi2q(kF3, 0xf7, dst, src2, src1);
1985 void sarxl(Register dst, Register src1, Register src2) {
1986 bmi2l(kF3, 0xf7, dst, src2, src1);
1988 void sarxl(Register dst, Operand src1, Register src2) {
1989 bmi2l(kF3, 0xf7, dst, src2, src1);
1991 void shlxq(Register dst, Register src1, Register src2) {
1992 bmi2q(k66, 0xf7, dst, src2, src1);
1994 void shlxq(Register dst, Operand src1, Register src2) {
1995 bmi2q(k66, 0xf7, dst, src2, src1);
1997 void shlxl(Register dst, Register src1, Register src2) {
1998 bmi2l(k66, 0xf7, dst, src2, src1);
2000 void shlxl(Register dst, Operand src1, Register src2) {
2001 bmi2l(k66, 0xf7, dst, src2, src1);
2003 void shrxq(Register dst, Register src1, Register src2) {
2004 bmi2q(kF2, 0xf7, dst, src2, src1);
2006 void shrxq(Register dst, Operand src1, Register src2) {
2007 bmi2q(kF2, 0xf7, dst, src2, src1);
2009 void shrxl(Register dst, Register src1, Register src2) {
2010 bmi2l(kF2, 0xf7, dst, src2, src1);
2012 void shrxl(Register dst, Operand src1, Register src2) {
2013 bmi2l(kF2, 0xf7, dst, src2, src1);
2553 YMMRegister src2, SIMDPrefix pp,
2557 XMMRegister src2, SIMDPrefix pp,
2561 Operand src2, SIMDPrefix pp, LeadingOpcode m,
2565 XMMRegister src2, SIMDPrefix pp,
2569 Operand src2, SIMDPrefix pp, LeadingOpcode m,