Lines Matching defs:prefix
473 // One byte prefix for a short conditional jump.
480 // VEX prefix encodings.
661 // Lock prefix.
958 // SSE instructions with prefix and SSE2 instructions
959 void sse2_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape,
961 void sse2_instr(XMMRegister dst, Operand src, byte prefix, byte escape,
963 #define DECLARE_SSE2_INSTRUCTION(instruction, prefix, escape, opcode) \
965 sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \
968 sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \
978 void sse2_instr(XMMRegister reg, byte imm8, byte prefix, byte escape,
981 sse2_instr(ext_reg, reg, prefix, escape, opcode);
985 #define DECLARE_SSE2_SHIFT_IMM(instruction, prefix, escape, opcode, extension) \
987 sse2_instr(reg, imm8, 0x##prefix, 0x##escape, 0x##opcode, 0x##extension); \
992 #define DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
994 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
997 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
1000 #define DECLARE_SSE2_PD_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1001 DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1003 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX); \
1006 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX); \
1012 #define DECLARE_SSE2_PI_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1013 DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1015 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1018 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1024 #define DECLARE_SSE2_SHIFT_AVX_INSTRUCTION(instruction, prefix, escape, \
1026 DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1028 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1031 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1038 #define DECLARE_SSE2_UNOP_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1056 void ssse3_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
1058 void ssse3_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
1061 #define DECLARE_SSSE3_INSTRUCTION(instruction, prefix, escape1, escape2, \
1064 ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1067 ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1075 void sse4_instr(Register dst, XMMRegister src, byte prefix, byte escape1,
1077 void sse4_instr(Operand dst, XMMRegister src, byte prefix, byte escape1,
1079 void sse4_instr(XMMRegister dst, Register src, byte prefix, byte escape1,
1081 void sse4_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
1083 void sse4_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
1085 #define DECLARE_SSE4_INSTRUCTION(instruction, prefix, escape1, escape2, \
1088 sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1091 sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1101 #define DECLARE_SSE4_EXTRACT_INSTRUCTION(instruction, prefix, escape1, \
1104 sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode, \
1108 sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode, \
1116 void sse4_2_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape1,
1118 void sse4_2_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
1120 #define DECLARE_SSE4_2_INSTRUCTION(instruction, prefix, escape1, escape2, \
1123 sse4_2_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1126 sse4_2_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1132 #define DECLARE_SSE34_AVX_INSTRUCTION(instruction, prefix, escape1, escape2, \
1135 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
1138 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
1141 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0, \
1145 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0, \
1154 #define DECLARE_SSSE3_UNOP_AVX_INSTRUCTION(instruction, prefix, escape1, \
1157 vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
1160 vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
1163 vinstr(0x##opcode, dst, ymm0, src, k##prefix, k##escape1##escape2, kW0); \
1166 vinstr(0x##opcode, dst, ymm0, src, k##prefix, k##escape1##escape2, kW0); \
1211 #define DECLARE_SSE4_PMOV_AVX_INSTRUCTION(instruction, prefix, escape1, \
1214 vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
1217 vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
1222 #define DECLARE_AVX_INSTRUCTION(instruction, prefix, escape1, escape2, opcode) \
1225 vinstr(0x##opcode, src, xmm0, idst, k##prefix, k##escape1##escape2, kW0); \
1229 vinstr(0x##opcode, src, xmm0, dst, k##prefix, k##escape1##escape2, kW0); \
1376 #define FMA(instr, length, prefix, escape1, escape2, extension, opcode) \
1378 fma_instr(0x##opcode, dst, src1, src2, k##length, k##prefix, \
1382 fma_instr(0x##opcode, dst, src1, src2, k##length, k##prefix, \
1460 #define AVX_SCALAR(instr, prefix, escape, opcode) \
1462 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kWIG); \
1465 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kWIG); \
1473 #define AVX_SSE2_SHIFT_IMM(instr, prefix, escape, opcode, extension) \
1476 vinstr(0x##opcode, ext_reg, dst, src, k##prefix, k##escape, kWIG); \
1870 #define AVX2_INSTRUCTION(instr, prefix, escape1, escape2, opcode) \
1873 vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0, \
2100 // Emits a REX prefix that encodes a 64-bit operand size and
2109 // Emits a REX prefix that encodes a 64-bit operand size and
2117 // Emits a REX prefix that encodes a 64-bit operand size and
2123 // Emits a REX prefix that encodes a 64-bit operand size and
2130 // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size.
2220 // Emit vex prefix