Lines Matching defs:opcode
466 // One byte opcode for test eax,0xXXXXXXXX.
468 // One byte opcode for test al, 0xXX.
470 // One byte opcode for nop.
781 // Takes a branch opcode (cc) and a label (L) and generates
944 void sse_instr(XMMRegister dst, XMMRegister src, byte escape, byte opcode);
945 void sse_instr(XMMRegister dst, Operand src, byte escape, byte opcode);
946 #define DECLARE_SSE_INSTRUCTION(instruction, escape, opcode) \
948 sse_instr(dst, src, 0x##escape, 0x##opcode); \
951 sse_instr(dst, src, 0x##escape, 0x##opcode); \
960 byte opcode);
962 byte opcode);
963 #define DECLARE_SSE2_INSTRUCTION(instruction, prefix, escape, opcode) \
965 sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \
968 sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \
979 byte opcode, int extension) {
981 sse2_instr(ext_reg, reg, prefix, escape, opcode);
985 #define DECLARE_SSE2_SHIFT_IMM(instruction, prefix, escape, opcode, extension) \
987 sse2_instr(reg, imm8, 0x##prefix, 0x##escape, 0x##opcode, 0x##extension); \
992 #define DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
994 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
997 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
1000 #define DECLARE_SSE2_PD_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1001 DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1003 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX); \
1006 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX); \
1012 #define DECLARE_SSE2_PI_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1013 DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1015 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1018 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1025 opcode) \
1026 DECLARE_SSE2_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1028 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1031 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0, AVX2); \
1038 #define DECLARE_SSE2_UNOP_AVX_INSTRUCTION(instruction, prefix, escape, opcode) \
1040 vpd(0x##opcode, dst, xmm0, src); \
1043 vpd(0x##opcode, dst, xmm0, src); \
1057 byte escape2, byte opcode);
1059 byte escape2, byte opcode);
1062 opcode) \
1064 ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1067 ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1076 byte escape2, byte opcode, int8_t imm8);
1078 byte escape2, byte opcode, int8_t imm8);
1080 byte escape2, byte opcode, int8_t imm8);
1082 byte escape2, byte opcode);
1084 byte escape2, byte opcode);
1086 opcode) \
1088 sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1091 sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1102 escape2, opcode) \
1104 sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode, \
1108 sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode, \
1117 byte escape2, byte opcode);
1119 byte escape2, byte opcode);
1121 opcode) \
1123 sse4_2_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1126 sse4_2_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
1133 opcode) \
1135 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
1138 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
1141 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0, \
1145 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0, \
1155 escape2, opcode) \
1157 vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
1160 vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
1163 vinstr(0x##opcode, dst, ymm0, src, k##prefix, k##escape1##escape2, kW0); \
1166 vinstr(0x##opcode, dst, ymm0, src, k##prefix, k##escape1##escape2, kW0); \
1212 escape2, opcode) \
1214 vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
1217 vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
1222 #define DECLARE_AVX_INSTRUCTION(instruction, prefix, escape1, escape2, opcode) \
1225 vinstr(0x##opcode, src, xmm0, idst, k##prefix, k##escape1##escape2, kW0); \
1229 vinstr(0x##opcode, src, xmm0, dst, k##prefix, k##escape1##escape2, kW0); \
1376 #define FMA(instr, length, prefix, escape1, escape2, extension, opcode) \
1378 fma_instr(0x##opcode, dst, src1, src2, k##length, k##prefix, \
1382 fma_instr(0x##opcode, dst, src1, src2, k##length, k##prefix, \
1417 #define AVX_SSE_UNOP(instr, escape, opcode) \
1419 vps(0x##opcode, dst, xmm0, src2); \
1422 vps(0x##opcode, dst, xmm0, src2); \
1425 vps(0x##opcode, dst, ymm0, src2); \
1428 vps(0x##opcode, dst, ymm0, src2); \
1433 #define AVX_SSE_BINOP(instr, escape, opcode) \
1435 vps(0x##opcode, dst, src1, src2); \
1438 vps(0x##opcode, dst, src1, src2); \
1441 vps(0x##opcode, dst, src1, src2); \
1444 vps(0x##opcode, dst, src1, src2); \
1449 #define AVX_3(instr, opcode, impl, SIMDRegister) \
1451 impl(opcode, dst, src1, src2); \
1454 impl(opcode, dst, src1, src2); \
1460 #define AVX_SCALAR(instr, prefix, escape, opcode) \
1462 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kWIG); \
1465 vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kWIG); \
1473 #define AVX_SSE2_SHIFT_IMM(instr, prefix, escape, opcode, extension) \
1476 vinstr(0x##opcode, ext_reg, dst, src, k##prefix, k##escape, kWIG); \
1870 #define AVX2_INSTRUCTION(instr, prefix, escape1, escape2, opcode) \
1873 vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0, \
2252 // a three-bit opcode extension into the ModR/M byte.
2280 // similar, differing just in the opcode or in the reg field of the
2282 void arithmetic_op_8(byte opcode, Register reg, Register rm_reg);
2283 void arithmetic_op_8(byte opcode, Register reg, Operand rm_reg);
2284 void arithmetic_op_16(byte opcode, Register reg, Register rm_reg);
2285 void arithmetic_op_16(byte opcode, Register reg, Operand rm_reg);
2287 void arithmetic_op(byte opcode, Register reg, Register rm_reg, int size);
2288 void arithmetic_op(byte opcode, Register reg, Operand rm_reg, int size);