Lines Matching refs:dst
43 void Move(Register dst, uint32_t src);
45 void Move(Register dst, Register src);
46 void Add(Register dst, Immediate src);
47 void And(Register dst, Immediate src);
49 // Will move src1 to dst if AVX is not supported.
50 void Movhps(XMMRegister dst, XMMRegister src1, Operand src2);
51 void Movlps(XMMRegister dst, XMMRegister src1, Operand src2);
53 void Pblendvb(XMMRegister dst, XMMRegister src1, XMMRegister src2,
57 void Pinsrb(XMMRegister dst, XMMRegister src1, Op src2, uint8_t imm8,
59 PinsrHelper(this, &Assembler::vpinsrb, &Assembler::pinsrb, dst, src1, src2,
64 void Pinsrw(XMMRegister dst, XMMRegister src1, Op src2, uint8_t imm8,
66 PinsrHelper(this, &Assembler::vpinsrw, &Assembler::pinsrw, dst, src1, src2,
70 // Supports both SSE and AVX. Move src1 to dst if they are not equal on SSE.
72 void Pshufb(XMMRegister dst, XMMRegister src, Op mask) {
75 vpshufb(dst, src, mask);
78 DCHECK_NE(mask, dst);
79 if (dst != src) {
80 movaps(dst, src);
83 pshufb(dst, mask);
88 void Pshufb(XMMRegister dst, Op mask) {
89 Pshufb(dst, dst, mask);
92 // Shufps that will mov src1 into dst if AVX is not supported.
93 void Shufps(XMMRegister dst, XMMRegister src1, XMMRegister src2,
102 // Call a method where the AVX version expects the dst argument to be
108 void emit(Dst dst, Arg arg, Args... args) {
111 (assm->*avx)(dst, dst, arg, args...);
115 (assm->*no_avx)(dst, arg, args...);
117 (assm->*no_avx)(dst, arg, args...);
122 // check that dst == first src.
127 void emit(Dst dst, Arg arg, Args... args) {
130 (assm->*avx)(dst, arg, args...);
132 DCHECK_EQ(dst, arg);
135 (assm->*no_avx)(dst, args...);
137 DCHECK_EQ(dst, arg);
138 (assm->*no_avx)(dst, args...);
142 // Call a method where the AVX version expects no duplicated dst argument.
147 void emit(Dst dst, Arg arg, Args... args) {
150 (assm->*avx)(dst, arg, args...);
154 (assm->*no_avx)(dst, arg, args...);
156 (assm->*no_avx)(dst, arg, args...);
163 void macro_name(Dst dst, Arg arg, Args... args) { \
165 .template emit<&Assembler::v##name, &Assembler::name>(dst, arg, \
182 void macro_name(Dst dst, Arg arg, Args... args) { \
185 dst, arg, args...); \
190 void macro_name(Dst dst, Arg arg, Args... args) { \
192 .template emit<&Assembler::v##name, &Assembler::name>(dst, arg, \
198 void macro_name(Dst dst, Arg arg, Args... args) { \
200 .template emit<&Assembler::v##name, &Assembler::name>(dst, arg, \
206 void macro_name(Dst dst, Arg arg, Args... args) { \
208 .template emit<&Assembler::v##name, &Assembler::name>(dst, arg, \
214 void macro_name(Dst dst, Arg arg, Args... args) { \
216 .template emit<&Assembler::v##name, &Assembler::name>(dst, arg, \
402 void F64x2ExtractLane(DoubleRegister dst, XMMRegister src, uint8_t lane);
403 void F64x2ReplaceLane(XMMRegister dst, XMMRegister src, DoubleRegister rep,
405 void F64x2Min(XMMRegister dst, XMMRegister lhs, XMMRegister rhs,
407 void F64x2Max(XMMRegister dst, XMMRegister lhs, XMMRegister rhs,
409 void F32x4Splat(XMMRegister dst, DoubleRegister src);
410 void F32x4ExtractLane(FloatRegister dst, XMMRegister src, uint8_t lane);
411 void F32x4Min(XMMRegister dst, XMMRegister lhs, XMMRegister rhs,
413 void F32x4Max(XMMRegister dst, XMMRegister lhs, XMMRegister rhs,
415 void S128Store32Lane(Operand dst, XMMRegister src, uint8_t laneidx);
416 void I8x16Splat(XMMRegister dst, Register src, XMMRegister scratch);
417 void I8x16Splat(XMMRegister dst, Operand src, XMMRegister scratch);
418 void I8x16Shl(XMMRegister dst, XMMRegister src1, uint8_t src2, Register tmp1,
420 void I8x16Shl(XMMRegister dst, XMMRegister src1, Register src2, Register tmp1,
422 void I8x16ShrS(XMMRegister dst, XMMRegister src1, uint8_t src2,
424 void I8x16ShrS(XMMRegister dst, XMMRegister src1, Register src2,
426 void I8x16ShrU(XMMRegister dst, XMMRegister src1, uint8_t src2, Register tmp1,
428 void I8x16ShrU(XMMRegister dst, XMMRegister src1, Register src2,
430 void I16x8Splat(XMMRegister dst, Register src);
431 void I16x8Splat(XMMRegister dst, Operand src);
432 void I16x8ExtMulLow(XMMRegister dst, XMMRegister src1, XMMRegister src2,
434 void I16x8ExtMulHighS(XMMRegister dst, XMMRegister src1, XMMRegister src2,
436 void I16x8ExtMulHighU(XMMRegister dst, XMMRegister src1, XMMRegister src2,
438 void I16x8SConvertI8x16High(XMMRegister dst, XMMRegister src);
439 void I16x8UConvertI8x16High(XMMRegister dst, XMMRegister src,
441 // Will move src1 to dst if AVX is not supported.
442 void I16x8Q15MulRSatS(XMMRegister dst, XMMRegister src1, XMMRegister src2,
444 void I32x4ExtAddPairwiseI16x8U(XMMRegister dst, XMMRegister src,
446 // Requires that dst == src1 if AVX is not supported.
447 void I32x4ExtMul(XMMRegister dst, XMMRegister src1, XMMRegister src2,
449 void I32x4SConvertI16x8High(XMMRegister dst, XMMRegister src);
450 void I32x4UConvertI16x8High(XMMRegister dst, XMMRegister src,
452 void I64x2Neg(XMMRegister dst, XMMRegister src, XMMRegister scratch);
453 void I64x2Abs(XMMRegister dst, XMMRegister src, XMMRegister scratch);
454 void I64x2GtS(XMMRegister dst, XMMRegister src0, XMMRegister src1,
456 void I64x2GeS(XMMRegister dst, XMMRegister src0, XMMRegister src1,
458 void I64x2ShrS(XMMRegister dst, XMMRegister src, uint8_t shift,
460 void I64x2ShrS(XMMRegister dst, XMMRegister src, Register shift,
463 void I64x2Mul(XMMRegister dst, XMMRegister lhs, XMMRegister rhs,
465 void I64x2ExtMul(XMMRegister dst, XMMRegister src1, XMMRegister src2,
467 void I64x2SConvertI32x4High(XMMRegister dst, XMMRegister src);
468 void I64x2UConvertI32x4High(XMMRegister dst, XMMRegister src,
470 void S128Not(XMMRegister dst, XMMRegister src, XMMRegister scratch);
471 // Requires dst == mask when AVX is not supported.
472 void S128Select(XMMRegister dst, XMMRegister mask, XMMRegister src1,
474 void S128Load8Splat(XMMRegister dst, Operand src, XMMRegister scratch);
475 void S128Load16Splat(XMMRegister dst, Operand src, XMMRegister scratch);
476 void S128Load32Splat(XMMRegister dst, Operand src);
477 void S128Store64Lane(Operand dst, XMMRegister src, uint8_t laneidx);
479 void F64x2Qfma(XMMRegister dst, XMMRegister src1, XMMRegister src2,
481 void F64x2Qfms(XMMRegister dst, XMMRegister src1, XMMRegister src2,
483 void F32x4Qfma(XMMRegister dst, XMMRegister src1, XMMRegister src2,
485 void F32x4Qfms(XMMRegister dst, XMMRegister src1, XMMRegister src2,
496 XMMRegister dst, XMMRegister src1, Op src2, uint8_t imm8,
502 (assm->*avx)(dst, src1, src2, imm8);
506 if (dst != src1) assm->movaps(dst, src1);
511 (assm->*noavx)(dst, src2, imm8);
513 (assm->*noavx)(dst, src2, imm8);
519 void I8x16SplatPreAvx2(XMMRegister dst, Op src, XMMRegister scratch);
521 void I16x8SplatPreAvx2(XMMRegister dst, Op src);
542 void Abspd(XMMRegister dst, XMMRegister src, Register tmp) {
543 FloatUnop(dst, src, tmp, &SharedTurboAssembler::Andps,
547 void Absps(XMMRegister dst, XMMRegister src, Register tmp) {
548 FloatUnop(dst, src, tmp, &SharedTurboAssembler::Andps,
552 void Negpd(XMMRegister dst, XMMRegister src, Register tmp) {
553 FloatUnop(dst, src, tmp, &SharedTurboAssembler::Xorps,
557 void Negps(XMMRegister dst, XMMRegister src, Register tmp) {
558 FloatUnop(dst, src, tmp, &SharedTurboAssembler::Xorps,
563 void Pextrd(Register dst, XMMRegister src, uint8_t imm8) {
565 Movd(dst, src);
571 vpextrd(dst, src, imm8);
574 pextrd(dst, src, imm8);
577 impl()->PextrdPreSse41(dst, src, imm8);
582 void Pinsrd(XMMRegister dst, XMMRegister src1, Op src2, uint8_t imm8,
585 PinsrHelper(this, &Assembler::vpinsrd, &Assembler::pinsrd, dst, src1,
589 if (dst != src1) {
590 movaps(dst, src1);
592 impl()->PinsrdPreSse41(dst, src2, imm8, load_pc_offset);
597 void Pinsrd(XMMRegister dst, Op src, uint8_t imm8,
599 Pinsrd(dst, dst, src, imm8, load_pc_offset);
602 void F64x2ConvertLowI32x4U(XMMRegister dst, XMMRegister src,
605 // dst = [ src_low, 0x43300000, src_high, 0x4330000 ];
608 if (!CpuFeatures::IsSupported(AVX) && dst != src) {
609 movaps(dst, src);
610 src = dst;
612 Unpcklps(dst, src,
617 Subpd(dst,
622 void I32x4SConvertF32x4(XMMRegister dst, XMMRegister src, XMMRegister tmp,
639 vandps(dst, src, tmp);
641 vcvttps2dq(dst, dst);
642 vpxor(dst, dst, tmp);
644 if (src == dst) {
647 andps(dst, tmp);
649 cmpleps(tmp, dst);
650 cvttps2dq(dst, dst);
651 xorps(dst, tmp);
655 cvttps2dq(dst, src);
656 xorps(dst, tmp);
659 andps(dst, tmp);
664 void I32x4TruncSatF64x2SZero(XMMRegister dst, XMMRegister src,
669 XMMRegister original_dst = dst;
671 if (dst == src) {
673 dst = scratch;
675 // dst = 0 if src == NaN, else all ones.
676 vcmpeqpd(dst, src, src);
677 // dst = 0 if src == NaN, else INT32_MAX as double.
679 dst, dst,
682 // dst = 0 if src == NaN, src is saturated to INT32_MAX as double.
683 vminpd(dst, src, dst);
686 vcvttpd2dq(original_dst, dst);
688 if (dst != src) {
689 movaps(dst, src);
691 movaps(scratch, dst);
692 cmpeqpd(scratch, dst);
696 minpd(dst, scratch);
697 cvttpd2dq(dst, dst);
701 void I32x4TruncSatF64x2UZero(XMMRegister dst, XMMRegister src,
708 vmaxpd(dst, src, scratch);
711 dst, dst,
715 vroundpd(dst, dst, kRoundToZero);
717 vaddpd(dst, dst,
721 // dst = [dst[0], dst[2], 0, 0]
722 vshufps(dst, dst, scratch, 0x88);
725 if (dst != src) {
726 movaps(dst, src);
729 maxpd(dst, scratch);
730 minpd(dst, ExternalReferenceAsOperand(
733 roundpd(dst, dst, kRoundToZero);
734 addpd(dst,
737 shufps(dst, scratch, 0x88);
741 void I32x4TruncF64x2UZero(XMMRegister dst, XMMRegister src, Register tmp,
745 if (dst != src && !CpuFeatures::IsSupported(AVX)) {
746 movaps(dst, src);
747 src = dst;
750 Roundpd(dst, src, kRoundToZero);
752 Addpd(dst, dst,
756 // dst = [dst[0], dst[2], 0, 0]
757 Shufps(dst, dst, scratch, 0x88);
760 void I32x4TruncF32x4U(XMMRegister dst, XMMRegister src, Register scratch,
775 if (dst != src) {
776 Movaps(dst, src);
778 // In dst, lanes < INT32_MAX are zeroed, other lanes left alone.
779 Pxor(dst, tmp);
796 Addps(dst, dst, dst);
798 Pslld(dst, byte{8});
800 Paddd(dst, tmp);
803 void I32x4ExtAddPairwiseI16x8S(XMMRegister dst, XMMRegister src,
811 // dst = | a*1 + b*1 | c*1 + d*1 | e*1 + f*1 | g*1 + h*1 |
812 if (!CpuFeatures::IsSupported(AVX) && (dst != src)) {
813 movaps(dst, src);
814 src = dst;
817 Pmaddwd(dst, src, op);
820 void I16x8ExtAddPairwiseI8x16S(XMMRegister dst, XMMRegister src,
830 vpmaddubsw(dst, scratch, src);
833 if (dst == src) {
836 movaps(dst, scratch);
838 movaps(dst, op);
839 pmaddubsw(dst, src);
844 void I16x8ExtAddPairwiseI8x16U(XMMRegister dst, XMMRegister src,
851 vpmaddubsw(dst, src, op);
854 if (dst != src) {
855 movaps(dst, src);
857 pmaddubsw(dst, op);
861 void I8x16Swizzle(XMMRegister dst, XMMRegister src, XMMRegister mask,
867 Pshufb(dst, src, mask);
878 vpshufb(dst, src, scratch);
882 if (dst != src) {
883 DCHECK_NE(dst, mask);
884 movaps(dst, src);
887 pshufb(dst, scratch);
891 void I8x16Popcnt(XMMRegister dst, XMMRegister src, XMMRegister tmp1,
894 DCHECK_NE(dst, tmp1);
896 DCHECK_NE(dst, tmp2);
904 vpand(dst, tmp1, src);
909 vpshufb(dst, tmp1, dst);
911 vpaddb(dst, dst, tmp2);
919 if (dst != src) {
920 movaps(dst, src);
925 psubb(dst, tmp1);
928 movaps(tmp1, dst);
929 andps(dst, splat_0x33);
932 paddb(dst, tmp1);
933 movaps(tmp1, dst);
934 psrlw(dst, 4);
935 paddb(dst, tmp1);
936 andps(dst, ExternalReferenceAsOperand(
952 movaps(dst, mask);
953 pshufb(dst, tmp1);
956 paddb(dst, tmp1);
971 void FloatUnop(XMMRegister dst, XMMRegister src, Register tmp,
973 if (!CpuFeatures::IsSupported(AVX) && (dst != src)) {
974 movaps(dst, src);
975 src = dst;
978 (assm->*op)(dst, src, ExternalReferenceAsOperand(ext, tmp));