Lines Matching refs:dst
250 void TurboAssembler::CeilF32(DoubleRegister dst, DoubleRegister src) {
251 fiebra(ROUND_TOWARD_POS_INF, dst, src);
254 void TurboAssembler::CeilF64(DoubleRegister dst, DoubleRegister src) {
255 fidbra(ROUND_TOWARD_POS_INF, dst, src);
258 void TurboAssembler::FloorF32(DoubleRegister dst, DoubleRegister src) {
259 fiebra(ROUND_TOWARD_NEG_INF, dst, src);
262 void TurboAssembler::FloorF64(DoubleRegister dst, DoubleRegister src) {
263 fidbra(ROUND_TOWARD_NEG_INF, dst, src);
266 void TurboAssembler::TruncF32(DoubleRegister dst, DoubleRegister src) {
267 fiebra(ROUND_TOWARD_0, dst, src);
270 void TurboAssembler::TruncF64(DoubleRegister dst, DoubleRegister src) {
271 fidbra(ROUND_TOWARD_0, dst, src);
274 void TurboAssembler::NearestIntF32(DoubleRegister dst, DoubleRegister src) {
275 fiebra(ROUND_TO_NEAREST_TO_EVEN, dst, src);
278 void TurboAssembler::NearestIntF64(DoubleRegister dst, DoubleRegister src) {
279 fidbra(ROUND_TO_NEAREST_TO_EVEN, dst, src);
510 void TurboAssembler::Move(Register dst, Handle<HeapObject> value,
516 IndirectLoadConstant(dst, value);
521 mov(dst, Operand(static_cast<int>(index), rmode));
524 mov(dst, Operand(value.address(), rmode));
528 void TurboAssembler::Move(Register dst, ExternalReference reference) {
533 IndirectLoadExternalReference(dst, reference);
536 mov(dst, Operand(reference));
539 void TurboAssembler::Move(Register dst, Register src, Condition cond) {
540 if (dst != src) {
542 mov(dst, src);
544 LoadOnConditionP(cond, dst, src);
549 void TurboAssembler::Move(DoubleRegister dst, DoubleRegister src) {
550 if (dst != src) {
551 ldr(dst, src);
555 void TurboAssembler::Move(Register dst, const MemOperand& src) {
556 LoadU64(dst, src);
580 void TurboAssembler::RotateInsertSelectBits(Register dst, Register src,
587 risbg(dst, src, startBit,
590 risbg(dst, src, startBit, endBit, shiftAmt);
593 void TurboAssembler::BranchRelativeOnIdxHighP(Register dst, Register inc,
596 brxhg(dst, inc, L);
598 brxh(dst, inc, L);
806 void TurboAssembler::SmiUntag(Register dst, const MemOperand& src) {
808 LoadS32(dst, src);
810 LoadU64(dst, src);
812 SmiUntag(dst);
815 void TurboAssembler::SmiUntagField(Register dst, const MemOperand& src) {
816 SmiUntag(dst, src);
1119 void TurboAssembler::CanonicalizeNaN(const DoubleRegister dst,
1122 if (dst != src) ldr(dst, src);
1124 sdbr(dst, kDoubleRegZero);
1127 void TurboAssembler::ConvertIntToDouble(DoubleRegister dst, Register src) {
1128 cdfbr(dst, src);
1131 void TurboAssembler::ConvertUnsignedIntToDouble(DoubleRegister dst,
1134 cdlfbr(Condition(5), Condition(0), dst, src);
1139 cdgbr(dst, src);
1143 void TurboAssembler::ConvertIntToFloat(DoubleRegister dst, Register src) {
1144 cefbra(Condition(4), dst, src);
1147 void TurboAssembler::ConvertUnsignedIntToFloat(DoubleRegister dst,
1149 celfbr(Condition(4), Condition(0), dst, src);
1172 void TurboAssembler::ConvertFloat32ToInt64(const Register dst,
1191 cgebr(m, dst, double_input);
1194 void TurboAssembler::ConvertDoubleToInt64(const Register dst,
1213 cgdbr(m, dst, double_input);
1216 void TurboAssembler::ConvertDoubleToInt32(const Register dst,
1237 lghi(dst, Operand::Zero());
1239 cfdbr(m, dst, double_input);
1316 const Register dst, const DoubleRegister double_input,
1334 clgdbr(m, Condition(0), dst, double_input);
1338 const Register dst, const DoubleRegister double_input,
1357 lghi(dst, Operand::Zero());
1359 clfdbr(m, Condition(0), dst, double_input);
1362 void TurboAssembler::MovDoubleToInt64(Register dst, DoubleRegister src) {
1363 lgdr(dst, src);
1366 void TurboAssembler::MovInt64ToDouble(DoubleRegister dst, Register src) {
1367 ldgr(dst, src);
1601 void TurboAssembler::MovFromFloatResult(const DoubleRegister dst) {
1602 Move(dst, d0);
1605 void TurboAssembler::MovFromFloatParameter(const DoubleRegister dst) {
1606 Move(dst, d0);
2111 void MacroAssembler::LoadNativeContextSlot(Register dst, int index) {
2112 LoadMap(dst, cp);
2114 dst, FieldMemOperand(
2115 dst, Map::kConstructorOrBackPointerOrNativeContextOffset));
2116 LoadTaggedPointerField(dst, MemOperand(dst, Context::SlotOffset(index)));
2436 void TurboAssembler::mov(Register dst, Register src) { lgr(dst, src); }
2438 void TurboAssembler::mov(Register dst, const Operand& src) {
2458 llill(dst, Operand(lo_32));
2461 llilf(dst, Operand(lo_32));
2465 llihl(dst, Operand(hi_32));
2468 llihf(dst, Operand(hi_32));
2471 lghi(dst, Operand(value));
2474 lgfi(dst, Operand(value));
2479 iihf(dst, Operand(hi_32));
2480 iilf(dst, Operand(lo_32));
2483 void TurboAssembler::MulS32(Register dst, const MemOperand& src1) {
2485 ms(dst, src1);
2487 msy(dst, src1);
2493 void TurboAssembler::MulS32(Register dst, Register src1) { msr(dst, src1); }
2495 void TurboAssembler::MulS32(Register dst, const Operand& src1) {
2496 msfi(dst, src1);
2501 lgfr(dst, src1); \
2502 instr(dst, src2); \
2503 srlg(dst, dst, Operand(32)); \
2506 void TurboAssembler::MulHighS32(Register dst, Register src1,
2511 void TurboAssembler::MulHighS32(Register dst, Register src1, Register src2) {
2512 if (dst == src2) {
2518 void TurboAssembler::MulHighS32(Register dst, Register src1,
2529 LoadU32(dst, r0); \
2532 void TurboAssembler::MulHighU32(Register dst, Register src1,
2537 void TurboAssembler::MulHighU32(Register dst, Register src1, Register src2) {
2541 void TurboAssembler::MulHighU32(Register dst, Register src1,
2543 USE(dst);
2553 lgfr(dst, src1); \
2554 instr(dst, src2); \
2555 cgfr(dst, dst); \
2558 void TurboAssembler::Mul32WithOverflowIfCCUnequal(Register dst, Register src1,
2560 Register result = dst;
2561 if (src2.rx() == dst || src2.rb() == dst) dst = r0;
2563 if (result != dst) llgfr(result, dst);
2566 void TurboAssembler::Mul32WithOverflowIfCCUnequal(Register dst, Register src1,
2568 if (dst == src2) {
2574 void TurboAssembler::Mul32WithOverflowIfCCUnequal(Register dst, Register src1,
2585 LoadU32(dst, r1); \
2588 void TurboAssembler::DivS32(Register dst, Register src1,
2593 void TurboAssembler::DivS32(Register dst, Register src1, Register src2) {
2604 LoadU32(dst, r1); \
2607 void TurboAssembler::DivU32(Register dst, Register src1,
2612 void TurboAssembler::DivU32(Register dst, Register src1, Register src2) {
2622 lgr(dst, r1); \
2625 void TurboAssembler::DivS64(Register dst, Register src1,
2630 void TurboAssembler::DivS64(Register dst, Register src1, Register src2) {
2641 lgr(dst, r1); \
2644 void TurboAssembler::DivU64(Register dst, Register src1,
2649 void TurboAssembler::DivU64(Register dst, Register src1, Register src2) {
2659 LoadU32(dst, r0); \
2662 void TurboAssembler::ModS32(Register dst, Register src1,
2667 void TurboAssembler::ModS32(Register dst, Register src1, Register src2) {
2678 LoadU32(dst, r0); \
2681 void TurboAssembler::ModU32(Register dst, Register src1,
2686 void TurboAssembler::ModU32(Register dst, Register src1, Register src2) {
2696 lgr(dst, r0); \
2699 void TurboAssembler::ModS64(Register dst, Register src1,
2704 void TurboAssembler::ModS64(Register dst, Register src1, Register src2) {
2715 lgr(dst, r0); \
2718 void TurboAssembler::ModU64(Register dst, Register src1,
2723 void TurboAssembler::ModU64(Register dst, Register src1, Register src2) {
2729 void TurboAssembler::MulS64(Register dst, const Operand& opnd) {
2730 msgfi(dst, opnd);
2733 void TurboAssembler::MulS64(Register dst, Register src) { msgr(dst, src); }
2735 void TurboAssembler::MulS64(Register dst, const MemOperand& opnd) {
2736 msg(dst, opnd);
2754 // Add 32-bit (Register dst = Register dst + Immediate opnd)
2755 void TurboAssembler::AddS32(Register dst, const Operand& opnd) {
2757 ahi(dst, opnd);
2759 afi(dst, opnd);
2762 // Add Pointer Size (Register dst = Register dst + Immediate opnd)
2763 void TurboAssembler::AddS64(Register dst, const Operand& opnd) {
2765 aghi(dst, opnd);
2767 agfi(dst, opnd);
2770 void TurboAssembler::AddS32(Register dst, Register src, int32_t opnd) {
2771 AddS32(dst, src, Operand(opnd));
2774 // Add 32-bit (Register dst = Register src + Immediate opnd)
2775 void TurboAssembler::AddS32(Register dst, Register src, const Operand& opnd) {
2776 if (dst != src) {
2778 ahik(dst, src, opnd);
2781 lr(dst, src);
2783 AddS32(dst, opnd);
2786 void TurboAssembler::AddS64(Register dst, Register src, int32_t opnd) {
2787 AddS64(dst, src, Operand(opnd));
2790 // Add Pointer Size (Register dst = Register src + Immediate opnd)
2791 void TurboAssembler::AddS64(Register dst, Register src, const Operand& opnd) {
2792 if (dst != src) {
2794 aghik(dst, src, opnd);
2797 mov(dst, src);
2799 AddS64(dst, opnd);
2802 // Add 32-bit (Register dst = Register dst + Register src)
2803 void TurboAssembler::AddS32(Register dst, Register src) { ar(dst, src); }
2805 // Add Pointer Size (Register dst = Register dst + Register src)
2806 void TurboAssembler::AddS64(Register dst, Register src) { agr(dst, src); }
2808 // Add 32-bit (Register dst = Register src1 + Register src2)
2809 void TurboAssembler::AddS32(Register dst, Register src1, Register src2) {
2810 if (dst != src1 && dst != src2) {
2814 ark(dst, src1, src2);
2817 lr(dst, src1);
2819 } else if (dst == src2) {
2822 ar(dst, src2);
2825 // Add Pointer Size (Register dst = Register src1 + Register src2)
2826 void TurboAssembler::AddS64(Register dst, Register src1, Register src2) {
2827 if (dst != src1 && dst != src2) {
2831 agrk(dst, src1, src2);
2834 mov(dst, src1);
2836 } else if (dst == src2) {
2839 agr(dst, src2);
2843 void TurboAssembler::AddS32(Register dst, const MemOperand& opnd) {
2846 a(dst, opnd);
2848 ay(dst, opnd);
2852 void TurboAssembler::AddS64(Register dst, const MemOperand& opnd) {
2854 ag(dst, opnd);
2877 // Add Logical 32-bit (Register dst = Register src1 + Register src2)
2878 void TurboAssembler::AddU32(Register dst, Register src1, Register src2) {
2879 if (dst != src2 && dst != src1) {
2880 lr(dst, src1);
2881 alr(dst, src2);
2882 } else if (dst != src2) {
2883 // dst == src1
2884 DCHECK(dst == src1);
2885 alr(dst, src2);
2887 // dst == src2
2888 DCHECK(dst == src2);
2889 alr(dst, src1);
2893 // Add Logical 32-bit (Register dst = Register dst + Immediate opnd)
2894 void TurboAssembler::AddU32(Register dst, const Operand& imm) {
2895 alfi(dst, imm);
2898 // Add Logical Pointer Size (Register dst = Register dst + Immediate opnd)
2899 void TurboAssembler::AddU64(Register dst, const Operand& imm) {
2900 algfi(dst, imm);
2903 void TurboAssembler::AddU64(Register dst, Register src1, Register src2) {
2904 if (dst != src2 && dst != src1) {
2906 algrk(dst, src1, src2);
2908 lgr(dst, src1);
2909 algr(dst, src2);
2911 } else if (dst != src2) {
2912 // dst == src1
2913 DCHECK(dst == src1);
2914 algr(dst, src2);
2916 // dst == src2
2917 DCHECK(dst == src2);
2918 algr(dst, src1);
2923 void TurboAssembler::AddU32(Register dst, const MemOperand& opnd) {
2926 al_z(dst, opnd);
2928 aly(dst, opnd);
2932 void TurboAssembler::AddU64(Register dst, const MemOperand& opnd) {
2934 alg(dst, opnd);
2941 // Subtract Logical 32-bit (Register dst = Register src1 - Register src2)
2942 void TurboAssembler::SubU32(Register dst, Register src1, Register src2) {
2943 if (dst != src2 && dst != src1) {
2944 lr(dst, src1);
2945 slr(dst, src2);
2946 } else if (dst != src2) {
2947 // dst == src1
2948 DCHECK(dst == src1);
2949 slr(dst, src2);
2951 // dst == src2
2952 DCHECK(dst == src2);
2953 lr(r0, dst);
2954 SubU32(dst, src1, r0);
2958 // Subtract 32-bit (Register dst = Register dst - Immediate opnd)
2959 void TurboAssembler::SubS32(Register dst, const Operand& imm) {
2960 AddS32(dst, Operand(-(imm.immediate())));
2963 // Subtract Pointer Size (Register dst = Register dst - Immediate opnd)
2964 void TurboAssembler::SubS64(Register dst, const Operand& imm) {
2965 AddS64(dst, Operand(-(imm.immediate())));
2968 void TurboAssembler::SubS32(Register dst, Register src, int32_t imm) {
2969 SubS32(dst, src, Operand(imm));
2972 // Subtract 32-bit (Register dst = Register src - Immediate opnd)
2973 void TurboAssembler::SubS32(Register dst, Register src, const Operand& imm) {
2974 AddS32(dst, src, Operand(-(imm.immediate())));
2977 void TurboAssembler::SubS64(Register dst, Register src, int32_t imm) {
2978 SubS64(dst, src, Operand(imm));
2981 // Subtract Pointer Sized (Register dst = Register src - Immediate opnd)
2982 void TurboAssembler::SubS64(Register dst, Register src, const Operand& imm) {
2983 AddS64(dst, src, Operand(-(imm.immediate())));
2986 // Subtract 32-bit (Register dst = Register dst - Register src)
2987 void TurboAssembler::SubS32(Register dst, Register src) { sr(dst, src); }
2989 // Subtract Pointer Size (Register dst = Register dst - Register src)
2990 void TurboAssembler::SubS64(Register dst, Register src) { sgr(dst, src); }
2993 void TurboAssembler::SubS32(Register dst, Register src1, Register src2) {
2996 srk(dst, src1, src2);
2999 if (dst != src1 && dst != src2) lr(dst, src1);
3000 // In scenario where we have dst = src - dst, we need to swap and negate
3001 if (dst != src1 && dst == src2) {
3003 lcr(dst, dst); // dst = -dst
3005 ar(dst, src1); // dst = dst + src
3008 sr(dst, src2);
3013 void TurboAssembler::SubS64(Register dst, Register src1, Register src2) {
3016 sgrk(dst, src1, src2);
3019 if (dst != src1 && dst != src2) mov(dst, src1);
3020 // In scenario where we have dst = src - dst, we need to swap and negate
3021 if (dst != src1 && dst == src2) {
3023 lcgr(dst, dst); // dst = -dst
3025 AddS64(dst, src1); // dst = dst + src
3028 SubS64(dst, src2);
3033 void TurboAssembler::SubS32(Register dst, const MemOperand& opnd) {
3036 s(dst, opnd);
3038 sy(dst, opnd);
3042 void TurboAssembler::SubS64(Register dst, const MemOperand& opnd) {
3044 sg(dst, opnd);
3046 SubS32(dst, opnd);
3050 void TurboAssembler::MovIntToFloat(DoubleRegister dst, Register src) {
3052 ldgr(dst, r0);
3055 void TurboAssembler::MovFloatToInt(Register dst, DoubleRegister src) {
3056 lgdr(dst, src);
3057 srlg(dst, dst, Operand(32));
3061 void TurboAssembler::LoadAndSub32(Register dst, Register src,
3063 lcr(dst, src);
3064 laa(dst, dst, opnd);
3067 void TurboAssembler::LoadAndSub64(Register dst, Register src,
3069 lcgr(dst, src);
3070 laag(dst, dst, opnd);
3078 void TurboAssembler::SubU32(Register dst, const MemOperand& opnd) {
3081 sl(dst, opnd);
3083 sly(dst, opnd);
3087 void TurboAssembler::SubU64(Register dst, const MemOperand& opnd) {
3090 slgf(dst, opnd);
3092 SubU32(dst, opnd);
3100 // AND 32-bit - dst = dst & src
3101 void TurboAssembler::And(Register dst, Register src) { nr(dst, src); }
3103 // AND Pointer Size - dst = dst & src
3104 void TurboAssembler::AndP(Register dst, Register src) { ngr(dst, src); }
3106 // Non-clobbering AND 32-bit - dst = src1 & src1
3107 void TurboAssembler::And(Register dst, Register src1, Register src2) {
3108 if (dst != src1 && dst != src2) {
3112 nrk(dst, src1, src2);
3115 lr(dst, src1);
3117 } else if (dst == src2) {
3120 And(dst, src2);
3123 // Non-clobbering AND pointer size - dst = src1 & src1
3124 void TurboAssembler::AndP(Register dst, Register src1, Register src2) {
3125 if (dst != src1 && dst != src2) {
3129 ngrk(dst, src1, src2);
3132 mov(dst, src1);
3134 } else if (dst == src2) {
3137 AndP(dst, src2);
3141 void TurboAssembler::And(Register dst, const MemOperand& opnd) {
3144 n(dst, opnd);
3146 ny(dst, opnd);
3150 void TurboAssembler::AndP(Register dst, const MemOperand& opnd) {
3153 ng(dst, opnd);
3155 And(dst, opnd);
3159 // AND 32-bit - dst = dst & imm
3160 void TurboAssembler::And(Register dst, const Operand& opnd) { nilf(dst, opnd); }
3162 // AND Pointer Size - dst = dst & imm
3163 void TurboAssembler::AndP(Register dst, const Operand& opnd) {
3168 nihf(dst, Operand(value >> 32));
3170 nilf(dst, Operand(value & 0xFFFFFFFF));
3172 And(dst, opnd);
3176 // AND 32-bit - dst = src & imm
3177 void TurboAssembler::And(Register dst, Register src, const Operand& opnd) {
3178 if (dst != src) lr(dst, src);
3179 nilf(dst, opnd);
3182 // AND Pointer Size - dst = src & imm
3183 void TurboAssembler::AndP(Register dst, Register src, const Operand& opnd) {
3205 RotateInsertSelectBits(dst, src, Operand(startBit), Operand(endBit),
3212 RotateInsertSelectBits(dst, src, Operand::Zero(), Operand(endBit),
3218 // If we are &'ing zero, we can just whack the dst register and skip copy
3219 if (dst != src && (0 != value)) mov(dst, src);
3220 AndP(dst, opnd);
3223 // OR 32-bit - dst = dst & src
3224 void TurboAssembler::Or(Register dst, Register src) { or_z(dst, src); }
3226 // OR Pointer Size - dst = dst & src
3227 void TurboAssembler::OrP(Register dst, Register src) { ogr(dst, src); }
3229 // Non-clobbering OR 32-bit - dst = src1 & src1
3230 void TurboAssembler::Or(Register dst, Register src1, Register src2) {
3231 if (dst != src1 && dst != src2) {
3235 ork(dst, src1, src2);
3238 lr(dst, src1);
3240 } else if (dst == src2) {
3243 Or(dst, src2);
3246 // Non-clobbering OR pointer size - dst = src1 & src1
3247 void TurboAssembler::OrP(Register dst, Register src1, Register src2) {
3248 if (dst != src1 && dst != src2) {
3252 ogrk(dst, src1, src2);
3255 mov(dst, src1);
3257 } else if (dst == src2) {
3260 OrP(dst, src2);
3264 void TurboAssembler::Or(Register dst, const MemOperand& opnd) {
3267 o(dst, opnd);
3269 oy(dst, opnd);
3273 void TurboAssembler::OrP(Register dst, const MemOperand& opnd) {
3276 og(dst, opnd);
3278 Or(dst, opnd);
3282 // OR 32-bit - dst = dst & imm
3283 void TurboAssembler::Or(Register dst, const Operand& opnd) { oilf(dst, opnd); }
3285 // OR Pointer Size - dst = dst & imm
3286 void TurboAssembler::OrP(Register dst, const Operand& opnd) {
3291 oihf(dst, Operand(value >> 32));
3293 oilf(dst, Operand(value & 0xFFFFFFFF));
3295 Or(dst, opnd);
3299 // OR 32-bit - dst = src & imm
3300 void TurboAssembler::Or(Register dst, Register src, const Operand& opnd) {
3301 if (dst != src) lr(dst, src);
3302 oilf(dst, opnd);
3305 // OR Pointer Size - dst = src & imm
3306 void TurboAssembler::OrP(Register dst, Register src, const Operand& opnd) {
3307 if (dst != src) mov(dst, src);
3308 OrP(dst, opnd);
3311 // XOR 32-bit - dst = dst & src
3312 void TurboAssembler::Xor(Register dst, Register src) { xr(dst, src); }
3314 // XOR Pointer Size - dst = dst & src
3315 void TurboAssembler::XorP(Register dst, Register src) { xgr(dst, src); }
3317 // Non-clobbering XOR 32-bit - dst = src1 & src1
3318 void TurboAssembler::Xor(Register dst, Register src1, Register src2) {
3319 if (dst != src1 && dst != src2) {
3323 xrk(dst, src1, src2);
3326 lr(dst, src1);
3328 } else if (dst == src2) {
3331 Xor(dst, src2);
3334 // Non-clobbering XOR pointer size - dst = src1 & src1
3335 void TurboAssembler::XorP(Register dst, Register src1, Register src2) {
3336 if (dst != src1 && dst != src2) {
3340 xgrk(dst, src1, src2);
3343 mov(dst, src1);
3345 } else if (dst == src2) {
3348 XorP(dst, src2);
3352 void TurboAssembler::Xor(Register dst, const MemOperand& opnd) {
3355 x(dst, opnd);
3357 xy(dst, opnd);
3361 void TurboAssembler::XorP(Register dst, const MemOperand& opnd) {
3364 xg(dst, opnd);
3366 Xor(dst, opnd);
3370 // XOR 32-bit - dst = dst & imm
3371 void TurboAssembler::Xor(Register dst, const Operand& opnd) { xilf(dst, opnd); }
3373 // XOR Pointer Size - dst = dst & imm
3374 void TurboAssembler::XorP(Register dst, const Operand& opnd) {
3377 xihf(dst, Operand(value >> 32));
3378 xilf(dst, Operand(value & 0xFFFFFFFF));
3380 Xor(dst, opnd);
3384 // XOR 32-bit - dst = src & imm
3385 void TurboAssembler::Xor(Register dst, Register src, const Operand& opnd) {
3386 if (dst != src) lr(dst, src);
3387 xilf(dst, opnd);
3390 // XOR Pointer Size - dst = src & imm
3391 void TurboAssembler::XorP(Register dst, Register src, const Operand& opnd) {
3392 if (dst != src) mov(dst, src);
3393 XorP(dst, opnd);
3396 void TurboAssembler::Not32(Register dst, Register src) {
3397 if (src != no_reg && src != dst) lr(dst, src);
3398 xilf(dst, Operand(0xFFFFFFFF));
3401 void TurboAssembler::Not64(Register dst, Register src) {
3402 if (src != no_reg && src != dst) lgr(dst, src);
3403 xihf(dst, Operand(0xFFFFFFFF));
3404 xilf(dst, Operand(0xFFFFFFFF));
3407 void TurboAssembler::NotP(Register dst, Register src) {
3409 Not64(dst, src);
3411 Not32(dst, src);
3440 void TurboAssembler::CmpS32(Register dst, const Operand& opnd) {
3444 chi(dst, opnd);
3446 cfi(dst, opnd);
3450 cfi(dst, opnd);
3456 void TurboAssembler::CmpS64(Register dst, const Operand& opnd) {
3458 cgfi(dst, opnd);
3461 cgr(dst, r0);
3466 void TurboAssembler::CmpS32(Register dst, const MemOperand& opnd) {
3470 c(dst, opnd);
3472 cy(dst, opnd);
3476 void TurboAssembler::CmpS64(Register dst, const MemOperand& opnd) {
3479 cg(dst, opnd);
3503 void TurboAssembler::CmpU32(Register dst, Register src) { clr(dst, src); }
3506 void TurboAssembler::CmpU64(Register dst, Register src) {
3508 clgr(dst, src);
3510 CmpU32(dst, src);
3515 void TurboAssembler::CmpU32(Register dst, const Operand& opnd) {
3516 clfi(dst, opnd);
3520 void TurboAssembler::CmpU64(Register dst, const Operand& opnd) {
3523 clgfi(dst, opnd);
3525 CmpU32(dst, opnd);
3530 void TurboAssembler::CmpU32(Register dst, const MemOperand& opnd) {
3534 cl(dst, opnd);
3536 cly(dst, opnd);
3540 void TurboAssembler::CmpU64(Register dst, const MemOperand& opnd) {
3544 clg(dst, opnd);
3546 CmpU32(dst, opnd);
3573 void TurboAssembler::LoadSmiLiteral(Register dst, Smi smi) {
3576 llilf(dst, Operand(value));
3580 llihf(dst, Operand(value >> 32));
3598 void TurboAssembler::LoadU64(Register dst, const MemOperand& mem,
3609 lg(dst, src);
3692 void TurboAssembler::LoadS32(Register dst, Register src) {
3694 lgfr(dst, src);
3696 if (dst != src) lr(dst, src);
3701 void TurboAssembler::LoadS32(Register dst, const MemOperand& mem,
3709 lgf(dst, MemOperand(mem.rb(), scratch));
3711 l(dst, MemOperand(mem.rb(), scratch));
3715 lgf(dst, mem);
3718 l(dst, mem);
3720 ly(dst, mem);
3727 void TurboAssembler::LoadU32(Register dst, Register src) {
3729 llgfr(dst, src);
3731 if (dst != src) lr(dst, src);
3737 void TurboAssembler::LoadU32(Register dst, const MemOperand& mem,
3744 llgf(dst, mem);
3748 llgf(dst, MemOperand(base, scratch));
3769 l(dst, mem);
3771 ly(dst, mem);
3773 ly(dst, MemOperand(base, scratch));
3778 void TurboAssembler::LoadU16(Register dst, const MemOperand& mem) {
3781 llgh(dst, mem);
3783 llh(dst, mem);
3787 void TurboAssembler::LoadU16(Register dst, Register src) {
3789 llghr(dst, src);
3791 llhr(dst, src);
3795 void TurboAssembler::LoadS8(Register dst, const MemOperand& mem) {
3798 lgb(dst, mem);
3800 lb(dst, mem);
3804 void TurboAssembler::LoadS8(Register dst, Register src) {
3806 lgbr(dst, src);
3808 lbr(dst, src);
3812 void TurboAssembler::LoadU8(Register dst, const MemOperand& mem) {
3815 llgc(dst, mem);
3817 llc(dst, mem);
3821 void TurboAssembler::LoadU8(Register dst, Register src) {
3823 llgcr(dst, src);
3825 llcr(dst, src);
3830 void TurboAssembler::LoadU64LE(Register dst, const MemOperand& mem,
3832 lrvg(dst, mem);
3835 void TurboAssembler::LoadS32LE(Register dst, const MemOperand& opnd,
3837 lrv(dst, opnd);
3838 LoadS32(dst, dst);
3841 void TurboAssembler::LoadU32LE(Register dst, const MemOperand& opnd,
3843 lrv(dst, opnd);
3844 LoadU32(dst, dst);
3847 void TurboAssembler::LoadU16LE(Register dst, const MemOperand& opnd) {
3848 lrvh(dst, opnd);
3849 LoadU16(dst, dst);
3852 void TurboAssembler::LoadS16LE(Register dst, const MemOperand& opnd) {
3853 lrvh(dst, opnd);
3854 LoadS16(dst, dst);
3857 void TurboAssembler::LoadV128LE(DoubleRegister dst, const MemOperand& opnd,
3862 vlbr(dst, opnd, Condition(4));
3867 vlvgp(dst, scratch1, scratch0);
3871 void TurboAssembler::LoadF64LE(DoubleRegister dst, const MemOperand& opnd,
3874 ldgr(dst, scratch);
3877 void TurboAssembler::LoadF32LE(DoubleRegister dst, const MemOperand& opnd,
3881 ldgr(dst, scratch);
3951 void TurboAssembler::LoadU64LE(Register dst, const MemOperand& mem,
3953 LoadU64(dst, mem, scratch);
3956 void TurboAssembler::LoadS32LE(Register dst, const MemOperand& opnd,
3958 LoadS32(dst, opnd, scratch);
3961 void TurboAssembler::LoadU32LE(Register dst, const MemOperand& opnd,
3963 LoadU32(dst, opnd, scratch);
3966 void TurboAssembler::LoadU16LE(Register dst, const MemOperand& opnd) {
3967 LoadU16(dst, opnd);
3970 void TurboAssembler::LoadS16LE(Register dst, const MemOperand& opnd) {
3971 LoadS16(dst, opnd);
3974 void TurboAssembler::LoadV128LE(DoubleRegister dst, const MemOperand& opnd,
3977 LoadV128(dst, opnd, scratch0);
3980 void TurboAssembler::LoadF64LE(DoubleRegister dst, const MemOperand& opnd,
3983 LoadF64(dst, opnd);
3986 void TurboAssembler::LoadF32LE(DoubleRegister dst, const MemOperand& opnd,
3989 LoadF32(dst, opnd);
4025 void TurboAssembler::LoadAndTest32(Register dst, Register src) {
4026 ltr(dst, src);
4030 void TurboAssembler::LoadAndTestP(Register dst, Register src) {
4032 ltgr(dst, src);
4034 ltr(dst, src);
4039 void TurboAssembler::LoadAndTest32(Register dst, const MemOperand& mem) {
4040 lt_z(dst, mem);
4044 void TurboAssembler::LoadAndTestP(Register dst, const MemOperand& mem) {
4046 ltg(dst, mem);
4048 lt_z(dst, mem);
4053 void TurboAssembler::LoadOnConditionP(Condition cond, Register dst,
4056 locgr(cond, dst, src);
4058 locr(cond, dst, src);
4063 void TurboAssembler::LoadF64(DoubleRegister dst, const MemOperand& mem) {
4066 ld(dst, mem);
4068 ldy(dst, mem);
4073 void TurboAssembler::LoadF32(DoubleRegister dst, const MemOperand& mem) {
4075 le_z(dst, mem);
4078 ley(dst, mem);
4082 void TurboAssembler::LoadV128(Simd128Register dst, const MemOperand& mem,
4086 vl(dst, mem, Condition(0));
4090 vl(dst, MemOperand(scratch), Condition(0));
4095 void TurboAssembler::StoreF64(DoubleRegister dst, const MemOperand& mem) {
4097 std(dst, mem);
4099 stdy(dst, mem);
4124 void TurboAssembler::AddF32(DoubleRegister dst, DoubleRegister lhs,
4126 if (dst == lhs) {
4127 aebr(dst, rhs);
4128 } else if (dst == rhs) {
4129 aebr(dst, lhs);
4131 ler(dst, lhs);
4132 aebr(dst, rhs);
4136 void TurboAssembler::SubF32(DoubleRegister dst, DoubleRegister lhs,
4138 if (dst == lhs) {
4139 sebr(dst, rhs);
4140 } else if (dst == rhs) {
4141 sebr(dst, lhs);
4142 lcebr(dst, dst);
4144 ler(dst, lhs);
4145 sebr(dst, rhs);
4149 void TurboAssembler::MulF32(DoubleRegister dst, DoubleRegister lhs,
4151 if (dst == lhs) {
4152 meebr(dst, rhs);
4153 } else if (dst == rhs) {
4154 meebr(dst, lhs);
4156 ler(dst, lhs);
4157 meebr(dst, rhs);
4161 void TurboAssembler::DivF32(DoubleRegister dst, DoubleRegister lhs,
4163 if (dst == lhs) {
4164 debr(dst, rhs);
4165 } else if (dst == rhs) {
4167 StoreF32(dst, MemOperand(sp));
4168 ler(dst, lhs);
4169 deb(dst, MemOperand(sp));
4172 ler(dst, lhs);
4173 debr(dst, rhs);
4177 void TurboAssembler::AddF64(DoubleRegister dst, DoubleRegister lhs,
4179 if (dst == lhs) {
4180 adbr(dst, rhs);
4181 } else if (dst == rhs) {
4182 adbr(dst, lhs);
4184 ldr(dst, lhs);
4185 adbr(dst, rhs);
4189 void TurboAssembler::SubF64(DoubleRegister dst, DoubleRegister lhs,
4191 if (dst == lhs) {
4192 sdbr(dst, rhs);
4193 } else if (dst == rhs) {
4194 sdbr(dst, lhs);
4195 lcdbr(dst, dst);
4197 ldr(dst, lhs);
4198 sdbr(dst, rhs);
4202 void TurboAssembler::MulF64(DoubleRegister dst, DoubleRegister lhs,
4204 if (dst == lhs) {
4205 mdbr(dst, rhs);
4206 } else if (dst == rhs) {
4207 mdbr(dst, lhs);
4209 ldr(dst, lhs);
4210 mdbr(dst, rhs);
4214 void TurboAssembler::DivF64(DoubleRegister dst, DoubleRegister lhs,
4216 if (dst == lhs) {
4217 ddbr(dst, rhs);
4218 } else if (dst == rhs) {
4220 StoreF64(dst, MemOperand(sp));
4221 ldr(dst, lhs);
4222 ddb(dst, MemOperand(sp));
4225 ldr(dst, lhs);
4226 ddbr(dst, rhs);
4230 void TurboAssembler::AddFloat32(DoubleRegister dst, const MemOperand& opnd,
4233 aeb(dst, opnd);
4236 aebr(dst, scratch);
4240 void TurboAssembler::AddFloat64(DoubleRegister dst, const MemOperand& opnd,
4243 adb(dst, opnd);
4246 adbr(dst, scratch);
4250 void TurboAssembler::SubFloat32(DoubleRegister dst, const MemOperand& opnd,
4253 seb(dst, opnd);
4256 sebr(dst, scratch);
4260 void TurboAssembler::SubFloat64(DoubleRegister dst, const MemOperand& opnd,
4263 sdb(dst, opnd);
4266 sdbr(dst, scratch);
4270 void TurboAssembler::MulFloat32(DoubleRegister dst, const MemOperand& opnd,
4273 meeb(dst, opnd);
4276 meebr(dst, scratch);
4280 void TurboAssembler::MulFloat64(DoubleRegister dst, const MemOperand& opnd,
4283 mdb(dst, opnd);
4286 mdbr(dst, scratch);
4290 void TurboAssembler::DivFloat32(DoubleRegister dst, const MemOperand& opnd,
4293 deb(dst, opnd);
4296 debr(dst, scratch);
4300 void TurboAssembler::DivFloat64(DoubleRegister dst, const MemOperand& opnd,
4303 ddb(dst, opnd);
4306 ddbr(dst, scratch);
4310 void TurboAssembler::LoadF32AsF64(DoubleRegister dst, const MemOperand& opnd,
4313 ldeb(dst, opnd);
4316 ldebr(dst, scratch);
4353 void TurboAssembler::LoadS16(Register dst, Register src) {
4355 lghr(dst, src);
4357 lhr(dst, src);
4363 void TurboAssembler::LoadS16(Register dst, const MemOperand& mem,
4372 lgh(dst, MemOperand(base, scratch));
4374 lh(dst, MemOperand(base, scratch));
4378 lgh(dst, mem);
4381 lh(dst, mem);
4383 lhy(dst, mem);
4426 void TurboAssembler::ShiftLeftU32(Register dst, Register src,
4428 ShiftLeftU32(dst, src, r0, val);
4432 void TurboAssembler::ShiftLeftU32(Register dst, Register src, Register val,
4434 if (dst == src) {
4435 sll(dst, val, val2);
4437 sllk(dst, src, val, val2);
4439 DCHECK(dst != val || val == r0); // The lr/sll path clobbers val.
4440 lr(dst, src);
4441 sll(dst, val, val2);
4446 void TurboAssembler::ShiftLeftU64(Register dst, Register src,
4448 ShiftLeftU64(dst, src, r0, val);
4452 void TurboAssembler::ShiftLeftU64(Register dst, Register src, Register val,
4454 sllg(dst, src, val, val2);
4458 void TurboAssembler::ShiftRightU32(Register dst, Register src,
4460 ShiftRightU32(dst, src, r0, val);
4464 void TurboAssembler::ShiftRightU32(Register dst, Register src, Register val,
4466 if (dst == src) {
4467 srl(dst, val, val2);
4469 srlk(dst, src, val, val2);
4471 DCHECK(dst != val || val == r0); // The lr/srl path clobbers val.
4472 lr(dst, src);
4473 srl(dst, val, val2);
4477 void TurboAssembler::ShiftRightU64(Register dst, Register src, Register val,
4479 srlg(dst, src, val, val2);
4483 void TurboAssembler::ShiftRightU64(Register dst, Register src,
4485 ShiftRightU64(dst, src, r0, val);
4489 void TurboAssembler::ShiftRightS32(Register dst, Register src,
4491 ShiftRightS32(dst, src, r0, val);
4495 void TurboAssembler::ShiftRightS32(Register dst, Register src, Register val,
4497 if (dst == src) {
4498 sra(dst, val, val2);
4500 srak(dst, src, val, val2);
4502 DCHECK(dst != val || val == r0); // The lr/sra path clobbers val.
4503 lr(dst, src);
4504 sra(dst, val, val2);
4509 void TurboAssembler::ShiftRightS64(Register dst, Register src,
4511 ShiftRightS64(dst, src, r0, val);
4515 void TurboAssembler::ShiftRightS64(Register dst, Register src, Register val,
4517 srag(dst, src, val, val2);
4521 void TurboAssembler::ClearRightImm(Register dst, Register src,
4528 RotateInsertSelectBits(dst, src, Operand::Zero(), Operand(endBit),
4536 if (dst != src) mov(dst, src);
4539 nill(dst, Operand(static_cast<uint16_t>(hexMask)));
4541 nilf(dst, Operand(static_cast<uint32_t>(hexMask)));
4543 nilf(dst, Operand(static_cast<intptr_t>(0)));
4544 nihf(dst, Operand(hexMask >> 32));
4548 void TurboAssembler::Popcnt32(Register dst, Register src) {
4550 DCHECK(dst != r0);
4552 popcnt(dst, src);
4553 ShiftRightU32(r0, dst, Operand(16));
4554 ar(dst, r0);
4555 ShiftRightU32(r0, dst, Operand(8));
4556 ar(dst, r0);
4557 llgcr(dst, dst);
4561 void TurboAssembler::Popcnt64(Register dst, Register src) {
4563 DCHECK(dst != r0);
4565 popcnt(dst, src);
4566 ShiftRightU64(r0, dst, Operand(32));
4567 AddS64(dst, r0);
4568 ShiftRightU64(r0, dst, Operand(16));
4569 AddS64(dst, r0);
4570 ShiftRightU64(r0, dst, Operand(8));
4571 AddS64(dst, r0);
4572 LoadU8(dst, dst);
4576 void TurboAssembler::SwapP(Register src, Register dst, Register scratch) {
4577 if (src == dst) return;
4578 DCHECK(!AreAliased(src, dst, scratch));
4580 mov(src, dst);
4581 mov(dst, scratch);
4584 void TurboAssembler::SwapP(Register src, MemOperand dst, Register scratch) {
4585 if (dst.rx() != r0) DCHECK(!AreAliased(src, dst.rx(), scratch));
4586 if (dst.rb() != r0) DCHECK(!AreAliased(src, dst.rb(), scratch));
4589 LoadU64(src, dst);
4590 StoreU64(scratch, dst);
4593 void TurboAssembler::SwapP(MemOperand src, MemOperand dst, Register scratch_0,
4597 if (dst.rx() != r0) DCHECK(!AreAliased(dst.rx(), scratch_0, scratch_1));
4598 if (dst.rb() != r0) DCHECK(!AreAliased(dst.rb(), scratch_0, scratch_1));
4601 LoadU64(scratch_1, dst);
4602 StoreU64(scratch_0, dst);
4606 void TurboAssembler::SwapFloat32(DoubleRegister src, DoubleRegister dst,
4608 if (src == dst) return;
4609 DCHECK(!AreAliased(src, dst, scratch));
4611 ldr(src, dst);
4612 ldr(dst, scratch);
4615 void TurboAssembler::SwapFloat32(DoubleRegister src, MemOperand dst,
4619 LoadF32(src, dst);
4620 StoreF32(scratch, dst);
4623 void TurboAssembler::SwapFloat32(MemOperand src, MemOperand dst,
4629 LoadF32(d0, dst);
4630 StoreF32(scratch, dst);
4637 void TurboAssembler::SwapDouble(DoubleRegister src, DoubleRegister dst,
4639 if (src == dst) return;
4640 DCHECK(!AreAliased(src, dst, scratch));
4642 ldr(src, dst);
4643 ldr(dst, scratch);
4646 void TurboAssembler::SwapDouble(DoubleRegister src, MemOperand dst,
4650 LoadF64(src, dst);
4651 StoreF64(scratch, dst);
4654 void TurboAssembler::SwapDouble(MemOperand src, MemOperand dst,
4660 LoadF64(d0, dst);
4661 StoreF64(scratch, dst);
4668 void TurboAssembler::SwapSimd128(Simd128Register src, Simd128Register dst,
4670 if (src == dst) return;
4672 vlr(src, dst, Condition(0), Condition(0), Condition(0));
4673 vlr(dst, scratch, Condition(0), Condition(0), Condition(0));
4676 void TurboAssembler::SwapSimd128(Simd128Register src, MemOperand dst,
4680 LoadV128(src, dst, ip);
4681 StoreV128(scratch, dst, ip);
4684 void TurboAssembler::SwapSimd128(MemOperand src, MemOperand dst,
4690 LoadV128(d0, dst, ip);
4691 StoreV128(scratch, dst, ip);
4698 void TurboAssembler::ComputeCodeStartAddress(Register dst) {
4699 larl(dst, Operand(-pc_offset() / 2));
4702 void TurboAssembler::LoadPC(Register dst) {
4704 larl(dst, ¤t_pc);
4846 void TurboAssembler::CountLeadingZerosU32(Register dst, Register src,
4848 llgfr(dst, src);
4850 dst); // will modify a register pair scratch and scratch + 1
4851 AddS32(dst, scratch_pair, Operand(-32));
4854 void TurboAssembler::CountLeadingZerosU64(Register dst, Register src,
4858 mov(dst, scratch_pair);
4861 void TurboAssembler::CountTrailingZerosU32(Register dst, Register src,
4865 DCHECK(!AreAliased(dst, scratch0, scratch1));
4871 mov(dst, Operand(32));
4877 mov(dst, Operand(63));
4878 SubS64(dst, scratch0);
4882 void TurboAssembler::CountTrailingZerosU64(Register dst, Register src,
4886 DCHECK(!AreAliased(dst, scratch0, scratch1));
4892 mov(dst, Operand(64));
4897 mov(dst, Operand(63));
4898 SubS64(dst, scratch0);
5115 void TurboAssembler::F64x2Splat(Simd128Register dst, Simd128Register src) {
5116 vrep(dst, src, Operand(0), Condition(3));
5119 void TurboAssembler::F32x4Splat(Simd128Register dst, Simd128Register src) {
5120 vrep(dst, src, Operand(0), Condition(2));
5123 void TurboAssembler::I64x2Splat(Simd128Register dst, Register src) {
5124 vlvg(dst, src, MemOperand(r0, 0), Condition(3));
5125 vrep(dst, dst, Operand(0), Condition(3));
5128 void TurboAssembler::I32x4Splat(Simd128Register dst, Register src) {
5129 vlvg(dst, src, MemOperand(r0, 0), Condition(2));
5130 vrep(dst, dst, Operand(0), Condition(2));
5133 void TurboAssembler::I16x8Splat(Simd128Register dst, Register src) {
5134 vlvg(dst, src, MemOperand(r0, 0), Condition(1));
5135 vrep(dst, dst, Operand(0), Condition(1));
5138 void TurboAssembler::I8x16Splat(Simd128Register dst, Register src) {
5139 vlvg(dst, src, MemOperand(r0, 0), Condition(0));
5140 vrep(dst, dst, Operand(0), Condition(0));
5143 void TurboAssembler::F64x2ExtractLane(DoubleRegister dst, Simd128Register src,
5145 vrep(dst, src, Operand(1 - imm_lane_idx), Condition(3));
5148 void TurboAssembler::F32x4ExtractLane(DoubleRegister dst, Simd128Register src,
5150 vrep(dst, src, Operand(3 - imm_lane_idx), Condition(2));
5153 void TurboAssembler::I64x2ExtractLane(Register dst, Simd128Register src,
5155 vlgv(dst, src, MemOperand(r0, 1 - imm_lane_idx), Condition(3));
5158 void TurboAssembler::I32x4ExtractLane(Register dst, Simd128Register src,
5160 vlgv(dst, src, MemOperand(r0, 3 - imm_lane_idx), Condition(2));
5163 void TurboAssembler::I16x8ExtractLaneU(Register dst, Simd128Register src,
5165 vlgv(dst, src, MemOperand(r0, 7 - imm_lane_idx), Condition(1));
5168 void TurboAssembler::I16x8ExtractLaneS(Register dst, Simd128Register src,
5171 lghr(dst, scratch);
5174 void TurboAssembler::I8x16ExtractLaneU(Register dst, Simd128Register src,
5176 vlgv(dst, src, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
5179 void TurboAssembler::I8x16ExtractLaneS(Register dst, Simd128Register src,
5182 lgbr(dst, scratch);
5185 void TurboAssembler::F64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
5189 if (src1 != dst) {
5190 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5192 vlvg(dst, scratch, MemOperand(r0, 1 - imm_lane_idx), Condition(3));
5195 void TurboAssembler::F32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
5199 if (src1 != dst) {
5200 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5202 vlvg(dst, scratch, MemOperand(r0, 3 - imm_lane_idx), Condition(2));
5205 void TurboAssembler::I64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
5208 if (src1 != dst) {
5209 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5211 vlvg(dst, src2, MemOperand(r0, 1 - imm_lane_idx), Condition(3));
5214 void TurboAssembler::I32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
5217 if (src1 != dst) {
5218 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5220 vlvg(dst, src2, MemOperand(r0, 3 - imm_lane_idx), Condition(2));
5223 void TurboAssembler::I16x8ReplaceLane(Simd128Register dst, Simd128Register src1,
5226 if (src1 != dst) {
5227 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5229 vlvg(dst, src2, MemOperand(r0, 7 - imm_lane_idx), Condition(1));
5232 void TurboAssembler::I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
5235 if (src1 != dst) {
5236 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5238 vlvg(dst, src2, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
5241 void TurboAssembler::S128Not(Simd128Register dst, Simd128Register src) {
5242 vno(dst, src, src, Condition(0), Condition(0), Condition(0));
5245 void TurboAssembler::S128Zero(Simd128Register dst, Simd128Register src) {
5246 vx(dst, src, src, Condition(0), Condition(0), Condition(0));
5249 void TurboAssembler::S128AllOnes(Simd128Register dst, Simd128Register src) {
5250 vceq(dst, src, src, Condition(0), Condition(3));
5253 void TurboAssembler::S128Select(Simd128Register dst, Simd128Register src1,
5255 vsel(dst, src1, src2, mask, Condition(0), Condition(0));
5296 void TurboAssembler::name(Simd128Register dst, Simd128Register src) { \
5297 op(dst, src, Condition(c1), Condition(c2), Condition(c3)); \
5317 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5319 op(dst, src1, src2, Condition(c1), Condition(c2)); \
5374 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5376 op(dst, src1, src2, Condition(c1), Condition(c2), Condition(c3)); \
5397 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5401 op(dst, src1, scratch, Condition(0), Condition(0), Condition(c1)); \
5403 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5407 name(dst, src1, scratch1, scratch2); \
5428 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5432 mul_odd(dst, src1, src2, Condition(0), Condition(0), Condition(mode)); \
5433 merge(dst, scratch, dst, Condition(0), Condition(0), Condition(mode + 1)); \
5446 void TurboAssembler::name(Register dst, Simd128Register src, \
5449 xgr(dst, dst); \
5454 locgr(Condition(8), dst, scratch1); \
5467 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5469 op(dst, src2, src3, src1, Condition(c1), Condition(0)); \
5475 void TurboAssembler::I64x2Mul(Simd128Register dst, Simd128Register src1,
5487 vlvgp(dst, scratch1, scratch2);
5490 void TurboAssembler::F64x2Ne(Simd128Register dst, Simd128Register src1,
5492 vfce(dst, src1, src2, Condition(0), Condition(0), Condition(3));
5493 vno(dst, dst, dst, Condition(0), Condition(0), Condition(3));
5496 void TurboAssembler::F64x2Lt(Simd128Register dst, Simd128Register src1,
5498 vfch(dst, src2, src1, Condition(0), Condition(0), Condition(3));
5501 void TurboAssembler::F64x2Le(Simd128Register dst, Simd128Register src1,
5503 vfche(dst, src2, src1, Condition(0), Condition(0), Condition(3));
5506 void TurboAssembler::F32x4Ne(Simd128Register dst, Simd128Register src1,
5508 vfce(dst, src1, src2, Condition(0), Condition(0), Condition(2));
5509 vno(dst, dst, dst, Condition(0), Condition(0), Condition(2));
5512 void TurboAssembler::F32x4Lt(Simd128Register dst, Simd128Register src1,
5514 vfch(dst, src2, src1, Condition(0), Condition(0), Condition(2));
5517 void TurboAssembler::F32x4Le(Simd128Register dst, Simd128Register src1,
5519 vfche(dst, src2, src1, Condition(0), Condition(0), Condition(2));
5522 void TurboAssembler::I64x2Ne(Simd128Register dst, Simd128Register src1,
5524 vceq(dst, src1, src2, Condition(0), Condition(3));
5525 vno(dst, dst, dst, Condition(0), Condition(0), Condition(3));
5528 void TurboAssembler::I64x2GeS(Simd128Register dst, Simd128Register src1,
5531 vch(dst, src2, src1, Condition(0), Condition(3));
5532 vno(dst, dst, dst, Condition(0), Condition(0), Condition(3));
5535 void TurboAssembler::I32x4Ne(Simd128Register dst, Simd128Register src1,
5537 vceq(dst, src1, src2, Condition(0), Condition(2));
5538 vno(dst, dst, dst, Condition(0), Condition(0), Condition(2));
5541 void TurboAssembler::I32x4GeS(Simd128Register dst, Simd128Register src1,
5544 vch(dst, src2, src1, Condition(0), Condition(2));
5545 vno(dst, dst, dst, Condition(0), Condition(0), Condition(2));
5548 void TurboAssembler::I32x4GeU(Simd128Register dst, Simd128Register src1,
5551 vchl(dst, src1, src2, Condition(0), Condition(2));
5552 vo(dst, dst, scratch, Condition(0), Condition(0), Condition(2));
5555 void TurboAssembler::I16x8Ne(Simd128Register dst, Simd128Register src1,
5557 vceq(dst, src1, src2, Condition(0), Condition(1));
5558 vno(dst, dst, dst, Condition(0), Condition(0), Condition(1));
5561 void TurboAssembler::I16x8GeS(Simd128Register dst, Simd128Register src1,
5564 vch(dst, src2, src1, Condition(0), Condition(1));
5565 vno(dst, dst, dst, Condition(0), Condition(0), Condition(1));
5568 void TurboAssembler::I16x8GeU(Simd128Register dst, Simd128Register src1,
5571 vchl(dst, src1, src2, Condition(0), Condition(1));
5572 vo(dst, dst, scratch, Condition(0), Condition(0), Condition(1));
5575 void TurboAssembler::I8x16Ne(Simd128Register dst, Simd128Register src1,
5577 vceq(dst, src1, src2, Condition(0), Condition(0));
5578 vno(dst, dst, dst, Condition(0), Condition(0), Condition(0));
5581 void TurboAssembler::I8x16GeS(Simd128Register dst, Simd128Register src1,
5584 vch(dst, src2, src1, Condition(0), Condition(0));
5585 vno(dst, dst, dst, Condition(0), Condition(0), Condition(0));
5588 void TurboAssembler::I8x16GeU(Simd128Register dst, Simd128Register src1,
5591 vchl(dst, src1, src2, Condition(0), Condition(0));
5592 vo(dst, dst, scratch, Condition(0), Condition(0), Condition(0));
5595 void TurboAssembler::I64x2BitMask(Register dst, Simd128Register src,
5600 vlgv(dst, scratch2, MemOperand(r0, 7), Condition(0));
5603 void TurboAssembler::I32x4BitMask(Register dst, Simd128Register src,
5608 vlgv(dst, scratch2, MemOperand(r0, 7), Condition(0));
5611 void TurboAssembler::I16x8BitMask(Register dst, Simd128Register src,
5616 vlgv(dst, scratch2, MemOperand(r0, 7), Condition(0));
5619 void TurboAssembler::F64x2ConvertLowI32x4S(Simd128Register dst,
5621 vupl(dst, src, Condition(0), Condition(0), Condition(2));
5622 vcdg(dst, dst, Condition(4), Condition(0), Condition(3));
5625 void TurboAssembler::F64x2ConvertLowI32x4U(Simd128Register dst,
5627 vupll(dst, src, Condition(0), Condition(0), Condition(2));
5628 vcdlg(dst, dst, Condition(4), Condition(0), Condition(3));
5631 void TurboAssembler::I8x16BitMask(Register dst, Simd128Register src,
5638 vlgv(dst, scratch3, MemOperand(r0, 3), Condition(1));
5641 void TurboAssembler::V128AnyTrue(Register dst, Simd128Register src,
5643 mov(dst, Operand(1));
5646 locgr(Condition(8), dst, scratch);
5649 #define CONVERT_FLOAT_TO_INT32(convert, dst, src, scratch1, scratch2) \
5654 vlvg(dst, scratch2, MemOperand(r0, index), Condition(2)); \
5656 void TurboAssembler::I32x4SConvertF32x4(Simd128Register dst,
5662 vn(dst, src, scratch1, Condition(0), Condition(0), Condition(0));
5664 vcgd(dst, dst, Condition(5), Condition(0), Condition(2));
5666 CONVERT_FLOAT_TO_INT32(ConvertFloat32ToInt32, dst, dst, scratch1, scratch2)
5670 void TurboAssembler::I32x4UConvertF32x4(Simd128Register dst,
5677 vclgd(dst, src, Condition(5), Condition(0), Condition(2));
5679 CONVERT_FLOAT_TO_INT32(ConvertFloat32ToUnsignedInt32, dst, src, scratch1,
5685 #define CONVERT_INT32_TO_FLOAT(convert, dst, src, scratch1, scratch2) \
5690 vlvg(dst, scratch2, MemOperand(r0, index), Condition(2)); \
5692 void TurboAssembler::F32x4SConvertI32x4(Simd128Register dst,
5697 vcdg(dst, src, Condition(4), Condition(0), Condition(2));
5699 CONVERT_INT32_TO_FLOAT(ConvertIntToFloat, dst, src, scratch1, scratch2)
5702 void TurboAssembler::F32x4UConvertI32x4(Simd128Register dst,
5707 vcdlg(dst, src, Condition(4), Condition(0), Condition(2));
5709 CONVERT_INT32_TO_FLOAT(ConvertUnsignedIntToFloat, dst, src, scratch1,
5715 void TurboAssembler::I16x8SConvertI32x4(Simd128Register dst,
5718 vpks(dst, src2, src1, Condition(0), Condition(2));
5721 void TurboAssembler::I8x16SConvertI16x8(Simd128Register dst,
5724 vpks(dst, src2, src1, Condition(0), Condition(1));
5727 #define VECTOR_PACK_UNSIGNED(dst, src1, src2, scratch, mode) \
5732 vmx(dst, src2, kDoubleRegZero, Condition(0), Condition(0), Condition(mode));
5733 void TurboAssembler::I16x8UConvertI32x4(Simd128Register dst,
5738 VECTOR_PACK_UNSIGNED(dst, src1, src2, scratch, 2)
5739 vpkls(dst, dst, scratch, Condition(0), Condition(2));
5742 void TurboAssembler::I8x16UConvertI16x8(Simd128Register dst,
5747 VECTOR_PACK_UNSIGNED(dst, src1, src2, scratch, 1)
5748 vpkls(dst, dst, scratch, Condition(0), Condition(1));
5752 #define BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, op, extract_high, \
5754 DCHECK(dst != scratch1 && dst != scratch2); \
5755 DCHECK(dst != src1 && dst != src2); \
5758 op(dst, scratch1, scratch2, Condition(0), Condition(0), \
5764 void TurboAssembler::I16x8AddSatS(Simd128Register dst, Simd128Register src1,
5768 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuph, vupl, 1)
5769 vpks(dst, dst, scratch1, Condition(0), Condition(2));
5772 void TurboAssembler::I16x8SubSatS(Simd128Register dst, Simd128Register src1,
5776 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuph, vupl, 1)
5777 vpks(dst, dst, scratch1, Condition(0), Condition(2));
5780 void TurboAssembler::I16x8AddSatU(Simd128Register dst, Simd128Register src1,
5784 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuplh, vupll, 1)
5785 vpkls(dst, dst, scratch1, Condition(0), Condition(2));
5788 void TurboAssembler::I16x8SubSatU(Simd128Register dst, Simd128Register src1,
5792 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuplh, vupll, 1)
5796 vmx(dst, kDoubleRegZero, dst, Condition(0), Condition(0), Condition(2));
5799 vpkls(dst, dst, scratch1, Condition(0), Condition(2));
5802 void TurboAssembler::I8x16AddSatS(Simd128Register dst, Simd128Register src1,
5806 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuph, vupl, 0)
5807 vpks(dst, dst, scratch1, Condition(0), Condition(1));
5810 void TurboAssembler::I8x16SubSatS(Simd128Register dst, Simd128Register src1,
5814 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuph, vupl, 0)
5815 vpks(dst, dst, scratch1, Condition(0), Condition(1));
5818 void TurboAssembler::I8x16AddSatU(Simd128Register dst, Simd128Register src1,
5822 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuplh, vupll, 0)
5823 vpkls(dst, dst, scratch1, Condition(0), Condition(1));
5826 void TurboAssembler::I8x16SubSatU(Simd128Register dst, Simd128Register src1,
5830 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuplh, vupll, 0)
5834 vmx(dst, kDoubleRegZero, dst, Condition(0), Condition(0), Condition(1));
5837 vpkls(dst, dst, scratch1, Condition(0), Condition(1));
5841 void TurboAssembler::F64x2PromoteLowF32x4(Simd128Register dst,
5854 vlvgp(dst, scratch3, scratch4);
5857 void TurboAssembler::F32x4DemoteF64x2Zero(Simd128Register dst,
5870 vx(dst, dst, dst, Condition(0), Condition(0), Condition(2));
5871 vlvg(dst, scratch3, MemOperand(r0, 2), Condition(2));
5872 vlvg(dst, scratch4, MemOperand(r0, 3), Condition(2));
5875 #define EXT_ADD_PAIRWISE(dst, src, scratch1, scratch2, lane_size, mul_even, \
5883 va(dst, scratch1, scratch2, Condition(0), Condition(0), \
5885 void TurboAssembler::I32x4ExtAddPairwiseI16x8S(Simd128Register dst,
5889 EXT_ADD_PAIRWISE(dst, src, scratch1, scratch2, 1, vme, vmo)
5892 void TurboAssembler::I32x4ExtAddPairwiseI16x8U(Simd128Register dst,
5897 vsum(dst, src, scratch, Condition(0), Condition(0), Condition(1));
5900 void TurboAssembler::I16x8ExtAddPairwiseI8x16S(Simd128Register dst,
5904 EXT_ADD_PAIRWISE(dst, src, scratch1, scratch2, 0, vme, vmo)
5907 void TurboAssembler::I16x8ExtAddPairwiseI8x16U(Simd128Register dst,
5911 EXT_ADD_PAIRWISE(dst, src, scratch1, scratch2, 0, vmle, vmlo)
5915 void TurboAssembler::I32x4TruncSatF64x2SZero(Simd128Register dst,
5923 vx(dst, dst, dst, Condition(0), Condition(0), Condition(2));
5924 vpks(dst, dst, scratch, Condition(0), Condition(3));
5927 void TurboAssembler::I32x4TruncSatF64x2UZero(Simd128Register dst,
5931 vx(dst, dst, dst, Condition(0), Condition(0), Condition(2));
5932 vpkls(dst, dst, scratch, Condition(0), Condition(3));
5935 void TurboAssembler::S128Const(Simd128Register dst, uint64_t high, uint64_t low,
5939 vlvgp(dst, scratch2, scratch1);
5942 void TurboAssembler::I8x16Swizzle(Simd128Register dst, Simd128Register src1,
5956 vlvgp(dst, scratch2, scratch1);
5959 vperm(dst, dst, scratch3, scratch4, Condition(0), Condition(0));
5962 void TurboAssembler::I8x16Shuffle(Simd128Register dst, Simd128Register src1,
5969 vperm(dst, src1, src2, scratch3, Condition(0), Condition(0));
5972 void TurboAssembler::I32x4DotI16x8S(Simd128Register dst, Simd128Register src1,
5976 vmo(dst, src1, src2, Condition(0), Condition(0), Condition(1));
5977 va(dst, scratch, dst, Condition(0), Condition(0), Condition(2));
5990 void TurboAssembler::I16x8Q15MulRSatS(Simd128Register dst, Simd128Register src1,
5998 Q15_MUL_ROAUND(dst, src1, src2, scratch1, scratch3, vuph)
5999 vpks(dst, dst, scratch2, Condition(0), Condition(2));
6021 Simd128Register dst, const MemOperand& mem, Register scratch) { \
6023 vector_instr(dst, mem, Condition(condition)); \
6027 vlvg(dst, scratch, MemOperand(r0, 0), Condition(condition)); \
6028 vrep(dst, dst, Operand(0), Condition(condition)); \
6044 Simd128Register dst, const MemOperand& mem, Register scratch) { \
6046 vlebrg(dst, mem, Condition(0)); \
6049 vlvg(dst, scratch, MemOperand(r0, 0), Condition(3)); \
6051 unpack_instr(dst, dst, Condition(0), Condition(0), Condition(condition)); \
6057 void TurboAssembler::LoadV32ZeroLE(Simd128Register dst, const MemOperand& mem,
6059 vx(dst, dst, dst, Condition(0), Condition(0), Condition(0));
6061 vlebrf(dst, mem, Condition(3));
6065 vlvg(dst, scratch, MemOperand(r0, 3), Condition(2));
6068 void TurboAssembler::LoadV64ZeroLE(Simd128Register dst, const MemOperand& mem,
6070 vx(dst, dst, dst, Condition(0), Condition(0), Condition(0));
6072 vlebrg(dst, mem, Condition(1));
6076 vlvg(dst, scratch, MemOperand(r0, 1), Condition(3));
6086 void TurboAssembler::LoadLane##name##LE(Simd128Register dst, \
6090 vector_instr(dst, mem, Condition(lane)); \
6094 vlvg(dst, scratch, MemOperand(r0, lane), Condition(condition)); \