Lines Matching defs:src2
2279 DoubleRegister src2) {
2280 if (src2 == d0) {
2282 Move(d2, src2);
2286 Move(d2, src2);
2502 instr(dst, src2); \
2507 const MemOperand& src2) {
2511 void TurboAssembler::MulHighS32(Register dst, Register src1, Register src2) {
2512 if (dst == src2) {
2513 std::swap(src1, src2);
2519 const Operand& src2) {
2528 instr(r0, src2); \
2533 const MemOperand& src2) {
2537 void TurboAssembler::MulHighU32(Register dst, Register src1, Register src2) {
2542 const Operand& src2) {
2545 USE(src2);
2554 instr(dst, src2); \
2559 const MemOperand& src2) {
2561 if (src2.rx() == dst || src2.rb() == dst) dst = r0;
2567 Register src2) {
2568 if (dst == src2) {
2569 std::swap(src1, src2);
2575 const Operand& src2) {
2584 instr(r0, src2); \
2589 const MemOperand& src2) {
2593 void TurboAssembler::DivS32(Register dst, Register src1, Register src2) {
2603 instr(r0, src2); \
2608 const MemOperand& src2) {
2612 void TurboAssembler::DivU32(Register dst, Register src1, Register src2) {
2621 instr(r0, src2); \
2626 const MemOperand& src2) {
2630 void TurboAssembler::DivS64(Register dst, Register src1, Register src2) {
2640 instr(r0, src2); \
2645 const MemOperand& src2) {
2649 void TurboAssembler::DivU64(Register dst, Register src1, Register src2) {
2658 instr(r0, src2); \
2663 const MemOperand& src2) {
2667 void TurboAssembler::ModS32(Register dst, Register src1, Register src2) {
2677 instr(r0, src2); \
2682 const MemOperand& src2) {
2686 void TurboAssembler::ModU32(Register dst, Register src1, Register src2) {
2695 instr(r0, src2); \
2700 const MemOperand& src2) {
2704 void TurboAssembler::ModS64(Register dst, Register src1, Register src2) {
2714 instr(r0, src2); \
2719 const MemOperand& src2) {
2723 void TurboAssembler::ModU64(Register dst, Register src1, Register src2) {
2808 // Add 32-bit (Register dst = Register src1 + Register src2)
2809 void TurboAssembler::AddS32(Register dst, Register src1, Register src2) {
2810 if (dst != src1 && dst != src2) {
2814 ark(dst, src1, src2);
2819 } else if (dst == src2) {
2820 src2 = src1;
2822 ar(dst, src2);
2825 // Add Pointer Size (Register dst = Register src1 + Register src2)
2826 void TurboAssembler::AddS64(Register dst, Register src1, Register src2) {
2827 if (dst != src1 && dst != src2) {
2831 agrk(dst, src1, src2);
2836 } else if (dst == src2) {
2837 src2 = src1;
2839 agr(dst, src2);
2877 // Add Logical 32-bit (Register dst = Register src1 + Register src2)
2878 void TurboAssembler::AddU32(Register dst, Register src1, Register src2) {
2879 if (dst != src2 && dst != src1) {
2881 alr(dst, src2);
2882 } else if (dst != src2) {
2885 alr(dst, src2);
2887 // dst == src2
2888 DCHECK(dst == src2);
2903 void TurboAssembler::AddU64(Register dst, Register src1, Register src2) {
2904 if (dst != src2 && dst != src1) {
2906 algrk(dst, src1, src2);
2909 algr(dst, src2);
2911 } else if (dst != src2) {
2914 algr(dst, src2);
2916 // dst == src2
2917 DCHECK(dst == src2);
2941 // Subtract Logical 32-bit (Register dst = Register src1 - Register src2)
2942 void TurboAssembler::SubU32(Register dst, Register src1, Register src2) {
2943 if (dst != src2 && dst != src1) {
2945 slr(dst, src2);
2946 } else if (dst != src2) {
2949 slr(dst, src2);
2951 // dst == src2
2952 DCHECK(dst == src2);
2993 void TurboAssembler::SubS32(Register dst, Register src1, Register src2) {
2996 srk(dst, src1, src2);
2999 if (dst != src1 && dst != src2) lr(dst, src1);
3001 if (dst != src1 && dst == src2) {
3008 sr(dst, src2);
3013 void TurboAssembler::SubS64(Register dst, Register src1, Register src2) {
3016 sgrk(dst, src1, src2);
3019 if (dst != src1 && dst != src2) mov(dst, src1);
3021 if (dst != src1 && dst == src2) {
3028 SubS64(dst, src2);
3107 void TurboAssembler::And(Register dst, Register src1, Register src2) {
3108 if (dst != src1 && dst != src2) {
3112 nrk(dst, src1, src2);
3117 } else if (dst == src2) {
3118 src2 = src1;
3120 And(dst, src2);
3124 void TurboAssembler::AndP(Register dst, Register src1, Register src2) {
3125 if (dst != src1 && dst != src2) {
3129 ngrk(dst, src1, src2);
3134 } else if (dst == src2) {
3135 src2 = src1;
3137 AndP(dst, src2);
3230 void TurboAssembler::Or(Register dst, Register src1, Register src2) {
3231 if (dst != src1 && dst != src2) {
3235 ork(dst, src1, src2);
3240 } else if (dst == src2) {
3241 src2 = src1;
3243 Or(dst, src2);
3247 void TurboAssembler::OrP(Register dst, Register src1, Register src2) {
3248 if (dst != src1 && dst != src2) {
3252 ogrk(dst, src1, src2);
3257 } else if (dst == src2) {
3258 src2 = src1;
3260 OrP(dst, src2);
3318 void TurboAssembler::Xor(Register dst, Register src1, Register src2) {
3319 if (dst != src1 && dst != src2) {
3323 xrk(dst, src1, src2);
3328 } else if (dst == src2) {
3329 src2 = src1;
3331 Xor(dst, src2);
3335 void TurboAssembler::XorP(Register dst, Register src1, Register src2) {
3336 if (dst != src1 && dst != src2) {
3340 xgrk(dst, src1, src2);
3345 } else if (dst == src2) {
3346 src2 = src1;
3348 XorP(dst, src2);
3433 void TurboAssembler::CmpS32(Register src1, Register src2) { cr_z(src1, src2); }
3436 void TurboAssembler::CmpS64(Register src1, Register src2) { cgr(src1, src2); }
3656 void TurboAssembler::StoreMultipleP(Register src1, Register src2,
3660 stmg(src1, src2, mem);
3663 stm(src1, src2, mem);
3666 stmy(src1, src2, mem);
3681 void TurboAssembler::StoreMultipleW(Register src1, Register src2,
3684 stm(src1, src2, mem);
3687 stmy(src1, src2, mem);
5186 DoubleRegister src2, uint8_t imm_lane_idx,
5188 vlgv(scratch, src2, MemOperand(r0, 0), Condition(3));
5196 DoubleRegister src2, uint8_t imm_lane_idx,
5198 vlgv(scratch, src2, MemOperand(r0, 0), Condition(2));
5206 Register src2, uint8_t imm_lane_idx,
5211 vlvg(dst, src2, MemOperand(r0, 1 - imm_lane_idx), Condition(3));
5215 Register src2, uint8_t imm_lane_idx,
5220 vlvg(dst, src2, MemOperand(r0, 3 - imm_lane_idx), Condition(2));
5224 Register src2, uint8_t imm_lane_idx,
5229 vlvg(dst, src2, MemOperand(r0, 7 - imm_lane_idx), Condition(1));
5233 Register src2, uint8_t imm_lane_idx,
5238 vlvg(dst, src2, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
5254 Simd128Register src2, Simd128Register mask) {
5255 vsel(dst, src1, src2, mask, Condition(0), Condition(0));
5318 Simd128Register src2) { \
5319 op(dst, src1, src2, Condition(c1), Condition(c2)); \
5375 Simd128Register src2) { \
5376 op(dst, src1, src2, Condition(c1), Condition(c2), Condition(c3)); \
5398 Register src2, Simd128Register scratch) { \
5399 vlvg(scratch, src2, MemOperand(r0, 0), Condition(c1)); \
5404 const Operand& src2, Register scratch1, \
5406 mov(scratch1, src2); \
5429 Simd128Register src2, Simd128Register scratch) { \
5430 mul_even(scratch, src1, src2, Condition(0), Condition(0), \
5432 mul_odd(dst, src1, src2, Condition(0), Condition(0), Condition(mode)); \
5468 Simd128Register src2, Simd128Register src3) { \
5469 op(dst, src2, src3, src1, Condition(c1), Condition(0)); \
5476 Simd128Register src2, Register scratch1,
5482 vlgv(scratch_2, src2, MemOperand(r0, i), Condition(3));
5491 Simd128Register src2) {
5492 vfce(dst, src1, src2, Condition(0), Condition(0), Condition(3));
5497 Simd128Register src2) {
5498 vfch(dst, src2, src1, Condition(0), Condition(0), Condition(3));
5502 Simd128Register src2) {
5503 vfche(dst, src2, src1, Condition(0), Condition(0), Condition(3));
5507 Simd128Register src2) {
5508 vfce(dst, src1, src2, Condition(0), Condition(0), Condition(2));
5513 Simd128Register src2) {
5514 vfch(dst, src2, src1, Condition(0), Condition(0), Condition(2));
5518 Simd128Register src2) {
5519 vfche(dst, src2, src1, Condition(0), Condition(0), Condition(2));
5523 Simd128Register src2) {
5524 vceq(dst, src1, src2, Condition(0), Condition(3));
5529 Simd128Register src2) {
5531 vch(dst, src2, src1, Condition(0), Condition(3));
5536 Simd128Register src2) {
5537 vceq(dst, src1, src2, Condition(0), Condition(2));
5542 Simd128Register src2) {
5544 vch(dst, src2, src1, Condition(0), Condition(2));
5549 Simd128Register src2, Simd128Register scratch) {
5550 vceq(scratch, src1, src2, Condition(0), Condition(2));
5551 vchl(dst, src1, src2, Condition(0), Condition(2));
5556 Simd128Register src2) {
5557 vceq(dst, src1, src2, Condition(0), Condition(1));
5562 Simd128Register src2) {
5564 vch(dst, src2, src1, Condition(0), Condition(1));
5569 Simd128Register src2, Simd128Register scratch) {
5570 vceq(scratch, src1, src2, Condition(0), Condition(1));
5571 vchl(dst, src1, src2, Condition(0), Condition(1));
5576 Simd128Register src2) {
5577 vceq(dst, src1, src2, Condition(0), Condition(0));
5582 Simd128Register src2) {
5584 vch(dst, src2, src1, Condition(0), Condition(0));
5589 Simd128Register src2, Simd128Register scratch) {
5590 vceq(scratch, src1, src2, Condition(0), Condition(0));
5591 vchl(dst, src1, src2, Condition(0), Condition(0));
5717 Simd128Register src2) {
5718 vpks(dst, src2, src1, Condition(0), Condition(2));
5723 Simd128Register src2) {
5724 vpks(dst, src2, src1, Condition(0), Condition(1));
5727 #define VECTOR_PACK_UNSIGNED(dst, src1, src2, scratch, mode) \
5732 vmx(dst, src2, kDoubleRegZero, Condition(0), Condition(0), Condition(mode));
5735 Simd128Register src2,
5738 VECTOR_PACK_UNSIGNED(dst, src1, src2, scratch, 2)
5744 Simd128Register src2,
5747 VECTOR_PACK_UNSIGNED(dst, src1, src2, scratch, 1)
5752 #define BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, op, extract_high, \
5755 DCHECK(dst != src1 && dst != src2); \
5757 extract_high(scratch2, src2, Condition(0), Condition(0), Condition(mode)); \
5761 extract_low(scratch2, src2, Condition(0), Condition(0), Condition(mode)); \
5765 Simd128Register src2,
5768 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuph, vupl, 1)
5773 Simd128Register src2,
5776 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuph, vupl, 1)
5781 Simd128Register src2,
5784 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuplh, vupll, 1)
5789 Simd128Register src2,
5792 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuplh, vupll, 1)
5803 Simd128Register src2,
5806 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuph, vupl, 0)
5811 Simd128Register src2,
5814 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuph, vupl, 0)
5819 Simd128Register src2,
5822 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuplh, vupll, 0)
5827 Simd128Register src2,
5830 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuplh, vupll, 0)
5943 Simd128Register src2, Register scratch1,
5946 DCHECK(!AreAliased(src1, src2, scratch3, scratch4));
5950 vmnl(scratch4, src2, scratch3, Condition(0), Condition(0), Condition(0));
5963 Simd128Register src2, uint64_t high,
5969 vperm(dst, src1, src2, scratch3, Condition(0), Condition(0));
5973 Simd128Register src2,
5975 vme(scratch, src1, src2, Condition(0), Condition(0), Condition(1));
5976 vmo(dst, src1, src2, Condition(0), Condition(0), Condition(1));
5980 #define Q15_MUL_ROAUND(accumulator, src1, src2, const_val, scratch, unpack) \
5982 unpack(accumulator, src2, Condition(0), Condition(0), Condition(1)); \
5991 Simd128Register src2,
5995 DCHECK(!AreAliased(src1, src2, scratch1, scratch2, scratch3));
5997 Q15_MUL_ROAUND(scratch2, src1, src2, scratch1, scratch3, vupl)
5998 Q15_MUL_ROAUND(dst, src1, src2, scratch1, scratch3, vuph)