Lines Matching defs:src1
2278 void TurboAssembler::MovToFloatParameters(DoubleRegister src1,
2281 DCHECK(src1 != d2);
2283 Move(d0, src1);
2285 Move(d0, src1);
2483 void TurboAssembler::MulS32(Register dst, const MemOperand& src1) {
2484 if (is_uint12(src1.offset())) {
2485 ms(dst, src1);
2486 } else if (is_int20(src1.offset())) {
2487 msy(dst, src1);
2493 void TurboAssembler::MulS32(Register dst, Register src1) { msr(dst, src1); }
2495 void TurboAssembler::MulS32(Register dst, const Operand& src1) {
2496 msfi(dst, src1);
2501 lgfr(dst, src1); \
2506 void TurboAssembler::MulHighS32(Register dst, Register src1,
2511 void TurboAssembler::MulHighS32(Register dst, Register src1, Register src2) {
2513 std::swap(src1, src2);
2518 void TurboAssembler::MulHighS32(Register dst, Register src1,
2527 lr(r1, src1); \
2532 void TurboAssembler::MulHighU32(Register dst, Register src1,
2537 void TurboAssembler::MulHighU32(Register dst, Register src1, Register src2) {
2541 void TurboAssembler::MulHighU32(Register dst, Register src1,
2544 USE(src1);
2553 lgfr(dst, src1); \
2558 void TurboAssembler::Mul32WithOverflowIfCCUnequal(Register dst, Register src1,
2566 void TurboAssembler::Mul32WithOverflowIfCCUnequal(Register dst, Register src1,
2569 std::swap(src1, src2);
2574 void TurboAssembler::Mul32WithOverflowIfCCUnequal(Register dst, Register src1,
2583 lgfr(r1, src1); \
2588 void TurboAssembler::DivS32(Register dst, Register src1,
2593 void TurboAssembler::DivS32(Register dst, Register src1, Register src2) {
2601 lr(r0, src1); \
2607 void TurboAssembler::DivU32(Register dst, Register src1,
2612 void TurboAssembler::DivU32(Register dst, Register src1, Register src2) {
2620 lgr(r1, src1); \
2625 void TurboAssembler::DivS64(Register dst, Register src1,
2630 void TurboAssembler::DivS64(Register dst, Register src1, Register src2) {
2638 lgr(r1, src1); \
2644 void TurboAssembler::DivU64(Register dst, Register src1,
2649 void TurboAssembler::DivU64(Register dst, Register src1, Register src2) {
2657 lgfr(r1, src1); \
2662 void TurboAssembler::ModS32(Register dst, Register src1,
2667 void TurboAssembler::ModS32(Register dst, Register src1, Register src2) {
2675 lr(r0, src1); \
2681 void TurboAssembler::ModU32(Register dst, Register src1,
2686 void TurboAssembler::ModU32(Register dst, Register src1, Register src2) {
2694 lgr(r1, src1); \
2699 void TurboAssembler::ModS64(Register dst, Register src1,
2704 void TurboAssembler::ModS64(Register dst, Register src1, Register src2) {
2712 lgr(r1, src1); \
2718 void TurboAssembler::ModU64(Register dst, Register src1,
2723 void TurboAssembler::ModU64(Register dst, Register src1, Register src2) {
2808 // Add 32-bit (Register dst = Register src1 + Register src2)
2809 void TurboAssembler::AddS32(Register dst, Register src1, Register src2) {
2810 if (dst != src1 && dst != src2) {
2814 ark(dst, src1, src2);
2817 lr(dst, src1);
2820 src2 = src1;
2825 // Add Pointer Size (Register dst = Register src1 + Register src2)
2826 void TurboAssembler::AddS64(Register dst, Register src1, Register src2) {
2827 if (dst != src1 && dst != src2) {
2831 agrk(dst, src1, src2);
2834 mov(dst, src1);
2837 src2 = src1;
2877 // Add Logical 32-bit (Register dst = Register src1 + Register src2)
2878 void TurboAssembler::AddU32(Register dst, Register src1, Register src2) {
2879 if (dst != src2 && dst != src1) {
2880 lr(dst, src1);
2883 // dst == src1
2884 DCHECK(dst == src1);
2889 alr(dst, src1);
2903 void TurboAssembler::AddU64(Register dst, Register src1, Register src2) {
2904 if (dst != src2 && dst != src1) {
2906 algrk(dst, src1, src2);
2908 lgr(dst, src1);
2912 // dst == src1
2913 DCHECK(dst == src1);
2918 algr(dst, src1);
2941 // Subtract Logical 32-bit (Register dst = Register src1 - Register src2)
2942 void TurboAssembler::SubU32(Register dst, Register src1, Register src2) {
2943 if (dst != src2 && dst != src1) {
2944 lr(dst, src1);
2947 // dst == src1
2948 DCHECK(dst == src1);
2954 SubU32(dst, src1, r0);
2993 void TurboAssembler::SubS32(Register dst, Register src1, Register src2) {
2996 srk(dst, src1, src2);
2999 if (dst != src1 && dst != src2) lr(dst, src1);
3001 if (dst != src1 && dst == src2) {
3005 ar(dst, src1); // dst = dst + src
3013 void TurboAssembler::SubS64(Register dst, Register src1, Register src2) {
3016 sgrk(dst, src1, src2);
3019 if (dst != src1 && dst != src2) mov(dst, src1);
3021 if (dst != src1 && dst == src2) {
3025 AddS64(dst, src1); // dst = dst + src
3106 // Non-clobbering AND 32-bit - dst = src1 & src1
3107 void TurboAssembler::And(Register dst, Register src1, Register src2) {
3108 if (dst != src1 && dst != src2) {
3112 nrk(dst, src1, src2);
3115 lr(dst, src1);
3118 src2 = src1;
3123 // Non-clobbering AND pointer size - dst = src1 & src1
3124 void TurboAssembler::AndP(Register dst, Register src1, Register src2) {
3125 if (dst != src1 && dst != src2) {
3129 ngrk(dst, src1, src2);
3132 mov(dst, src1);
3135 src2 = src1;
3229 // Non-clobbering OR 32-bit - dst = src1 & src1
3230 void TurboAssembler::Or(Register dst, Register src1, Register src2) {
3231 if (dst != src1 && dst != src2) {
3235 ork(dst, src1, src2);
3238 lr(dst, src1);
3241 src2 = src1;
3246 // Non-clobbering OR pointer size - dst = src1 & src1
3247 void TurboAssembler::OrP(Register dst, Register src1, Register src2) {
3248 if (dst != src1 && dst != src2) {
3252 ogrk(dst, src1, src2);
3255 mov(dst, src1);
3258 src2 = src1;
3317 // Non-clobbering XOR 32-bit - dst = src1 & src1
3318 void TurboAssembler::Xor(Register dst, Register src1, Register src2) {
3319 if (dst != src1 && dst != src2) {
3323 xrk(dst, src1, src2);
3326 lr(dst, src1);
3329 src2 = src1;
3334 // Non-clobbering XOR pointer size - dst = src1 & src1
3335 void TurboAssembler::XorP(Register dst, Register src1, Register src2) {
3336 if (dst != src1 && dst != src2) {
3340 xgrk(dst, src1, src2);
3343 mov(dst, src1);
3346 src2 = src1;
3433 void TurboAssembler::CmpS32(Register src1, Register src2) { cr_z(src1, src2); }
3436 void TurboAssembler::CmpS64(Register src1, Register src2) { cgr(src1, src2); }
3584 void TurboAssembler::CmpSmiLiteral(Register src1, Smi smi, Register scratch) {
3587 cfi(src1, Operand(smi));
3590 cih(src1, Operand(static_cast<intptr_t>(smi.ptr()) >> 32));
3593 cgr(src1, scratch);
3656 void TurboAssembler::StoreMultipleP(Register src1, Register src2,
3660 stmg(src1, src2, mem);
3663 stm(src1, src2, mem);
3666 stmy(src1, src2, mem);
3681 void TurboAssembler::StoreMultipleW(Register src1, Register src2,
3684 stm(src1, src2, mem);
3687 stmy(src1, src2, mem);
5185 void TurboAssembler::F64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
5189 if (src1 != dst) {
5190 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5195 void TurboAssembler::F32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
5199 if (src1 != dst) {
5200 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5205 void TurboAssembler::I64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
5208 if (src1 != dst) {
5209 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5214 void TurboAssembler::I32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
5217 if (src1 != dst) {
5218 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5223 void TurboAssembler::I16x8ReplaceLane(Simd128Register dst, Simd128Register src1,
5226 if (src1 != dst) {
5227 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5232 void TurboAssembler::I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
5235 if (src1 != dst) {
5236 vlr(dst, src1, Condition(0), Condition(0), Condition(0));
5253 void TurboAssembler::S128Select(Simd128Register dst, Simd128Register src1,
5255 vsel(dst, src1, src2, mask, Condition(0), Condition(0));
5317 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5319 op(dst, src1, src2, Condition(c1), Condition(c2)); \
5374 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5376 op(dst, src1, src2, Condition(c1), Condition(c2), Condition(c3)); \
5397 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5401 op(dst, src1, scratch, Condition(0), Condition(0), Condition(c1)); \
5403 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5407 name(dst, src1, scratch1, scratch2); \
5428 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5430 mul_even(scratch, src1, src2, Condition(0), Condition(0), \
5432 mul_odd(dst, src1, src2, Condition(0), Condition(0), Condition(mode)); \
5467 void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
5469 op(dst, src2, src3, src1, Condition(c1), Condition(0)); \
5475 void TurboAssembler::I64x2Mul(Simd128Register dst, Simd128Register src1,
5481 vlgv(scratch_1, src1, MemOperand(r0, i), Condition(3));
5490 void TurboAssembler::F64x2Ne(Simd128Register dst, Simd128Register src1,
5492 vfce(dst, src1, src2, Condition(0), Condition(0), Condition(3));
5496 void TurboAssembler::F64x2Lt(Simd128Register dst, Simd128Register src1,
5498 vfch(dst, src2, src1, Condition(0), Condition(0), Condition(3));
5501 void TurboAssembler::F64x2Le(Simd128Register dst, Simd128Register src1,
5503 vfche(dst, src2, src1, Condition(0), Condition(0), Condition(3));
5506 void TurboAssembler::F32x4Ne(Simd128Register dst, Simd128Register src1,
5508 vfce(dst, src1, src2, Condition(0), Condition(0), Condition(2));
5512 void TurboAssembler::F32x4Lt(Simd128Register dst, Simd128Register src1,
5514 vfch(dst, src2, src1, Condition(0), Condition(0), Condition(2));
5517 void TurboAssembler::F32x4Le(Simd128Register dst, Simd128Register src1,
5519 vfche(dst, src2, src1, Condition(0), Condition(0), Condition(2));
5522 void TurboAssembler::I64x2Ne(Simd128Register dst, Simd128Register src1,
5524 vceq(dst, src1, src2, Condition(0), Condition(3));
5528 void TurboAssembler::I64x2GeS(Simd128Register dst, Simd128Register src1,
5531 vch(dst, src2, src1, Condition(0), Condition(3));
5535 void TurboAssembler::I32x4Ne(Simd128Register dst, Simd128Register src1,
5537 vceq(dst, src1, src2, Condition(0), Condition(2));
5541 void TurboAssembler::I32x4GeS(Simd128Register dst, Simd128Register src1,
5544 vch(dst, src2, src1, Condition(0), Condition(2));
5548 void TurboAssembler::I32x4GeU(Simd128Register dst, Simd128Register src1,
5550 vceq(scratch, src1, src2, Condition(0), Condition(2));
5551 vchl(dst, src1, src2, Condition(0), Condition(2));
5555 void TurboAssembler::I16x8Ne(Simd128Register dst, Simd128Register src1,
5557 vceq(dst, src1, src2, Condition(0), Condition(1));
5561 void TurboAssembler::I16x8GeS(Simd128Register dst, Simd128Register src1,
5564 vch(dst, src2, src1, Condition(0), Condition(1));
5568 void TurboAssembler::I16x8GeU(Simd128Register dst, Simd128Register src1,
5570 vceq(scratch, src1, src2, Condition(0), Condition(1));
5571 vchl(dst, src1, src2, Condition(0), Condition(1));
5575 void TurboAssembler::I8x16Ne(Simd128Register dst, Simd128Register src1,
5577 vceq(dst, src1, src2, Condition(0), Condition(0));
5581 void TurboAssembler::I8x16GeS(Simd128Register dst, Simd128Register src1,
5584 vch(dst, src2, src1, Condition(0), Condition(0));
5588 void TurboAssembler::I8x16GeU(Simd128Register dst, Simd128Register src1,
5590 vceq(scratch, src1, src2, Condition(0), Condition(0));
5591 vchl(dst, src1, src2, Condition(0), Condition(0));
5716 Simd128Register src1,
5718 vpks(dst, src2, src1, Condition(0), Condition(2));
5722 Simd128Register src1,
5724 vpks(dst, src2, src1, Condition(0), Condition(1));
5727 #define VECTOR_PACK_UNSIGNED(dst, src1, src2, scratch, mode) \
5730 vmx(scratch, src1, kDoubleRegZero, Condition(0), Condition(0), \
5734 Simd128Register src1,
5738 VECTOR_PACK_UNSIGNED(dst, src1, src2, scratch, 2)
5743 Simd128Register src1,
5747 VECTOR_PACK_UNSIGNED(dst, src1, src2, scratch, 1)
5752 #define BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, op, extract_high, \
5755 DCHECK(dst != src1 && dst != src2); \
5756 extract_high(scratch1, src1, Condition(0), Condition(0), Condition(mode)); \
5760 extract_low(scratch1, src1, Condition(0), Condition(0), Condition(mode)); \
5764 void TurboAssembler::I16x8AddSatS(Simd128Register dst, Simd128Register src1,
5768 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuph, vupl, 1)
5772 void TurboAssembler::I16x8SubSatS(Simd128Register dst, Simd128Register src1,
5776 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuph, vupl, 1)
5780 void TurboAssembler::I16x8AddSatU(Simd128Register dst, Simd128Register src1,
5784 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuplh, vupll, 1)
5788 void TurboAssembler::I16x8SubSatU(Simd128Register dst, Simd128Register src1,
5792 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuplh, vupll, 1)
5802 void TurboAssembler::I8x16AddSatS(Simd128Register dst, Simd128Register src1,
5806 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuph, vupl, 0)
5810 void TurboAssembler::I8x16SubSatS(Simd128Register dst, Simd128Register src1,
5814 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuph, vupl, 0)
5818 void TurboAssembler::I8x16AddSatU(Simd128Register dst, Simd128Register src1,
5822 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuplh, vupll, 0)
5826 void TurboAssembler::I8x16SubSatU(Simd128Register dst, Simd128Register src1,
5830 BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuplh, vupll, 0)
5942 void TurboAssembler::I8x16Swizzle(Simd128Register dst, Simd128Register src1,
5946 DCHECK(!AreAliased(src1, src2, scratch3, scratch4));
5952 vlgv(scratch1, src1, MemOperand(r0, 0), Condition(3));
5953 vlgv(scratch2, src1, MemOperand(r0, 1), Condition(3));
5962 void TurboAssembler::I8x16Shuffle(Simd128Register dst, Simd128Register src1,
5969 vperm(dst, src1, src2, scratch3, Condition(0), Condition(0));
5972 void TurboAssembler::I32x4DotI16x8S(Simd128Register dst, Simd128Register src1,
5975 vme(scratch, src1, src2, Condition(0), Condition(0), Condition(1));
5976 vmo(dst, src1, src2, Condition(0), Condition(0), Condition(1));
5980 #define Q15_MUL_ROAUND(accumulator, src1, src2, const_val, scratch, unpack) \
5981 unpack(scratch, src1, Condition(0), Condition(0), Condition(1)); \
5990 void TurboAssembler::I16x8Q15MulRSatS(Simd128Register dst, Simd128Register src1,
5995 DCHECK(!AreAliased(src1, src2, scratch1, scratch2, scratch3));
5997 Q15_MUL_ROAUND(scratch2, src1, src2, scratch1, scratch3, vupl)
5998 Q15_MUL_ROAUND(dst, src1, src2, scratch1, scratch3, vuph)