Lines Matching defs:src
10 #include "src/base/bits.h"
11 #include "src/base/division-by-constant.h"
12 #include "src/codegen/callable.h"
13 #include "src/codegen/code-factory.h"
14 #include "src/codegen/external-reference-table.h"
15 #include "src/codegen/interface-descriptors-inl.h"
16 #include "src/codegen/macro-assembler.h"
17 #include "src/codegen/register-configuration.h"
18 #include "src/debug/debug.h"
19 #include "src/deoptimizer/deoptimizer.h"
20 #include "src/execution/frames-inl.h"
21 #include "src/heap/memory-chunk.h"
22 #include "src/init/bootstrapper.h"
23 #include "src/logging/counters.h"
24 #include "src/objects/smi.h"
25 #include "src/runtime/runtime.h"
26 #include "src/snapshot/snapshot.h"
29 #include "src/wasm/wasm-code-manager.h"
35 #include "src/codegen/s390/macro-assembler-s390.h"
250 void TurboAssembler::CeilF32(DoubleRegister dst, DoubleRegister src) {
251 fiebra(ROUND_TOWARD_POS_INF, dst, src);
254 void TurboAssembler::CeilF64(DoubleRegister dst, DoubleRegister src) {
255 fidbra(ROUND_TOWARD_POS_INF, dst, src);
258 void TurboAssembler::FloorF32(DoubleRegister dst, DoubleRegister src) {
259 fiebra(ROUND_TOWARD_NEG_INF, dst, src);
262 void TurboAssembler::FloorF64(DoubleRegister dst, DoubleRegister src) {
263 fidbra(ROUND_TOWARD_NEG_INF, dst, src);
266 void TurboAssembler::TruncF32(DoubleRegister dst, DoubleRegister src) {
267 fiebra(ROUND_TOWARD_0, dst, src);
270 void TurboAssembler::TruncF64(DoubleRegister dst, DoubleRegister src) {
271 fidbra(ROUND_TOWARD_0, dst, src);
274 void TurboAssembler::NearestIntF32(DoubleRegister dst, DoubleRegister src) {
275 fiebra(ROUND_TO_NEAREST_TO_EVEN, dst, src);
278 void TurboAssembler::NearestIntF64(DoubleRegister dst, DoubleRegister src) {
279 fidbra(ROUND_TO_NEAREST_TO_EVEN, dst, src);
539 void TurboAssembler::Move(Register dst, Register src, Condition cond) {
540 if (dst != src) {
542 mov(dst, src);
544 LoadOnConditionP(cond, dst, src);
549 void TurboAssembler::Move(DoubleRegister dst, DoubleRegister src) {
550 if (dst != src) {
551 ldr(dst, src);
555 void TurboAssembler::Move(Register dst, const MemOperand& src) {
556 LoadU64(dst, src);
580 void TurboAssembler::RotateInsertSelectBits(Register dst, Register src,
587 risbg(dst, src, startBit,
590 risbg(dst, src, startBit, endBit, shiftAmt);
806 void TurboAssembler::SmiUntag(Register dst, const MemOperand& src) {
808 LoadS32(dst, src);
810 LoadU64(dst, src);
815 void TurboAssembler::SmiUntagField(Register dst, const MemOperand& src) {
816 SmiUntag(dst, src);
832 Register src) {
834 llgfr(destination, src);
1120 const DoubleRegister src) {
1122 if (dst != src) ldr(dst, src);
1127 void TurboAssembler::ConvertIntToDouble(DoubleRegister dst, Register src) {
1128 cdfbr(dst, src);
1132 Register src) {
1134 cdlfbr(Condition(5), Condition(0), dst, src);
1136 // zero-extend src
1137 llgfr(src, src);
1139 cdgbr(dst, src);
1143 void TurboAssembler::ConvertIntToFloat(DoubleRegister dst, Register src) {
1144 cefbra(Condition(4), dst, src);
1148 Register src) {
1149 celfbr(Condition(4), Condition(0), dst, src);
1153 Register src) {
1154 cegbr(double_dst, src);
1158 Register src) {
1159 cdgbr(double_dst, src);
1163 Register src) {
1164 celgbr(Condition(0), Condition(0), double_dst, src);
1168 Register src) {
1169 cdlgbr(Condition(0), Condition(0), double_dst, src);
1362 void TurboAssembler::MovDoubleToInt64(Register dst, DoubleRegister src) {
1363 lgdr(dst, src);
1366 void TurboAssembler::MovInt64ToDouble(DoubleRegister dst, Register src) {
1367 ldgr(dst, src);
1672 Register num = r7, src = r8, dest = ip; // r7 and r8 are context and root.
1673 mov(src, sp);
1682 LoadU64(r0, MemOperand(src));
1683 lay(src, MemOperand(src, kSystemPointerSize));
2274 void TurboAssembler::MovToFloatParameter(DoubleRegister src) { Move(d0, src); }
2276 void TurboAssembler::MovToFloatResult(DoubleRegister src) { Move(d0, src); }
2436 void TurboAssembler::mov(Register dst, Register src) { lgr(dst, src); }
2438 void TurboAssembler::mov(Register dst, const Operand& src) {
2441 if (src.is_heap_object_request()) {
2442 RequestHeapObject(src.heap_object_request());
2444 value = src.immediate();
2447 if (src.rmode() != RelocInfo::NO_INFO) {
2449 RecordRelocInfo(src.rmode(), value);
2455 if (src.rmode() == RelocInfo::NO_INFO) {
2733 void TurboAssembler::MulS64(Register dst, Register src) { msgr(dst, src); }
2770 void TurboAssembler::AddS32(Register dst, Register src, int32_t opnd) {
2771 AddS32(dst, src, Operand(opnd));
2774 // Add 32-bit (Register dst = Register src + Immediate opnd)
2775 void TurboAssembler::AddS32(Register dst, Register src, const Operand& opnd) {
2776 if (dst != src) {
2778 ahik(dst, src, opnd);
2781 lr(dst, src);
2786 void TurboAssembler::AddS64(Register dst, Register src, int32_t opnd) {
2787 AddS64(dst, src, Operand(opnd));
2790 // Add Pointer Size (Register dst = Register src + Immediate opnd)
2791 void TurboAssembler::AddS64(Register dst, Register src, const Operand& opnd) {
2792 if (dst != src) {
2794 aghik(dst, src, opnd);
2797 mov(dst, src);
2802 // Add 32-bit (Register dst = Register dst + Register src)
2803 void TurboAssembler::AddS32(Register dst, Register src) { ar(dst, src); }
2805 // Add Pointer Size (Register dst = Register dst + Register src)
2806 void TurboAssembler::AddS64(Register dst, Register src) { agr(dst, src); }
2968 void TurboAssembler::SubS32(Register dst, Register src, int32_t imm) {
2969 SubS32(dst, src, Operand(imm));
2972 // Subtract 32-bit (Register dst = Register src - Immediate opnd)
2973 void TurboAssembler::SubS32(Register dst, Register src, const Operand& imm) {
2974 AddS32(dst, src, Operand(-(imm.immediate())));
2977 void TurboAssembler::SubS64(Register dst, Register src, int32_t imm) {
2978 SubS64(dst, src, Operand(imm));
2981 // Subtract Pointer Sized (Register dst = Register src - Immediate opnd)
2982 void TurboAssembler::SubS64(Register dst, Register src, const Operand& imm) {
2983 AddS64(dst, src, Operand(-(imm.immediate())));
2986 // Subtract 32-bit (Register dst = Register dst - Register src)
2987 void TurboAssembler::SubS32(Register dst, Register src) { sr(dst, src); }
2989 // Subtract Pointer Size (Register dst = Register dst - Register src)
2990 void TurboAssembler::SubS64(Register dst, Register src) { sgr(dst, src); }
3000 // In scenario where we have dst = src - dst, we need to swap and negate
3005 ar(dst, src1); // dst = dst + src
3020 // In scenario where we have dst = src - dst, we need to swap and negate
3025 AddS64(dst, src1); // dst = dst + src
3050 void TurboAssembler::MovIntToFloat(DoubleRegister dst, Register src) {
3051 sllg(r0, src, Operand(32));
3055 void TurboAssembler::MovFloatToInt(Register dst, DoubleRegister src) {
3056 lgdr(dst, src);
3061 void TurboAssembler::LoadAndSub32(Register dst, Register src,
3063 lcr(dst, src);
3067 void TurboAssembler::LoadAndSub64(Register dst, Register src,
3069 lcgr(dst, src);
3100 // AND 32-bit - dst = dst & src
3101 void TurboAssembler::And(Register dst, Register src) { nr(dst, src); }
3103 // AND Pointer Size - dst = dst & src
3104 void TurboAssembler::AndP(Register dst, Register src) { ngr(dst, src); }
3176 // AND 32-bit - dst = src & imm
3177 void TurboAssembler::And(Register dst, Register src, const Operand& opnd) {
3178 if (dst != src) lr(dst, src);
3182 // AND Pointer Size - dst = src & imm
3183 void TurboAssembler::AndP(Register dst, Register src, const Operand& opnd) {
3205 RotateInsertSelectBits(dst, src, Operand(startBit), Operand(endBit),
3212 RotateInsertSelectBits(dst, src, Operand::Zero(), Operand(endBit),
3219 if (dst != src && (0 != value)) mov(dst, src);
3223 // OR 32-bit - dst = dst & src
3224 void TurboAssembler::Or(Register dst, Register src) { or_z(dst, src); }
3226 // OR Pointer Size - dst = dst & src
3227 void TurboAssembler::OrP(Register dst, Register src) { ogr(dst, src); }
3299 // OR 32-bit - dst = src & imm
3300 void TurboAssembler::Or(Register dst, Register src, const Operand& opnd) {
3301 if (dst != src) lr(dst, src);
3305 // OR Pointer Size - dst = src & imm
3306 void TurboAssembler::OrP(Register dst, Register src, const Operand& opnd) {
3307 if (dst != src) mov(dst, src);
3311 // XOR 32-bit - dst = dst & src
3312 void TurboAssembler::Xor(Register dst, Register src) { xr(dst, src); }
3314 // XOR Pointer Size - dst = dst & src
3315 void TurboAssembler::XorP(Register dst, Register src) { xgr(dst, src); }
3384 // XOR 32-bit - dst = src & imm
3385 void TurboAssembler::Xor(Register dst, Register src, const Operand& opnd) {
3386 if (dst != src) lr(dst, src);
3390 // XOR Pointer Size - dst = src & imm
3391 void TurboAssembler::XorP(Register dst, Register src, const Operand& opnd) {
3392 if (dst != src) mov(dst, src);
3396 void TurboAssembler::Not32(Register dst, Register src) {
3397 if (src != no_reg && src != dst) lr(dst, src);
3401 void TurboAssembler::Not64(Register dst, Register src) {
3402 if (src != no_reg && src != dst) lgr(dst, src);
3407 void TurboAssembler::NotP(Register dst, Register src) {
3409 Not64(dst, src);
3411 Not32(dst, src);
3503 void TurboAssembler::CmpU32(Register dst, Register src) { clr(dst, src); }
3506 void TurboAssembler::CmpU64(Register dst, Register src) {
3508 clgr(dst, src);
3510 CmpU32(dst, src);
3602 MemOperand src = mem;
3607 src = MemOperand(mem.rb(), scratch);
3609 lg(dst, src);
3613 void TurboAssembler::StoreU64(Register src, const MemOperand& mem,
3619 stg(src, MemOperand(mem.rb(), scratch));
3621 stg(src, mem);
3692 void TurboAssembler::LoadS32(Register dst, Register src) {
3694 lgfr(dst, src);
3696 if (dst != src) lr(dst, src);
3727 void TurboAssembler::LoadU32(Register dst, Register src) {
3729 llgfr(dst, src);
3731 if (dst != src) lr(dst, src);
3787 void TurboAssembler::LoadU16(Register dst, Register src) {
3789 llghr(dst, src);
3791 llhr(dst, src);
3804 void TurboAssembler::LoadS8(Register dst, Register src) {
3806 lgbr(dst, src);
3808 lbr(dst, src);
3821 void TurboAssembler::LoadU8(Register dst, Register src) {
3823 llgcr(dst, src);
3825 llcr(dst, src);
3884 void TurboAssembler::StoreU64LE(Register src, const MemOperand& mem,
3890 strvg(src, MemOperand(mem.rb(), scratch));
3892 strvg(src, mem);
3896 void TurboAssembler::StoreU32LE(Register src, const MemOperand& mem,
3902 strv(src, MemOperand(mem.rb(), scratch));
3904 strv(src, mem);
3908 void TurboAssembler::StoreU16LE(Register src, const MemOperand& mem,
3914 strvh(src, MemOperand(mem.rb(), scratch));
3916 strvh(src, mem);
3920 void TurboAssembler::StoreF64LE(DoubleRegister src, const MemOperand& opnd,
3923 lgdr(scratch, src);
3927 void TurboAssembler::StoreF32LE(DoubleRegister src, const MemOperand& opnd,
3930 lgdr(scratch, src);
3935 void TurboAssembler::StoreV128LE(Simd128Register src, const MemOperand& mem,
3940 vstbr(src, mem, Condition(4));
3942 vlgv(scratch1, src, MemOperand(r0, 1), Condition(3));
3943 vlgv(scratch2, src, MemOperand(r0, 0), Condition(3));
3992 void TurboAssembler::StoreU64LE(Register src, const MemOperand& mem,
3994 StoreU64(src, mem, scratch);
3997 void TurboAssembler::StoreU32LE(Register src, const MemOperand& mem,
3999 StoreU32(src, mem, scratch);
4002 void TurboAssembler::StoreU16LE(Register src, const MemOperand& mem,
4004 StoreU16(src, mem, scratch);
4007 void TurboAssembler::StoreF64LE(DoubleRegister src, const MemOperand& opnd,
4009 StoreF64(src, opnd);
4012 void TurboAssembler::StoreF32LE(DoubleRegister src, const MemOperand& opnd,
4014 StoreF32(src, opnd);
4017 void TurboAssembler::StoreV128LE(Simd128Register src, const MemOperand& mem,
4019 StoreV128(src, mem, scratch1);
4025 void TurboAssembler::LoadAndTest32(Register dst, Register src) {
4026 ltr(dst, src);
4030 void TurboAssembler::LoadAndTestP(Register dst, Register src) {
4032 ltgr(dst, src);
4034 ltr(dst, src);
4054 Register src) {
4056 locgr(cond, dst, src);
4058 locr(cond, dst, src);
4104 void TurboAssembler::StoreF32(DoubleRegister src, const MemOperand& mem) {
4106 ste(src, mem);
4108 stey(src, mem);
4112 void TurboAssembler::StoreV128(Simd128Register src, const MemOperand& mem,
4116 vst(src, mem, Condition(0));
4120 vst(src, MemOperand(scratch), Condition(0));
4322 void TurboAssembler::StoreU32(Register src, const MemOperand& mem,
4345 st(src, mem);
4347 sty(src, mem);
4349 StoreU32(src, MemOperand(base, scratch));
4353 void TurboAssembler::LoadS16(Register dst, Register src) {
4355 lghr(dst, src);
4357 lhr(dst, src);
4391 void TurboAssembler::StoreU16(Register src, const MemOperand& mem,
4397 sth(src, mem);
4399 sthy(src, mem);
4403 sth(src, MemOperand(base, scratch));
4409 void TurboAssembler::StoreU8(Register src, const MemOperand& mem,
4415 stc(src, mem);
4417 stcy(src, mem);
4421 stc(src, MemOperand(base, scratch));
4426 void TurboAssembler::ShiftLeftU32(Register dst, Register src,
4428 ShiftLeftU32(dst, src, r0, val);
4432 void TurboAssembler::ShiftLeftU32(Register dst, Register src, Register val,
4434 if (dst == src) {
4437 sllk(dst, src, val, val2);
4440 lr(dst, src);
4446 void TurboAssembler::ShiftLeftU64(Register dst, Register src,
4448 ShiftLeftU64(dst, src, r0, val);
4452 void TurboAssembler::ShiftLeftU64(Register dst, Register src, Register val,
4454 sllg(dst, src, val, val2);
4458 void TurboAssembler::ShiftRightU32(Register dst, Register src,
4460 ShiftRightU32(dst, src, r0, val);
4464 void TurboAssembler::ShiftRightU32(Register dst, Register src, Register val,
4466 if (dst == src) {
4469 srlk(dst, src, val, val2);
4472 lr(dst, src);
4477 void TurboAssembler::ShiftRightU64(Register dst, Register src, Register val,
4479 srlg(dst, src, val, val2);
4483 void TurboAssembler::ShiftRightU64(Register dst, Register src,
4485 ShiftRightU64(dst, src, r0, val);
4489 void TurboAssembler::ShiftRightS32(Register dst, Register src,
4491 ShiftRightS32(dst, src, r0, val);
4495 void TurboAssembler::ShiftRightS32(Register dst, Register src, Register val,
4497 if (dst == src) {
4500 srak(dst, src, val, val2);
4503 lr(dst, src);
4509 void TurboAssembler::ShiftRightS64(Register dst, Register src,
4511 ShiftRightS64(dst, src, r0, val);
4515 void TurboAssembler::ShiftRightS64(Register dst, Register src, Register val,
4517 srag(dst, src, val, val2);
4521 void TurboAssembler::ClearRightImm(Register dst, Register src,
4528 RotateInsertSelectBits(dst, src, Operand::Zero(), Operand(endBit),
4536 if (dst != src) mov(dst, src);
4548 void TurboAssembler::Popcnt32(Register dst, Register src) {
4549 DCHECK(src != r0);
4552 popcnt(dst, src);
4561 void TurboAssembler::Popcnt64(Register dst, Register src) {
4562 DCHECK(src != r0);
4565 popcnt(dst, src);
4576 void TurboAssembler::SwapP(Register src, Register dst, Register scratch) {
4577 if (src == dst) return;
4578 DCHECK(!AreAliased(src, dst, scratch));
4579 mov(scratch, src);
4580 mov(src, dst);
4584 void TurboAssembler::SwapP(Register src, MemOperand dst, Register scratch) {
4585 if (dst.rx() != r0) DCHECK(!AreAliased(src, dst.rx(), scratch));
4586 if (dst.rb() != r0) DCHECK(!AreAliased(src, dst.rb(), scratch));
4587 DCHECK(!AreAliased(src, scratch));
4588 mov(scratch, src);
4589 LoadU64(src, dst);
4593 void TurboAssembler::SwapP(MemOperand src, MemOperand dst, Register scratch_0,
4595 if (src.rx() != r0) DCHECK(!AreAliased(src.rx(), scratch_0, scratch_1));
4596 if (src.rb() != r0) DCHECK(!AreAliased(src.rb(), scratch_0, scratch_1));
4600 LoadU64(scratch_0, src);
4603 StoreU64(scratch_1, src);
4606 void TurboAssembler::SwapFloat32(DoubleRegister src, DoubleRegister dst,
4608 if (src == dst) return;
4609 DCHECK(!AreAliased(src, dst, scratch));
4610 ldr(scratch, src);
4611 ldr(src, dst);
4615 void TurboAssembler::SwapFloat32(DoubleRegister src, MemOperand dst,
4617 DCHECK(!AreAliased(src, scratch));
4618 ldr(scratch, src);
4619 LoadF32(src, dst);
4623 void TurboAssembler::SwapFloat32(MemOperand src, MemOperand dst,
4628 LoadF32(scratch, src);
4631 StoreF32(d0, src);
4637 void TurboAssembler::SwapDouble(DoubleRegister src, DoubleRegister dst,
4639 if (src == dst) return;
4640 DCHECK(!AreAliased(src, dst, scratch));
4641 ldr(scratch, src);
4642 ldr(src, dst);
4646 void TurboAssembler::SwapDouble(DoubleRegister src, MemOperand dst,
4648 DCHECK(!AreAliased(src, scratch));
4649 ldr(scratch, src);
4650 LoadF64(src, dst);
4654 void TurboAssembler::SwapDouble(MemOperand src, MemOperand dst,
4659 LoadF64(scratch, src);
4662 StoreF64(d0, src);
4668 void TurboAssembler::SwapSimd128(Simd128Register src, Simd128Register dst,
4670 if (src == dst) return;
4671 vlr(scratch, src, Condition(0), Condition(0), Condition(0));
4672 vlr(src, dst, Condition(0), Condition(0), Condition(0));
4676 void TurboAssembler::SwapSimd128(Simd128Register src, MemOperand dst,
4678 DCHECK(!AreAliased(src, scratch));
4679 vlr(scratch, src, Condition(0), Condition(0), Condition(0));
4680 LoadV128(src, dst, ip);
4684 void TurboAssembler::SwapSimd128(MemOperand src, MemOperand dst,
4689 LoadV128(scratch, src, ip);
4692 StoreV128(d0, src, ip);
4846 void TurboAssembler::CountLeadingZerosU32(Register dst, Register src,
4848 llgfr(dst, src);
4854 void TurboAssembler::CountLeadingZerosU64(Register dst, Register src,
4857 src); // will modify a register pair scratch and scratch + 1
4861 void TurboAssembler::CountTrailingZerosU32(Register dst, Register src,
4866 DCHECK(!AreAliased(src, scratch0, scratch1));
4869 // Check if src is all zeros.
4870 ltr(scratch1, src);
4882 void TurboAssembler::CountTrailingZerosU64(Register dst, Register src,
4887 DCHECK(!AreAliased(src, scratch0, scratch1));
4890 // Check if src is all zeros.
4891 ltgr(scratch1, src);
5115 void TurboAssembler::F64x2Splat(Simd128Register dst, Simd128Register src) {
5116 vrep(dst, src, Operand(0), Condition(3));
5119 void TurboAssembler::F32x4Splat(Simd128Register dst, Simd128Register src) {
5120 vrep(dst, src, Operand(0), Condition(2));
5123 void TurboAssembler::I64x2Splat(Simd128Register dst, Register src) {
5124 vlvg(dst, src, MemOperand(r0, 0), Condition(3));
5128 void TurboAssembler::I32x4Splat(Simd128Register dst, Register src) {
5129 vlvg(dst, src, MemOperand(r0, 0), Condition(2));
5133 void TurboAssembler::I16x8Splat(Simd128Register dst, Register src) {
5134 vlvg(dst, src, MemOperand(r0, 0), Condition(1));
5138 void TurboAssembler::I8x16Splat(Simd128Register dst, Register src) {
5139 vlvg(dst, src, MemOperand(r0, 0), Condition(0));
5143 void TurboAssembler::F64x2ExtractLane(DoubleRegister dst, Simd128Register src,
5145 vrep(dst, src, Operand(1 - imm_lane_idx), Condition(3));
5148 void TurboAssembler::F32x4ExtractLane(DoubleRegister dst, Simd128Register src,
5150 vrep(dst, src, Operand(3 - imm_lane_idx), Condition(2));
5153 void TurboAssembler::I64x2ExtractLane(Register dst, Simd128Register src,
5155 vlgv(dst, src, MemOperand(r0, 1 - imm_lane_idx), Condition(3));
5158 void TurboAssembler::I32x4ExtractLane(Register dst, Simd128Register src,
5160 vlgv(dst, src, MemOperand(r0, 3 - imm_lane_idx), Condition(2));
5163 void TurboAssembler::I16x8ExtractLaneU(Register dst, Simd128Register src,
5165 vlgv(dst, src, MemOperand(r0, 7 - imm_lane_idx), Condition(1));
5168 void TurboAssembler::I16x8ExtractLaneS(Register dst, Simd128Register src,
5170 vlgv(scratch, src, MemOperand(r0, 7 - imm_lane_idx), Condition(1));
5174 void TurboAssembler::I8x16ExtractLaneU(Register dst, Simd128Register src,
5176 vlgv(dst, src, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
5179 void TurboAssembler::I8x16ExtractLaneS(Register dst, Simd128Register src,
5181 vlgv(scratch, src, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
5241 void TurboAssembler::S128Not(Simd128Register dst, Simd128Register src) {
5242 vno(dst, src, src, Condition(0), Condition(0), Condition(0));
5245 void TurboAssembler::S128Zero(Simd128Register dst, Simd128Register src) {
5246 vx(dst, src, src, Condition(0), Condition(0), Condition(0));
5249 void TurboAssembler::S128AllOnes(Simd128Register dst, Simd128Register src) {
5250 vceq(dst, src, src, Condition(0), Condition(3));
5296 void TurboAssembler::name(Simd128Register dst, Simd128Register src) { \
5297 op(dst, src, Condition(c1), Condition(c2), Condition(c3)); \
5446 void TurboAssembler::name(Register dst, Simd128Register src, \
5452 vceq(scratch2, src, scratch2, Condition(0), Condition(mode)); \
5595 void TurboAssembler::I64x2BitMask(Register dst, Simd128Register src,
5599 vbperm(scratch2, src, scratch2, Condition(0), Condition(0), Condition(0));
5603 void TurboAssembler::I32x4BitMask(Register dst, Simd128Register src,
5607 vbperm(scratch2, src, scratch2, Condition(0), Condition(0), Condition(0));
5611 void TurboAssembler::I16x8BitMask(Register dst, Simd128Register src,
5615 vbperm(scratch2, src, scratch2, Condition(0), Condition(0), Condition(0));
5620 Simd128Register src) {
5621 vupl(dst, src, Condition(0), Condition(0), Condition(2));
5626 Simd128Register src) {
5627 vupll(dst, src, Condition(0), Condition(0), Condition(2));
5631 void TurboAssembler::I8x16BitMask(Register dst, Simd128Register src,
5637 vbperm(scratch3, src, scratch3, Condition(0), Condition(0), Condition(0));
5641 void TurboAssembler::V128AnyTrue(Register dst, Simd128Register src,
5645 vtm(src, src, Condition(0), Condition(0), Condition(0));
5649 #define CONVERT_FLOAT_TO_INT32(convert, dst, src, scratch1, scratch2) \
5651 vlgv(scratch2, src, MemOperand(r0, index), Condition(2)); \
5657 Simd128Register src,
5661 vfce(scratch1, src, src, Condition(0), Condition(0), Condition(2));
5662 vn(dst, src, scratch1, Condition(0), Condition(0), Condition(0));
5671 Simd128Register src,
5677 vclgd(dst, src, Condition(5), Condition(0), Condition(2));
5679 CONVERT_FLOAT_TO_INT32(ConvertFloat32ToUnsignedInt32, dst, src, scratch1,
5685 #define CONVERT_INT32_TO_FLOAT(convert, dst, src, scratch1, scratch2) \
5687 vlgv(scratch2, src, MemOperand(r0, index), Condition(2)); \
5693 Simd128Register src,
5697 vcdg(dst, src, Condition(4), Condition(0), Condition(2));
5699 CONVERT_INT32_TO_FLOAT(ConvertIntToFloat, dst, src, scratch1, scratch2)
5703 Simd128Register src,
5707 vcdlg(dst, src, Condition(4), Condition(0), Condition(2));
5709 CONVERT_INT32_TO_FLOAT(ConvertUnsignedIntToFloat, dst, src, scratch1,
5842 Simd128Register src,
5848 vlgv(scratch2, src, MemOperand(scratch2, index + 2), Condition(2));
5858 Simd128Register src,
5864 vlgv(scratch2, src, MemOperand(r0, index), Condition(3));
5875 #define EXT_ADD_PAIRWISE(dst, src, scratch1, scratch2, lane_size, mul_even, \
5877 CHECK_NE(src, scratch2); \
5879 mul_even(scratch1, src, scratch2, Condition(0), Condition(0), \
5881 mul_odd(scratch2, src, scratch2, Condition(0), Condition(0), \
5886 Simd128Register src,
5889 EXT_ADD_PAIRWISE(dst, src, scratch1, scratch2, 1, vme, vmo)
5893 Simd128Register src,
5897 vsum(dst, src, scratch, Condition(0), Condition(0), Condition(1));
5901 Simd128Register src,
5904 EXT_ADD_PAIRWISE(dst, src, scratch1, scratch2, 0, vme, vmo)
5908 Simd128Register src,
5911 EXT_ADD_PAIRWISE(dst, src, scratch1, scratch2, 0, vmle, vmlo)
5916 Simd128Register src,
5919 vlr(scratch, src, Condition(0), Condition(0), Condition(0));
5921 vn(scratch, src, scratch, Condition(0), Condition(0), Condition(0));
5928 Simd128Register src,
5930 vclgd(scratch, src, Condition(5), Condition(0), Condition(3));
6107 void TurboAssembler::StoreLane##name##LE(Simd128Register src, \
6111 vector_instr(src, mem, Condition(lane)); \
6114 vlgv(scratch, src, MemOperand(r0, lane), Condition(condition)); \