Lines Matching defs:result
1840 Register result,
1843 if (result.is_valid()) {
1855 // set result to 1 if normal, otherwise set result to 0 for abnormal
1856 frflags(result);
1857 andi(result, result, exception_flags);
1858 seqz(result, result); // result <-- 1 (normal), result <-- 0 (abnormal)
1884 void TurboAssembler::Trunc_uw_d(Register rd, FPURegister fs, Register result) {
1886 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1891 void TurboAssembler::Trunc_w_d(Register rd, FPURegister fs, Register result) {
1893 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1898 void TurboAssembler::Trunc_uw_s(Register rd, FPURegister fs, Register result) {
1900 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1905 void TurboAssembler::Trunc_w_s(Register rd, FPURegister fs, Register result) {
1907 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1912 void TurboAssembler::Trunc_ul_d(Register rd, FPURegister fs, Register result) {
1914 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1919 void TurboAssembler::Trunc_l_d(Register rd, FPURegister fs, Register result) {
1921 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1926 void TurboAssembler::Trunc_ul_s(Register rd, FPURegister fs, Register result) {
1928 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1933 void TurboAssembler::Trunc_l_s(Register rd, FPURegister fs, Register result) {
1935 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1940 void TurboAssembler::Round_w_s(Register rd, FPURegister fs, Register result) {
1942 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1947 void TurboAssembler::Round_w_d(Register rd, FPURegister fs, Register result) {
1949 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1954 void TurboAssembler::Ceil_w_s(Register rd, FPURegister fs, Register result) {
1956 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1961 void TurboAssembler::Ceil_w_d(Register rd, FPURegister fs, Register result) {
1963 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1968 void TurboAssembler::Floor_w_s(Register rd, FPURegister fs, Register result) {
1970 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1975 void TurboAssembler::Floor_w_d(Register rd, FPURegister fs, Register result) {
1977 rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) {
1984 // rounded result; this differs from behavior of RISCV fcvt instructions (which
2019 // in mantissa, the result is the same as src, so move src to dest (to avoid
2087 // number that rounds to zero. JS semantics requires that the rounded result
2104 // rounded result; this differs from behavior of RISCV fcvt instructions (which
2112 // in mantissa, the result is the same as src, so move src to dest (to avoid
2152 // number that rounds to zero. JS semantics requires that the rounded result
2761 void TurboAssembler::TryInlineTruncateDoubleToI(Register result,
2767 Trunc_w_d(result, double_input, scratch);
2773 Register result,
2778 TryInlineTruncateDoubleToI(result, double_input, &done);
2791 ld(result, sp, 0);
4725 // For RISCV, fmin_s returns the other non-NaN operand as result if only one
4726 // operand is NaN; but for JS, if any operand is NaN, result is Nan. The