Lines Matching refs:imm6
1027 int8_t imm6) {
1028 DCHECK(is_uint3(funct3) && rd.is_valid() && is_int6(imm6));
1029 ShortInstr instr = opcode | ((imm6 & 0x1f) << 2) |
1030 (rd.code() << kRvcRdShift) | ((imm6 & 0x20) << 7) |
1137 Register rs1, int8_t imm6) {
1138 DCHECK(is_uint3(funct3) && is_uint2(funct2) && is_int6(imm6));
1139 ShortInstr instr = opcode | ((imm6 & 0x1f) << 2) | ((imm6 & 0x20) << 7) |
2224 void Assembler::c_addi(Register rd, int8_t imm6) {
2225 DCHECK(rd != zero_reg && imm6 != 0);
2226 GenInstrCI(0b000, C1, rd, imm6);
2229 void Assembler::c_addiw(Register rd, int8_t imm6) {
2231 GenInstrCI(0b001, C1, rd, imm6);
2249 void Assembler::c_li(Register rd, int8_t imm6) {
2251 GenInstrCI(0b010, C1, rd, imm6);
2254 void Assembler::c_lui(Register rd, int8_t imm6) {
2255 DCHECK(rd != zero_reg && rd != sp && imm6 != 0);
2256 GenInstrCI(0b011, C1, rd, imm6);
2453 void Assembler::c_andi(Register rs1, int8_t imm6) {
2454 DCHECK(((rs1.code() & 0b11000) == 0b01000) && is_int6(imm6));
2455 GenInstrCBA(0b100, 0b10, C1, rs1, imm6);