Lines Matching refs:rd
818 Register rd, Register rs1, Register rs2) {
819 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
821 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
828 FPURegister rd, FPURegister rs1, FPURegister rs2) {
829 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
831 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
838 Register rd, FPURegister rs1, Register rs2) {
839 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
841 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
848 FPURegister rd, Register rs1, Register rs2) {
849 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
851 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
858 FPURegister rd, FPURegister rs1, Register rs2) {
859 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
861 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
868 Register rd, FPURegister rs1, FPURegister rs2) {
869 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
871 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
877 void Assembler::GenInstrR4(uint8_t funct2, Opcode opcode, Register rd,
880 DCHECK(is_uint2(funct2) && rd.is_valid() && rs1.is_valid() &&
882 Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) |
888 void Assembler::GenInstrR4(uint8_t funct2, Opcode opcode, FPURegister rd,
891 DCHECK(is_uint2(funct2) && rd.is_valid() && rs1.is_valid() &&
893 Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) |
900 uint8_t funct3, Register rd, Register rs1,
902 DCHECK(is_uint5(funct5) && is_uint3(funct3) && rd.is_valid() &&
904 Instr instr = AMO | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
910 void Assembler::GenInstrRFrm(uint8_t funct7, Opcode opcode, Register rd,
912 DCHECK(rd.is_valid() && rs1.is_valid() && rs2.is_valid() && is_uint3(frm));
913 Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) |
919 void Assembler::GenInstrI(uint8_t funct3, Opcode opcode, Register rd,
921 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
923 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
928 void Assembler::GenInstrI(uint8_t funct3, Opcode opcode, FPURegister rd,
930 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
932 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
938 Register rd, Register rs1, uint8_t shamt) {
939 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
941 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
948 Register rd, Register rs1, uint8_t shamt) {
949 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
951 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
992 void Assembler::GenInstrU(Opcode opcode, Register rd, int32_t imm20) {
993 DCHECK(rd.is_valid() && (is_int20(imm20) || is_uint20(imm20)));
994 Instr instr = opcode | (rd.code() << kRdShift) | (imm20 << kImm20Shift);
998 void Assembler::GenInstrJ(Opcode opcode, Register rd, int32_t imm21) {
999 DCHECK(rd.is_valid() && is_int21(imm21) && ((imm21 & 1) == 0));
1000 Instr instr = opcode | (rd.code() << kRdShift) |
1008 void Assembler::GenInstrCR(uint8_t funct4, Opcode opcode, Register rd,
1010 DCHECK(is_uint4(funct4) && rd.is_valid() && rs2.is_valid());
1012 (rd.code() << kRvcRdShift) | (funct4 << kRvcFunct4Shift);
1016 void Assembler::GenInstrCA(uint8_t funct6, Opcode opcode, Register rd,
1018 DCHECK(is_uint6(funct6) && rd.is_valid() && rs2.is_valid() &&
1021 ((rd.code() & 0x7) << kRvcRs1sShift) |
1026 void Assembler::GenInstrCI(uint8_t funct3, Opcode opcode, Register rd,
1028 DCHECK(is_uint3(funct3) && rd.is_valid() && is_int6(imm6));
1030 (rd.code() << kRvcRdShift) | ((imm6 & 0x20) << 7) |
1035 void Assembler::GenInstrCIU(uint8_t funct3, Opcode opcode, Register rd,
1037 DCHECK(is_uint3(funct3) && rd.is_valid() && is_uint6(uimm6));
1039 (rd.code() << kRvcRdShift) | ((uimm6 & 0x20) << 7) |
1044 void Assembler::GenInstrCIU(uint8_t funct3, Opcode opcode, FPURegister rd,
1046 DCHECK(is_uint3(funct3) && rd.is_valid() && is_uint6(uimm6));
1048 (rd.code() << kRvcRdShift) | ((uimm6 & 0x20) << 7) |
1053 void Assembler::GenInstrCIW(uint8_t funct3, Opcode opcode, Register rd,
1055 DCHECK(is_uint3(funct3) && rd.is_valid() && is_uint8(uimm8));
1057 ((rd.code() & 0x7) << kRvcRs2sShift) |
1078 void Assembler::GenInstrCL(uint8_t funct3, Opcode opcode, Register rd,
1080 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
1083 ((rd.code() & 0x7) << kRvcRs2sShift) |
1089 void Assembler::GenInstrCL(uint8_t funct3, Opcode opcode, FPURegister rd,
1091 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
1094 ((rd.code() & 0x7) << kRvcRs2sShift) |
1166 void Assembler::GenInstrV(uint8_t funct6, Opcode opcode, Register rd,
1170 ((rd.code() & 0x1F) << kRvvVdShift) |
1210 void Assembler::GenInstrV(uint8_t funct6, Register rd, Register rs1,
1213 ((rd.code() & 0x1F) << kRvvVdShift) |
1274 void Assembler::GenInstrV(uint8_t funct6, Opcode opcode, Register rd,
1278 ((rd.code() & 0x1F) << kRvvVdShift) |
1290 void Assembler::GenInstrLoad_ri(uint8_t funct3, Register rd, Register rs1,
1292 GenInstrI(funct3, LOAD, rd, rs1, imm12);
1300 void Assembler::GenInstrALU_ri(uint8_t funct3, Register rd, Register rs1,
1302 GenInstrI(funct3, OP_IMM, rd, rs1, imm12);
1305 void Assembler::GenInstrShift_ri(bool arithshift, uint8_t funct3, Register rd,
1308 GenInstrI(funct3, OP_IMM, rd, rs1, (arithshift << 10) | shamt);
1311 void Assembler::GenInstrALU_rr(uint8_t funct7, uint8_t funct3, Register rd,
1313 GenInstrR(funct7, funct3, OP, rd, rs1, rs2);
1316 void Assembler::GenInstrCSR_ir(uint8_t funct3, Register rd,
1318 GenInstrI(funct3, SYSTEM, rd, rs1, csr);
1321 void Assembler::GenInstrCSR_ii(uint8_t funct3, Register rd,
1323 GenInstrI(funct3, SYSTEM, rd, ToRegister(imm5), csr);
1326 void Assembler::GenInstrShiftW_ri(bool arithshift, uint8_t funct3, Register rd,
1328 GenInstrIShiftW(arithshift, funct3, OP_IMM_32, rd, rs1, shamt);
1331 void Assembler::GenInstrALUW_rr(uint8_t funct7, uint8_t funct3, Register rd,
1333 GenInstrR(funct7, funct3, OP_32, rd, rs1, rs2);
1340 void Assembler::GenInstrLoadFP_ri(uint8_t funct3, FPURegister rd, Register rs1,
1342 GenInstrI(funct3, LOAD_FP, rd, rs1, imm12);
1350 void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd,
1352 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1355 void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd,
1357 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1360 void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd,
1362 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1365 void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd,
1367 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1370 void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd,
1372 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1515 void Assembler::lui(Register rd, int32_t imm20) { GenInstrU(LUI, rd, imm20); }
1517 void Assembler::auipc(Register rd, int32_t imm20) {
1518 GenInstrU(AUIPC, rd, imm20);
1523 void Assembler::jal(Register rd, int32_t imm21) {
1524 GenInstrJ(JAL, rd, imm21);
1528 void Assembler::jalr(Register rd, Register rs1, int16_t imm12) {
1529 GenInstrI(0b000, JALR, rd, rs1, imm12);
1561 void Assembler::lb(Register rd, Register rs1, int16_t imm12) {
1562 GenInstrLoad_ri(0b000, rd, rs1, imm12);
1565 void Assembler::lh(Register rd, Register rs1, int16_t imm12) {
1566 GenInstrLoad_ri(0b001, rd, rs1, imm12);
1569 void Assembler::lw(Register rd, Register rs1, int16_t imm12) {
1570 GenInstrLoad_ri(0b010, rd, rs1, imm12);
1573 void Assembler::lbu(Register rd, Register rs1, int16_t imm12) {
1574 GenInstrLoad_ri(0b100, rd, rs1, imm12);
1577 void Assembler::lhu(Register rd, Register rs1, int16_t imm12) {
1578 GenInstrLoad_ri(0b101, rd, rs1, imm12);
1597 void Assembler::addi(Register rd, Register rs1, int16_t imm12) {
1598 GenInstrALU_ri(0b000, rd, rs1, imm12);
1601 void Assembler::slti(Register rd, Register rs1, int16_t imm12) {
1602 GenInstrALU_ri(0b010, rd, rs1, imm12);
1605 void Assembler::sltiu(Register rd, Register rs1, int16_t imm12) {
1606 GenInstrALU_ri(0b011, rd, rs1, imm12);
1609 void Assembler::xori(Register rd, Register rs1, int16_t imm12) {
1610 GenInstrALU_ri(0b100, rd, rs1, imm12);
1613 void Assembler::ori(Register rd, Register rs1, int16_t imm12) {
1614 GenInstrALU_ri(0b110, rd, rs1, imm12);
1617 void Assembler::andi(Register rd, Register rs1, int16_t imm12) {
1618 GenInstrALU_ri(0b111, rd, rs1, imm12);
1621 void Assembler::slli(Register rd, Register rs1, uint8_t shamt) {
1622 GenInstrShift_ri(0, 0b001, rd, rs1, shamt & 0x3f);
1625 void Assembler::srli(Register rd, Register rs1, uint8_t shamt) {
1626 GenInstrShift_ri(0, 0b101, rd, rs1, shamt & 0x3f);
1629 void Assembler::srai(Register rd, Register rs1, uint8_t shamt) {
1630 GenInstrShift_ri(1, 0b101, rd, rs1, shamt & 0x3f);
1635 void Assembler::add(Register rd, Register rs1, Register rs2) {
1636 GenInstrALU_rr(0b0000000, 0b000, rd, rs1, rs2);
1639 void Assembler::sub(Register rd, Register rs1, Register rs2) {
1640 GenInstrALU_rr(0b0100000, 0b000, rd, rs1, rs2);
1643 void Assembler::sll(Register rd, Register rs1, Register rs2) {
1644 GenInstrALU_rr(0b0000000, 0b001, rd, rs1, rs2);
1647 void Assembler::slt(Register rd, Register rs1, Register rs2) {
1648 GenInstrALU_rr(0b0000000, 0b010, rd, rs1, rs2);
1651 void Assembler::sltu(Register rd, Register rs1, Register rs2) {
1652 GenInstrALU_rr(0b0000000, 0b011, rd, rs1, rs2);
1655 void Assembler::xor_(Register rd, Register rs1, Register rs2) {
1656 GenInstrALU_rr(0b0000000, 0b100, rd, rs1, rs2);
1659 void Assembler::srl(Register rd, Register rs1, Register rs2) {
1660 GenInstrALU_rr(0b0000000, 0b101, rd, rs1, rs2);
1663 void Assembler::sra(Register rd, Register rs1, Register rs2) {
1664 GenInstrALU_rr(0b0100000, 0b101, rd, rs1, rs2);
1667 void Assembler::or_(Register rd, Register rs1, Register rs2) {
1668 GenInstrALU_rr(0b0000000, 0b110, rd, rs1, rs2);
1671 void Assembler::and_(Register rd, Register rs1, Register rs2) {
1672 GenInstrALU_rr(0b0000000, 0b111, rd, rs1, rs2);
1707 void Assembler::csrrw(Register rd, ControlStatusReg csr, Register rs1) {
1708 GenInstrCSR_ir(0b001, rd, csr, rs1);
1711 void Assembler::csrrs(Register rd, ControlStatusReg csr, Register rs1) {
1712 GenInstrCSR_ir(0b010, rd, csr, rs1);
1715 void Assembler::csrrc(Register rd, ControlStatusReg csr, Register rs1) {
1716 GenInstrCSR_ir(0b011, rd, csr, rs1);
1719 void Assembler::csrrwi(Register rd, ControlStatusReg csr, uint8_t imm5) {
1720 GenInstrCSR_ii(0b101, rd, csr, imm5);
1723 void Assembler::csrrsi(Register rd, ControlStatusReg csr, uint8_t imm5) {
1724 GenInstrCSR_ii(0b110, rd, csr, imm5);
1727 void Assembler::csrrci(Register rd, ControlStatusReg csr, uint8_t imm5) {
1728 GenInstrCSR_ii(0b111, rd, csr, imm5);
1733 void Assembler::lwu(Register rd, Register rs1, int16_t imm12) {
1734 GenInstrLoad_ri(0b110, rd, rs1, imm12);
1737 void Assembler::ld(Register rd, Register rs1, int16_t imm12) {
1738 GenInstrLoad_ri(0b011, rd, rs1, imm12);
1745 void Assembler::addiw(Register rd, Register rs1, int16_t imm12) {
1746 GenInstrI(0b000, OP_IMM_32, rd, rs1, imm12);
1749 void Assembler::slliw(Register rd, Register rs1, uint8_t shamt) {
1750 GenInstrShiftW_ri(0, 0b001, rd, rs1, shamt & 0x1f);
1753 void Assembler::srliw(Register rd, Register rs1, uint8_t shamt) {
1754 GenInstrShiftW_ri(0, 0b101, rd, rs1, shamt & 0x1f);
1757 void Assembler::sraiw(Register rd, Register rs1, uint8_t shamt) {
1758 GenInstrShiftW_ri(1, 0b101, rd, rs1, shamt & 0x1f);
1761 void Assembler::addw(Register rd, Register rs1, Register rs2) {
1762 GenInstrALUW_rr(0b0000000, 0b000, rd, rs1, rs2);
1765 void Assembler::subw(Register rd, Register rs1, Register rs2) {
1766 GenInstrALUW_rr(0b0100000, 0b000, rd, rs1, rs2);
1769 void Assembler::sllw(Register rd, Register rs1, Register rs2) {
1770 GenInstrALUW_rr(0b0000000, 0b001, rd, rs1, rs2);
1773 void Assembler::srlw(Register rd, Register rs1, Register rs2) {
1774 GenInstrALUW_rr(0b0000000, 0b101, rd, rs1, rs2);
1777 void Assembler::sraw(Register rd, Register rs1, Register rs2) {
1778 GenInstrALUW_rr(0b0100000, 0b101, rd, rs1, rs2);
1783 void Assembler::mul(Register rd, Register rs1, Register rs2) {
1784 GenInstrALU_rr(0b0000001, 0b000, rd, rs1, rs2);
1787 void Assembler::mulh(Register rd, Register rs1, Register rs2) {
1788 GenInstrALU_rr(0b0000001, 0b001, rd, rs1, rs2);
1791 void Assembler::mulhsu(Register rd, Register rs1, Register rs2) {
1792 GenInstrALU_rr(0b0000001, 0b010, rd, rs1, rs2);
1795 void Assembler::mulhu(Register rd, Register rs1, Register rs2) {
1796 GenInstrALU_rr(0b0000001, 0b011, rd, rs1, rs2);
1799 void Assembler::div(Register rd, Register rs1, Register rs2) {
1800 GenInstrALU_rr(0b0000001, 0b100, rd, rs1, rs2);
1803 void Assembler::divu(Register rd, Register rs1, Register rs2) {
1804 GenInstrALU_rr(0b0000001, 0b101, rd, rs1, rs2);
1807 void Assembler::rem(Register rd, Register rs1, Register rs2) {
1808 GenInstrALU_rr(0b0000001, 0b110, rd, rs1, rs2);
1811 void Assembler::remu(Register rd, Register rs1, Register rs2) {
1812 GenInstrALU_rr(0b0000001, 0b111, rd, rs1, rs2);
1817 void Assembler::mulw(Register rd, Register rs1, Register rs2) {
1818 GenInstrALUW_rr(0b0000001, 0b000, rd, rs1, rs2);
1821 void Assembler::divw(Register rd, Register rs1, Register rs2) {
1822 GenInstrALUW_rr(0b0000001, 0b100, rd, rs1, rs2);
1825 void Assembler::divuw(Register rd, Register rs1, Register rs2) {
1826 GenInstrALUW_rr(0b0000001, 0b101, rd, rs1, rs2);
1829 void Assembler::remw(Register rd, Register rs1, Register rs2) {
1830 GenInstrALUW_rr(0b0000001, 0b110, rd, rs1, rs2);
1833 void Assembler::remuw(Register rd, Register rs1, Register rs2) {
1834 GenInstrALUW_rr(0b0000001, 0b111, rd, rs1, rs2);
1839 void Assembler::lr_w(bool aq, bool rl, Register rd, Register rs1) {
1840 GenInstrRAtomic(0b00010, aq, rl, 0b010, rd, rs1, zero_reg);
1843 void Assembler::sc_w(bool aq, bool rl, Register rd, Register rs1,
1845 GenInstrRAtomic(0b00011, aq, rl, 0b010, rd, rs1, rs2);
1848 void Assembler::amoswap_w(bool aq, bool rl, Register rd, Register rs1,
1850 GenInstrRAtomic(0b00001, aq, rl, 0b010, rd, rs1, rs2);
1853 void Assembler::amoadd_w(bool aq, bool rl, Register rd, Register rs1,
1855 GenInstrRAtomic(0b00000, aq, rl, 0b010, rd, rs1, rs2);
1858 void Assembler::amoxor_w(bool aq, bool rl, Register rd, Register rs1,
1860 GenInstrRAtomic(0b00100, aq, rl, 0b010, rd, rs1, rs2);
1863 void Assembler::amoand_w(bool aq, bool rl, Register rd, Register rs1,
1865 GenInstrRAtomic(0b01100, aq, rl, 0b010, rd, rs1, rs2);
1868 void Assembler::amoor_w(bool aq, bool rl, Register rd, Register rs1,
1870 GenInstrRAtomic(0b01000, aq, rl, 0b010, rd, rs1, rs2);
1873 void Assembler::amomin_w(bool aq, bool rl, Register rd, Register rs1,
1875 GenInstrRAtomic(0b10000, aq, rl, 0b010, rd, rs1, rs2);
1878 void Assembler::amomax_w(bool aq, bool rl, Register rd, Register rs1,
1880 GenInstrRAtomic(0b10100, aq, rl, 0b010, rd, rs1, rs2);
1883 void Assembler::amominu_w(bool aq, bool rl, Register rd, Register rs1,
1885 GenInstrRAtomic(0b11000, aq, rl, 0b010, rd, rs1, rs2);
1888 void Assembler::amomaxu_w(bool aq, bool rl, Register rd, Register rs1,
1890 GenInstrRAtomic(0b11100, aq, rl, 0b010, rd, rs1, rs2);
1895 void Assembler::lr_d(bool aq, bool rl, Register rd, Register rs1) {
1896 GenInstrRAtomic(0b00010, aq, rl, 0b011, rd, rs1, zero_reg);
1899 void Assembler::sc_d(bool aq, bool rl, Register rd, Register rs1,
1901 GenInstrRAtomic(0b00011, aq, rl, 0b011, rd, rs1, rs2);
1904 void Assembler::amoswap_d(bool aq, bool rl, Register rd, Register rs1,
1906 GenInstrRAtomic(0b00001, aq, rl, 0b011, rd, rs1, rs2);
1909 void Assembler::amoadd_d(bool aq, bool rl, Register rd, Register rs1,
1911 GenInstrRAtomic(0b00000, aq, rl, 0b011, rd, rs1, rs2);
1914 void Assembler::amoxor_d(bool aq, bool rl, Register rd, Register rs1,
1916 GenInstrRAtomic(0b00100, aq, rl, 0b011, rd, rs1, rs2);
1919 void Assembler::amoand_d(bool aq, bool rl, Register rd, Register rs1,
1921 GenInstrRAtomic(0b01100, aq, rl, 0b011, rd, rs1, rs2);
1924 void Assembler::amoor_d(bool aq, bool rl, Register rd, Register rs1,
1926 GenInstrRAtomic(0b01000, aq, rl, 0b011, rd, rs1, rs2);
1929 void Assembler::amomin_d(bool aq, bool rl, Register rd, Register rs1,
1931 GenInstrRAtomic(0b10000, aq, rl, 0b011, rd, rs1, rs2);
1934 void Assembler::amomax_d(bool aq, bool rl, Register rd, Register rs1,
1936 GenInstrRAtomic(0b10100, aq, rl, 0b011, rd, rs1, rs2);
1939 void Assembler::amominu_d(bool aq, bool rl, Register rd, Register rs1,
1941 GenInstrRAtomic(0b11000, aq, rl, 0b011, rd, rs1, rs2);
1944 void Assembler::amomaxu_d(bool aq, bool rl, Register rd, Register rs1,
1946 GenInstrRAtomic(0b11100, aq, rl, 0b011, rd, rs1, rs2);
1951 void Assembler::flw(FPURegister rd, Register rs1, int16_t imm12) {
1952 GenInstrLoadFP_ri(0b010, rd, rs1, imm12);
1959 void Assembler::fmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1961 GenInstrR4(0b00, MADD, rd, rs1, rs2, rs3, frm);
1964 void Assembler::fmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1966 GenInstrR4(0b00, MSUB, rd, rs1, rs2, rs3, frm);
1969 void Assembler::fnmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1971 GenInstrR4(0b00, NMSUB, rd, rs1, rs2, rs3, frm);
1974 void Assembler::fnmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1976 GenInstrR4(0b00, NMADD, rd, rs1, rs2, rs3, frm);
1979 void Assembler::fadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1981 GenInstrALUFP_rr(0b0000000, frm, rd, rs1, rs2);
1984 void Assembler::fsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1986 GenInstrALUFP_rr(0b0000100, frm, rd, rs1, rs2);
1989 void Assembler::fmul_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1991 GenInstrALUFP_rr(0b0001000, frm, rd, rs1, rs2);
1994 void Assembler::fdiv_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1996 GenInstrALUFP_rr(0b0001100, frm, rd, rs1, rs2);
1999 void Assembler::fsqrt_s(FPURegister rd, FPURegister rs1, RoundingMode frm) {
2000 GenInstrALUFP_rr(0b0101100, frm, rd, rs1, zero_reg);
2003 void Assembler::fsgnj_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2004 GenInstrALUFP_rr(0b0010000, 0b000, rd, rs1, rs2);
2007 void Assembler::fsgnjn_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2008 GenInstrALUFP_rr(0b0010000, 0b001, rd, rs1, rs2);
2011 void Assembler::fsgnjx_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2012 GenInstrALUFP_rr(0b0010000, 0b010, rd, rs1, rs2);
2015 void Assembler::fmin_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2016 GenInstrALUFP_rr(0b0010100, 0b000, rd, rs1, rs2);
2019 void Assembler::fmax_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2020 GenInstrALUFP_rr(0b0010100, 0b001, rd, rs1, rs2);
2023 void Assembler::fcvt_w_s(Register rd, FPURegister rs1, RoundingMode frm) {
2024 GenInstrALUFP_rr(0b1100000, frm, rd, rs1, zero_reg);
2027 void Assembler::fcvt_wu_s(Register rd, FPURegister rs1, RoundingMode frm) {
2028 GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(1));
2031 void Assembler::fmv_x_w(Register rd, FPURegister rs1) {
2032 GenInstrALUFP_rr(0b1110000, 0b000, rd, rs1, zero_reg);
2035 void Assembler::feq_s(Register rd, FPURegister rs1, FPURegister rs2) {
2036 GenInstrALUFP_rr(0b1010000, 0b010, rd, rs1, rs2);
2039 void Assembler::flt_s(Register rd, FPURegister rs1, FPURegister rs2) {
2040 GenInstrALUFP_rr(0b1010000, 0b001, rd, rs1, rs2);
2043 void Assembler::fle_s(Register rd, FPURegister rs1, FPURegister rs2) {
2044 GenInstrALUFP_rr(0b1010000, 0b000, rd, rs1, rs2);
2047 void Assembler::fclass_s(Register rd, FPURegister rs1) {
2048 GenInstrALUFP_rr(0b1110000, 0b001, rd, rs1, zero_reg);
2051 void Assembler::fcvt_s_w(FPURegister rd, Register rs1, RoundingMode frm) {
2052 GenInstrALUFP_rr(0b1101000, frm, rd, rs1, zero_reg);
2055 void Assembler::fcvt_s_wu(FPURegister rd, Register rs1, RoundingMode frm) {
2056 GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(1));
2059 void Assembler::fmv_w_x(FPURegister rd, Register rs1) {
2060 GenInstrALUFP_rr(0b1111000, 0b000, rd, rs1, zero_reg);
2065 void Assembler::fcvt_l_s(Register rd, FPURegister rs1, RoundingMode frm) {
2066 GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(2));
2069 void Assembler::fcvt_lu_s(Register rd, FPURegister rs1, RoundingMode frm) {
2070 GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(3));
2073 void Assembler::fcvt_s_l(FPURegister rd, Register rs1, RoundingMode frm) {
2074 GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(2));
2077 void Assembler::fcvt_s_lu(FPURegister rd, Register rs1, RoundingMode frm) {
2078 GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(3));
2083 void Assembler::fld(FPURegister rd, Register rs1, int16_t imm12) {
2084 GenInstrLoadFP_ri(0b011, rd, rs1, imm12);
2091 void Assembler::fmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2093 GenInstrR4(0b01, MADD, rd, rs1, rs2, rs3, frm);
2096 void Assembler::fmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2098 GenInstrR4(0b01, MSUB, rd, rs1, rs2, rs3, frm);
2101 void Assembler::fnmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2103 GenInstrR4(0b01, NMSUB, rd, rs1, rs2, rs3, frm);
2106 void Assembler::fnmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2108 GenInstrR4(0b01, NMADD, rd, rs1, rs2, rs3, frm);
2111 void Assembler::fadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2113 GenInstrALUFP_rr(0b0000001, frm, rd, rs1, rs2);
2116 void Assembler::fsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2118 GenInstrALUFP_rr(0b0000101, frm, rd, rs1, rs2);
2121 void Assembler::fmul_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2123 GenInstrALUFP_rr(0b0001001, frm, rd, rs1, rs2);
2126 void Assembler::fdiv_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2128 GenInstrALUFP_rr(0b0001101, frm, rd, rs1, rs2);
2131 void Assembler::fsqrt_d(FPURegister rd, FPURegister rs1, RoundingMode frm) {
2132 GenInstrALUFP_rr(0b0101101, frm, rd, rs1, zero_reg);
2135 void Assembler::fsgnj_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2136 GenInstrALUFP_rr(0b0010001, 0b000, rd, rs1, rs2);
2139 void Assembler::fsgnjn_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2140 GenInstrALUFP_rr(0b0010001, 0b001, rd, rs1, rs2);
2143 void Assembler::fsgnjx_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2144 GenInstrALUFP_rr(0b0010001, 0b010, rd, rs1, rs2);
2147 void Assembler::fmin_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2148 GenInstrALUFP_rr(0b0010101, 0b000, rd, rs1, rs2);
2151 void Assembler::fmax_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2152 GenInstrALUFP_rr(0b0010101, 0b001, rd, rs1, rs2);
2155 void Assembler::fcvt_s_d(FPURegister rd, FPURegister rs1, RoundingMode frm) {
2156 GenInstrALUFP_rr(0b0100000, frm, rd, rs1, ToRegister(1));
2159 void Assembler::fcvt_d_s(FPURegister rd, FPURegister rs1, RoundingMode frm) {
2160 GenInstrALUFP_rr(0b0100001, frm, rd, rs1, zero_reg);
2163 void Assembler::feq_d(Register rd, FPURegister rs1, FPURegister rs2) {
2164 GenInstrALUFP_rr(0b1010001, 0b010, rd, rs1, rs2);
2167 void Assembler::flt_d(Register rd, FPURegister rs1, FPURegister rs2) {
2168 GenInstrALUFP_rr(0b1010001, 0b001, rd, rs1, rs2);
2171 void Assembler::fle_d(Register rd, FPURegister rs1, FPURegister rs2) {
2172 GenInstrALUFP_rr(0b1010001, 0b000, rd, rs1, rs2);
2175 void Assembler::fclass_d(Register rd, FPURegister rs1) {
2176 GenInstrALUFP_rr(0b1110001, 0b001, rd, rs1, zero_reg);
2179 void Assembler::fcvt_w_d(Register rd, FPURegister rs1, RoundingMode frm) {
2180 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, zero_reg);
2183 void Assembler::fcvt_wu_d(Register rd, FPURegister rs1, RoundingMode frm) {
2184 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(1));
2187 void Assembler::fcvt_d_w(FPURegister rd, Register rs1, RoundingMode frm) {
2188 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, zero_reg);
2191 void Assembler::fcvt_d_wu(FPURegister rd, Register rs1, RoundingMode frm) {
2192 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(1));
2197 void Assembler::fcvt_l_d(Register rd, FPURegister rs1, RoundingMode frm) {
2198 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(2));
2201 void Assembler::fcvt_lu_d(Register rd, FPURegister rs1, RoundingMode frm) {
2202 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(3));
2205 void Assembler::fmv_x_d(Register rd, FPURegister rs1) {
2206 GenInstrALUFP_rr(0b1110001, 0b000, rd, rs1, zero_reg);
2209 void Assembler::fcvt_d_l(FPURegister rd, Register rs1, RoundingMode frm) {
2210 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(2));
2213 void Assembler::fcvt_d_lu(FPURegister rd, Register rs1, RoundingMode frm) {
2214 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(3));
2217 void Assembler::fmv_d_x(FPURegister rd, Register rs1) {
2218 GenInstrALUFP_rr(0b1111001, 0b000, rd, rs1, zero_reg);
2224 void Assembler::c_addi(Register rd, int8_t imm6) {
2225 DCHECK(rd != zero_reg && imm6 != 0);
2226 GenInstrCI(0b000, C1, rd, imm6);
2229 void Assembler::c_addiw(Register rd, int8_t imm6) {
2230 DCHECK(rd != zero_reg);
2231 GenInstrCI(0b001, C1, rd, imm6);
2242 void Assembler::c_addi4spn(Register rd, int16_t uimm10) {
2246 GenInstrCIW(0b000, C0, rd, uimm8);
2249 void Assembler::c_li(Register rd, int8_t imm6) {
2250 DCHECK(rd != zero_reg);
2251 GenInstrCI(0b010, C1, rd, imm6);
2254 void Assembler::c_lui(Register rd, int8_t imm6) {
2255 DCHECK(rd != zero_reg && rd != sp && imm6 != 0);
2256 GenInstrCI(0b011, C1, rd, imm6);
2259 void Assembler::c_slli(Register rd, uint8_t shamt6) {
2260 DCHECK(rd != zero_reg && shamt6 != 0);
2261 GenInstrCIU(0b000, C2, rd, shamt6);
2264 void Assembler::c_fldsp(FPURegister rd, uint16_t uimm9) {
2267 GenInstrCIU(0b001, C2, rd, uimm6);
2270 void Assembler::c_lwsp(Register rd, uint16_t uimm8) {
2271 DCHECK(rd != zero_reg && is_uint8(uimm8) && (uimm8 & 0x3) == 0);
2273 GenInstrCIU(0b010, C2, rd, uimm6);
2276 void Assembler::c_ldsp(Register rd, uint16_t uimm9) {
2277 DCHECK(rd != zero_reg && is_uint9(uimm9) && (uimm9 & 0x7) == 0);
2279 GenInstrCIU(0b011, C2, rd, uimm6);
2288 void Assembler::c_mv(Register rd, Register rs2) {
2289 DCHECK(rd != zero_reg && rs2 != zero_reg);
2290 GenInstrCR(0b1000, C2, rd, rs2);
2301 void Assembler::c_add(Register rd, Register rs2) {
2302 DCHECK(rd != zero_reg && rs2 != zero_reg);
2303 GenInstrCR(0b1001, C2, rd, rs2);
2307 void Assembler::c_sub(Register rd, Register rs2) {
2308 DCHECK(((rd.code() & 0b11000) == 0b01000) &&
2310 GenInstrCA(0b100011, C1, rd, 0b00, rs2);
2313 void Assembler::c_xor(Register rd, Register rs2) {
2314 DCHECK(((rd.code() & 0b11000) == 0b01000) &&
2316 GenInstrCA(0b100011, C1, rd, 0b01, rs2);
2319 void Assembler::c_or(Register rd, Register rs2) {
2320 DCHECK(((rd.code() & 0b11000) == 0b01000) &&
2322 GenInstrCA(0b100011, C1, rd, 0b10, rs2);
2325 void Assembler::c_and(Register rd, Register rs2) {
2326 DCHECK(((rd.code() & 0b11000) == 0b01000) &&
2328 GenInstrCA(0b100011, C1, rd, 0b11, rs2);
2331 void Assembler::c_subw(Register rd, Register rs2) {
2332 DCHECK(((rd.code() & 0b11000) == 0b01000) &&
2334 GenInstrCA(0b100111, C1, rd, 0b00, rs2);
2337 void Assembler::c_addw(Register rd, Register rs2) {
2338 DCHECK(((rd.code() & 0b11000) == 0b01000) &&
2340 GenInstrCA(0b100111, C1, rd, 0b01, rs2);
2363 void Assembler::c_lw(Register rd, Register rs1, uint16_t uimm7) {
2364 DCHECK(((rd.code() & 0b11000) == 0b01000) &&
2369 GenInstrCL(0b010, C0, rd, rs1, uimm5);
2372 void Assembler::c_ld(Register rd, Register rs1, uint16_t uimm8) {
2373 DCHECK(((rd.code() & 0b11000) == 0b01000) &&
2377 GenInstrCL(0b011, C0, rd, rs1, uimm5);
2380 void Assembler::c_fld(FPURegister rd, Register rs1, uint16_t uimm8) {
2381 DCHECK(((rd.code() & 0b11000) == 0b01000) &&
2385 GenInstrCL(0b001, C0, rd, rs1, uimm5);
2508 void Assembler::vmv_xs(Register rd, VRegister vs2) {
2509 GenInstrV(VWXUNARY0_FUNCT6, OP_MVV, rd, 0b00000, vs2, NoMask);
2869 void Assembler::vsetvli(Register rd, Register rs1, VSew vsew, Vlmul vlmul,
2872 Instr instr = OP_V | ((rd.code() & 0x1F) << kRvvRdShift) | (0x7 << 12) |
2878 void Assembler::vsetivli(Register rd, uint8_t uimm, VSew vsew, Vlmul vlmul,
2882 Instr instr = OP_V | ((rd.code() & 0x1F) << kRvvRdShift) | (0x7 << 12) |
2888 void Assembler::vsetvl(Register rd, Register rs1, Register rs2) {
2889 Instr instr = OP_V | ((rd.code() & 0x1F) << kRvvRdShift) | (0x7 << 12) |
3171 void Assembler::vfirst_m(Register rd, VRegister vs2, MaskType mask) {
3172 GenInstrV(VWXUNARY0_FUNCT6, OP_MVV, rd, 0b10001, vs2, mask);
3175 void Assembler::vcpop_m(Register rd, VRegister vs2, MaskType mask) {
3176 GenInstrV(VWXUNARY0_FUNCT6, OP_MVV, rd, 0b10000, vs2, mask);
3204 void Assembler::RV_li(Register rd, int64_t imm) {
3205 // 64-bit imm is put in the register rd.
3215 // available, the upper 32 bit is built in rd, and the lower 32 bits are
3217 // to the upper part built in rd.
3223 lui(rd, (int32_t)high_20);
3225 addi(rd, rd, low_12);
3228 addi(rd, zero_reg, low_12);
3235 Register temp_reg = rd;
3255 lui(rd, (int32_t)high_20);
3258 addi(rd, rd, low_12);
3262 ori(rd, zero_reg, low_12);
3269 slli(rd, rd, 32);
3270 srli(rd, rd, 32);
3281 // Build upper part in rd
3282 temp_reg = rd;
3299 add(rd, rd, temp_reg);
3303 // No temp register. Build imm in rd.
3304 // Build upper 32 bits first in rd. Divide lower 32 bits parts and add
3306 // First build upper part in rd.
3312 lui(rd, (int32_t)high_20);
3314 addi(rd, rd, low_12);
3317 ori(rd, zero_reg, low_12);
3319 // upper part already in rd. Each part to be added to rd, has maximum of 11
3320 // bits, and always starts with a 1. rd is shifted by the size of the part
3332 slli(rd, rd, shift_val);
3341 slli(rd, rd, shift_val + 11);
3342 ori(rd, rd, part);
3347 slli(rd, rd, shift_val + (32 - i));
3348 ori(rd, rd, part);
3431 // No temp register. Build imm in rd.
3432 // Build upper 32 bits first in rd. Divide lower 32 bits parts and add
3434 // First build upper part in rd.
3447 // upper part already in rd. Each part to be added to rd, has maximum of 11
3448 // bits, and always starts with a 1. rd is shifted by the size of the part
3479 void Assembler::li_ptr(Register rd, int64_t imm) {
3480 // Initialize rd with an address
3489 lui(rd, (int32_t)high_20);
3490 addi(rd, rd, low_12); // 31 bits in rd.
3491 slli(rd, rd, 11); // Space for next 11 bis
3492 ori(rd, rd, b11); // 11 bits are put in. 42 bit in rd
3493 slli(rd, rd, 6); // Space for next 6 bits
3494 ori(rd, rd, a6); // 6 bits are put in. 48 bis in rd
3497 void Assembler::li_constant(Register rd, int64_t imm) {
3498 DEBUG_PRINTF("li_constant(%d, %lx <%ld>)\n", ToNumber(rd), imm, imm);
3499 lui(rd, (imm + (1LL << 47) + (1LL << 35) + (1LL << 23) + (1LL << 11)) >>
3501 addiw(rd, rd,
3504 slli(rd, rd, 12);
3505 addi(rd, rd, (imm + (1LL << 23) + (1LL << 11)) << 28 >> 52); // Bits 35:24
3506 slli(rd, rd, 12);
3507 addi(rd, rd, (imm + (1LL << 11)) << 40 >> 52); // Bits 23:12
3508 slli(rd, rd, 12);
3509 addi(rd, rd, imm << 52 >> 52); // Bits 11:0
4010 // Instruction to patch must be 'ld rd, offset(rd)' with 'offset == 0'.