Lines Matching defs:shamt
938 Register rd, Register rs1, uint8_t shamt) {
940 is_uint6(shamt));
942 (rs1.code() << kRs1Shift) | (shamt << kShamtShift) |
948 Register rd, Register rs1, uint8_t shamt) {
950 is_uint5(shamt));
952 (rs1.code() << kRs1Shift) | (shamt << kShamtWShift) |
1306 Register rs1, uint8_t shamt) {
1307 DCHECK(is_uint6(shamt));
1308 GenInstrI(funct3, OP_IMM, rd, rs1, (arithshift << 10) | shamt);
1327 Register rs1, uint8_t shamt) {
1328 GenInstrIShiftW(arithshift, funct3, OP_IMM_32, rd, rs1, shamt);
1621 void Assembler::slli(Register rd, Register rs1, uint8_t shamt) {
1622 GenInstrShift_ri(0, 0b001, rd, rs1, shamt & 0x3f);
1625 void Assembler::srli(Register rd, Register rs1, uint8_t shamt) {
1626 GenInstrShift_ri(0, 0b101, rd, rs1, shamt & 0x3f);
1629 void Assembler::srai(Register rd, Register rs1, uint8_t shamt) {
1630 GenInstrShift_ri(1, 0b101, rd, rs1, shamt & 0x3f);
1749 void Assembler::slliw(Register rd, Register rs1, uint8_t shamt) {
1750 GenInstrShiftW_ri(0, 0b001, rd, rs1, shamt & 0x1f);
1753 void Assembler::srliw(Register rd, Register rs1, uint8_t shamt) {
1754 GenInstrShiftW_ri(0, 0b101, rd, rs1, shamt & 0x1f);
1757 void Assembler::sraiw(Register rd, Register rs1, uint8_t shamt) {
1758 GenInstrShiftW_ri(1, 0b101, rd, rs1, shamt & 0x1f);