Lines Matching defs:rs3
878 Register rs1, Register rs2, Register rs3,
881 rs2.is_valid() && rs3.is_valid() && is_uint3(frm));
884 (funct2 << kFunct2Shift) | (rs3.code() << kRs3Shift);
889 FPURegister rs1, FPURegister rs2, FPURegister rs3,
892 rs2.is_valid() && rs3.is_valid() && is_uint3(frm));
895 (funct2 << kFunct2Shift) | (rs3.code() << kRs3Shift);
1960 FPURegister rs3, RoundingMode frm) {
1961 GenInstrR4(0b00, MADD, rd, rs1, rs2, rs3, frm);
1965 FPURegister rs3, RoundingMode frm) {
1966 GenInstrR4(0b00, MSUB, rd, rs1, rs2, rs3, frm);
1970 FPURegister rs3, RoundingMode frm) {
1971 GenInstrR4(0b00, NMSUB, rd, rs1, rs2, rs3, frm);
1975 FPURegister rs3, RoundingMode frm) {
1976 GenInstrR4(0b00, NMADD, rd, rs1, rs2, rs3, frm);
2092 FPURegister rs3, RoundingMode frm) {
2093 GenInstrR4(0b01, MADD, rd, rs1, rs2, rs3, frm);
2097 FPURegister rs3, RoundingMode frm) {
2098 GenInstrR4(0b01, MSUB, rd, rs1, rs2, rs3, frm);
2102 FPURegister rs3, RoundingMode frm) {
2103 GenInstrR4(0b01, NMSUB, rd, rs1, rs2, rs3, frm);
2107 FPURegister rs3, RoundingMode frm) {
2108 GenInstrR4(0b01, NMADD, rd, rs1, rs2, rs3, frm);