Lines Matching defs:rs2
730 // | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode |
818 Register rd, Register rs1, Register rs2) {
820 rs1.is_valid() && rs2.is_valid());
822 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
828 FPURegister rd, FPURegister rs1, FPURegister rs2) {
830 rs1.is_valid() && rs2.is_valid());
832 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
838 Register rd, FPURegister rs1, Register rs2) {
840 rs1.is_valid() && rs2.is_valid());
842 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
848 FPURegister rd, Register rs1, Register rs2) {
850 rs1.is_valid() && rs2.is_valid());
852 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
858 FPURegister rd, FPURegister rs1, Register rs2) {
860 rs1.is_valid() && rs2.is_valid());
862 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
868 Register rd, FPURegister rs1, FPURegister rs2) {
870 rs1.is_valid() && rs2.is_valid());
872 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
878 Register rs1, Register rs2, Register rs3,
881 rs2.is_valid() && rs3.is_valid() && is_uint3(frm));
883 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
889 FPURegister rs1, FPURegister rs2, FPURegister rs3,
892 rs2.is_valid() && rs3.is_valid() && is_uint3(frm));
894 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
901 Register rs2) {
903 rs1.is_valid() && rs2.is_valid());
905 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
911 Register rs1, Register rs2, RoundingMode frm) {
912 DCHECK(rd.is_valid() && rs1.is_valid() && rs2.is_valid() && is_uint3(frm));
914 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
958 Register rs2, int16_t imm12) {
959 DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() &&
963 (rs2.code() << kRs2Shift) |
969 FPURegister rs2, int16_t imm12) {
970 DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() &&
974 (rs2.code() << kRs2Shift) |
980 Register rs2, int16_t imm13) {
981 DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() &&
986 (rs2.code() << kRs2Shift) |
1009 Register rs2) {
1010 DCHECK(is_uint4(funct4) && rd.is_valid() && rs2.is_valid());
1011 ShortInstr instr = opcode | (rs2.code() << kRvcRs2Shift) |
1017 uint8_t funct, Register rs2) {
1018 DCHECK(is_uint6(funct6) && rd.is_valid() && rs2.is_valid() &&
1020 ShortInstr instr = opcode | ((rs2.code() & 0x7) << kRvcRs2sShift) |
1062 void Assembler::GenInstrCSS(uint8_t funct3, Opcode opcode, Register rs2,
1064 DCHECK(is_uint3(funct3) && rs2.is_valid() && is_uint6(uimm6));
1065 ShortInstr instr = opcode | (uimm6 << 7) | (rs2.code() << kRvcRs2Shift) |
1070 void Assembler::GenInstrCSS(uint8_t funct3, Opcode opcode, FPURegister rs2,
1072 DCHECK(is_uint3(funct3) && rs2.is_valid() && is_uint6(uimm6));
1073 ShortInstr instr = opcode | (uimm6 << 7) | (rs2.code() << kRvcRs2Shift) |
1105 void Assembler::GenInstrCS(uint8_t funct3, Opcode opcode, Register rs2,
1107 DCHECK(is_uint3(funct3) && rs2.is_valid() && rs1.is_valid() &&
1110 ((rs2.code() & 0x7) << kRvcRs2sShift) |
1116 void Assembler::GenInstrCS(uint8_t funct3, Opcode opcode, FPURegister rs2,
1118 DCHECK(is_uint3(funct3) && rs2.is_valid() && rs1.is_valid() &&
1121 ((rs2.code() & 0x7) << kRvcRs2sShift) |
1245 Register rs1, Register rs2, MaskType mask,
1251 ((rs2.code() << kRvvRs2Shift) & kRvvRs2Mask) |
1285 void Assembler::GenInstrBranchCC_rri(uint8_t funct3, Register rs1, Register rs2,
1287 GenInstrB(funct3, BRANCH, rs1, rs2, imm13);
1295 void Assembler::GenInstrStore_rri(uint8_t funct3, Register rs1, Register rs2,
1297 GenInstrS(funct3, STORE, rs1, rs2, imm12);
1312 Register rs1, Register rs2) {
1313 GenInstrR(funct7, funct3, OP, rd, rs1, rs2);
1332 Register rs1, Register rs2) {
1333 GenInstrR(funct7, funct3, OP_32, rd, rs1, rs2);
1336 void Assembler::GenInstrPriv(uint8_t funct7, Register rs1, Register rs2) {
1337 GenInstrR(funct7, 0b000, SYSTEM, ToRegister(0), rs1, rs2);
1346 FPURegister rs2, int16_t imm12) {
1347 GenInstrS(funct3, STORE_FP, rs1, rs2, imm12);
1351 FPURegister rs1, FPURegister rs2) {
1352 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1356 Register rs1, Register rs2) {
1357 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1361 FPURegister rs1, Register rs2) {
1362 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1366 FPURegister rs1, Register rs2) {
1367 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1371 FPURegister rs1, FPURegister rs2) {
1372 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1535 void Assembler::beq(Register rs1, Register rs2, int16_t imm13) {
1536 GenInstrBranchCC_rri(0b000, rs1, rs2, imm13);
1539 void Assembler::bne(Register rs1, Register rs2, int16_t imm13) {
1540 GenInstrBranchCC_rri(0b001, rs1, rs2, imm13);
1543 void Assembler::blt(Register rs1, Register rs2, int16_t imm13) {
1544 GenInstrBranchCC_rri(0b100, rs1, rs2, imm13);
1547 void Assembler::bge(Register rs1, Register rs2, int16_t imm13) {
1548 GenInstrBranchCC_rri(0b101, rs1, rs2, imm13);
1551 void Assembler::bltu(Register rs1, Register rs2, int16_t imm13) {
1552 GenInstrBranchCC_rri(0b110, rs1, rs2, imm13);
1555 void Assembler::bgeu(Register rs1, Register rs2, int16_t imm13) {
1556 GenInstrBranchCC_rri(0b111, rs1, rs2, imm13);
1635 void Assembler::add(Register rd, Register rs1, Register rs2) {
1636 GenInstrALU_rr(0b0000000, 0b000, rd, rs1, rs2);
1639 void Assembler::sub(Register rd, Register rs1, Register rs2) {
1640 GenInstrALU_rr(0b0100000, 0b000, rd, rs1, rs2);
1643 void Assembler::sll(Register rd, Register rs1, Register rs2) {
1644 GenInstrALU_rr(0b0000000, 0b001, rd, rs1, rs2);
1647 void Assembler::slt(Register rd, Register rs1, Register rs2) {
1648 GenInstrALU_rr(0b0000000, 0b010, rd, rs1, rs2);
1651 void Assembler::sltu(Register rd, Register rs1, Register rs2) {
1652 GenInstrALU_rr(0b0000000, 0b011, rd, rs1, rs2);
1655 void Assembler::xor_(Register rd, Register rs1, Register rs2) {
1656 GenInstrALU_rr(0b0000000, 0b100, rd, rs1, rs2);
1659 void Assembler::srl(Register rd, Register rs1, Register rs2) {
1660 GenInstrALU_rr(0b0000000, 0b101, rd, rs1, rs2);
1663 void Assembler::sra(Register rd, Register rs1, Register rs2) {
1664 GenInstrALU_rr(0b0100000, 0b101, rd, rs1, rs2);
1667 void Assembler::or_(Register rd, Register rs1, Register rs2) {
1668 GenInstrALU_rr(0b0000000, 0b110, rd, rs1, rs2);
1671 void Assembler::and_(Register rd, Register rs1, Register rs2) {
1672 GenInstrALU_rr(0b0000000, 0b111, rd, rs1, rs2);
1761 void Assembler::addw(Register rd, Register rs1, Register rs2) {
1762 GenInstrALUW_rr(0b0000000, 0b000, rd, rs1, rs2);
1765 void Assembler::subw(Register rd, Register rs1, Register rs2) {
1766 GenInstrALUW_rr(0b0100000, 0b000, rd, rs1, rs2);
1769 void Assembler::sllw(Register rd, Register rs1, Register rs2) {
1770 GenInstrALUW_rr(0b0000000, 0b001, rd, rs1, rs2);
1773 void Assembler::srlw(Register rd, Register rs1, Register rs2) {
1774 GenInstrALUW_rr(0b0000000, 0b101, rd, rs1, rs2);
1777 void Assembler::sraw(Register rd, Register rs1, Register rs2) {
1778 GenInstrALUW_rr(0b0100000, 0b101, rd, rs1, rs2);
1783 void Assembler::mul(Register rd, Register rs1, Register rs2) {
1784 GenInstrALU_rr(0b0000001, 0b000, rd, rs1, rs2);
1787 void Assembler::mulh(Register rd, Register rs1, Register rs2) {
1788 GenInstrALU_rr(0b0000001, 0b001, rd, rs1, rs2);
1791 void Assembler::mulhsu(Register rd, Register rs1, Register rs2) {
1792 GenInstrALU_rr(0b0000001, 0b010, rd, rs1, rs2);
1795 void Assembler::mulhu(Register rd, Register rs1, Register rs2) {
1796 GenInstrALU_rr(0b0000001, 0b011, rd, rs1, rs2);
1799 void Assembler::div(Register rd, Register rs1, Register rs2) {
1800 GenInstrALU_rr(0b0000001, 0b100, rd, rs1, rs2);
1803 void Assembler::divu(Register rd, Register rs1, Register rs2) {
1804 GenInstrALU_rr(0b0000001, 0b101, rd, rs1, rs2);
1807 void Assembler::rem(Register rd, Register rs1, Register rs2) {
1808 GenInstrALU_rr(0b0000001, 0b110, rd, rs1, rs2);
1811 void Assembler::remu(Register rd, Register rs1, Register rs2) {
1812 GenInstrALU_rr(0b0000001, 0b111, rd, rs1, rs2);
1817 void Assembler::mulw(Register rd, Register rs1, Register rs2) {
1818 GenInstrALUW_rr(0b0000001, 0b000, rd, rs1, rs2);
1821 void Assembler::divw(Register rd, Register rs1, Register rs2) {
1822 GenInstrALUW_rr(0b0000001, 0b100, rd, rs1, rs2);
1825 void Assembler::divuw(Register rd, Register rs1, Register rs2) {
1826 GenInstrALUW_rr(0b0000001, 0b101, rd, rs1, rs2);
1829 void Assembler::remw(Register rd, Register rs1, Register rs2) {
1830 GenInstrALUW_rr(0b0000001, 0b110, rd, rs1, rs2);
1833 void Assembler::remuw(Register rd, Register rs1, Register rs2) {
1834 GenInstrALUW_rr(0b0000001, 0b111, rd, rs1, rs2);
1844 Register rs2) {
1845 GenInstrRAtomic(0b00011, aq, rl, 0b010, rd, rs1, rs2);
1849 Register rs2) {
1850 GenInstrRAtomic(0b00001, aq, rl, 0b010, rd, rs1, rs2);
1854 Register rs2) {
1855 GenInstrRAtomic(0b00000, aq, rl, 0b010, rd, rs1, rs2);
1859 Register rs2) {
1860 GenInstrRAtomic(0b00100, aq, rl, 0b010, rd, rs1, rs2);
1864 Register rs2) {
1865 GenInstrRAtomic(0b01100, aq, rl, 0b010, rd, rs1, rs2);
1869 Register rs2) {
1870 GenInstrRAtomic(0b01000, aq, rl, 0b010, rd, rs1, rs2);
1874 Register rs2) {
1875 GenInstrRAtomic(0b10000, aq, rl, 0b010, rd, rs1, rs2);
1879 Register rs2) {
1880 GenInstrRAtomic(0b10100, aq, rl, 0b010, rd, rs1, rs2);
1884 Register rs2) {
1885 GenInstrRAtomic(0b11000, aq, rl, 0b010, rd, rs1, rs2);
1889 Register rs2) {
1890 GenInstrRAtomic(0b11100, aq, rl, 0b010, rd, rs1, rs2);
1900 Register rs2) {
1901 GenInstrRAtomic(0b00011, aq, rl, 0b011, rd, rs1, rs2);
1905 Register rs2) {
1906 GenInstrRAtomic(0b00001, aq, rl, 0b011, rd, rs1, rs2);
1910 Register rs2) {
1911 GenInstrRAtomic(0b00000, aq, rl, 0b011, rd, rs1, rs2);
1915 Register rs2) {
1916 GenInstrRAtomic(0b00100, aq, rl, 0b011, rd, rs1, rs2);
1920 Register rs2) {
1921 GenInstrRAtomic(0b01100, aq, rl, 0b011, rd, rs1, rs2);
1925 Register rs2) {
1926 GenInstrRAtomic(0b01000, aq, rl, 0b011, rd, rs1, rs2);
1930 Register rs2) {
1931 GenInstrRAtomic(0b10000, aq, rl, 0b011, rd, rs1, rs2);
1935 Register rs2) {
1936 GenInstrRAtomic(0b10100, aq, rl, 0b011, rd, rs1, rs2);
1940 Register rs2) {
1941 GenInstrRAtomic(0b11000, aq, rl, 0b011, rd, rs1, rs2);
1945 Register rs2) {
1946 GenInstrRAtomic(0b11100, aq, rl, 0b011, rd, rs1, rs2);
1959 void Assembler::fmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1961 GenInstrR4(0b00, MADD, rd, rs1, rs2, rs3, frm);
1964 void Assembler::fmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1966 GenInstrR4(0b00, MSUB, rd, rs1, rs2, rs3, frm);
1969 void Assembler::fnmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1971 GenInstrR4(0b00, NMSUB, rd, rs1, rs2, rs3, frm);
1974 void Assembler::fnmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1976 GenInstrR4(0b00, NMADD, rd, rs1, rs2, rs3, frm);
1979 void Assembler::fadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1981 GenInstrALUFP_rr(0b0000000, frm, rd, rs1, rs2);
1984 void Assembler::fsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1986 GenInstrALUFP_rr(0b0000100, frm, rd, rs1, rs2);
1989 void Assembler::fmul_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1991 GenInstrALUFP_rr(0b0001000, frm, rd, rs1, rs2);
1994 void Assembler::fdiv_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1996 GenInstrALUFP_rr(0b0001100, frm, rd, rs1, rs2);
2003 void Assembler::fsgnj_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2004 GenInstrALUFP_rr(0b0010000, 0b000, rd, rs1, rs2);
2007 void Assembler::fsgnjn_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2008 GenInstrALUFP_rr(0b0010000, 0b001, rd, rs1, rs2);
2011 void Assembler::fsgnjx_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2012 GenInstrALUFP_rr(0b0010000, 0b010, rd, rs1, rs2);
2015 void Assembler::fmin_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2016 GenInstrALUFP_rr(0b0010100, 0b000, rd, rs1, rs2);
2019 void Assembler::fmax_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2020 GenInstrALUFP_rr(0b0010100, 0b001, rd, rs1, rs2);
2035 void Assembler::feq_s(Register rd, FPURegister rs1, FPURegister rs2) {
2036 GenInstrALUFP_rr(0b1010000, 0b010, rd, rs1, rs2);
2039 void Assembler::flt_s(Register rd, FPURegister rs1, FPURegister rs2) {
2040 GenInstrALUFP_rr(0b1010000, 0b001, rd, rs1, rs2);
2043 void Assembler::fle_s(Register rd, FPURegister rs1, FPURegister rs2) {
2044 GenInstrALUFP_rr(0b1010000, 0b000, rd, rs1, rs2);
2091 void Assembler::fmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2093 GenInstrR4(0b01, MADD, rd, rs1, rs2, rs3, frm);
2096 void Assembler::fmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2098 GenInstrR4(0b01, MSUB, rd, rs1, rs2, rs3, frm);
2101 void Assembler::fnmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2103 GenInstrR4(0b01, NMSUB, rd, rs1, rs2, rs3, frm);
2106 void Assembler::fnmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2108 GenInstrR4(0b01, NMADD, rd, rs1, rs2, rs3, frm);
2111 void Assembler::fadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2113 GenInstrALUFP_rr(0b0000001, frm, rd, rs1, rs2);
2116 void Assembler::fsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2118 GenInstrALUFP_rr(0b0000101, frm, rd, rs1, rs2);
2121 void Assembler::fmul_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2123 GenInstrALUFP_rr(0b0001001, frm, rd, rs1, rs2);
2126 void Assembler::fdiv_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2128 GenInstrALUFP_rr(0b0001101, frm, rd, rs1, rs2);
2135 void Assembler::fsgnj_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2136 GenInstrALUFP_rr(0b0010001, 0b000, rd, rs1, rs2);
2139 void Assembler::fsgnjn_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2140 GenInstrALUFP_rr(0b0010001, 0b001, rd, rs1, rs2);
2143 void Assembler::fsgnjx_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2144 GenInstrALUFP_rr(0b0010001, 0b010, rd, rs1, rs2);
2147 void Assembler::fmin_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2148 GenInstrALUFP_rr(0b0010101, 0b000, rd, rs1, rs2);
2151 void Assembler::fmax_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2152 GenInstrALUFP_rr(0b0010101, 0b001, rd, rs1, rs2);
2163 void Assembler::feq_d(Register rd, FPURegister rs1, FPURegister rs2) {
2164 GenInstrALUFP_rr(0b1010001, 0b010, rd, rs1, rs2);
2167 void Assembler::flt_d(Register rd, FPURegister rs1, FPURegister rs2) {
2168 GenInstrALUFP_rr(0b1010001, 0b001, rd, rs1, rs2);
2171 void Assembler::fle_d(Register rd, FPURegister rs1, FPURegister rs2) {
2172 GenInstrALUFP_rr(0b1010001, 0b000, rd, rs1, rs2);
2288 void Assembler::c_mv(Register rd, Register rs2) {
2289 DCHECK(rd != zero_reg && rs2 != zero_reg);
2290 GenInstrCR(0b1000, C2, rd, rs2);
2301 void Assembler::c_add(Register rd, Register rs2) {
2302 DCHECK(rd != zero_reg && rs2 != zero_reg);
2303 GenInstrCR(0b1001, C2, rd, rs2);
2307 void Assembler::c_sub(Register rd, Register rs2) {
2309 ((rs2.code() & 0b11000) == 0b01000));
2310 GenInstrCA(0b100011, C1, rd, 0b00, rs2);
2313 void Assembler::c_xor(Register rd, Register rs2) {
2315 ((rs2.code() & 0b11000) == 0b01000));
2316 GenInstrCA(0b100011, C1, rd, 0b01, rs2);
2319 void Assembler::c_or(Register rd, Register rs2) {
2321 ((rs2.code() & 0b11000) == 0b01000));
2322 GenInstrCA(0b100011, C1, rd, 0b10, rs2);
2325 void Assembler::c_and(Register rd, Register rs2) {
2327 ((rs2.code() & 0b11000) == 0b01000));
2328 GenInstrCA(0b100011, C1, rd, 0b11, rs2);
2331 void Assembler::c_subw(Register rd, Register rs2) {
2333 ((rs2.code() & 0b11000) == 0b01000));
2334 GenInstrCA(0b100111, C1, rd, 0b00, rs2);
2337 void Assembler::c_addw(Register rd, Register rs2) {
2339 ((rs2.code() & 0b11000) == 0b01000));
2340 GenInstrCA(0b100111, C1, rd, 0b01, rs2);
2343 void Assembler::c_swsp(Register rs2, uint16_t uimm8) {
2346 GenInstrCSS(0b110, C2, rs2, uimm6);
2349 void Assembler::c_sdsp(Register rs2, uint16_t uimm9) {
2352 GenInstrCSS(0b111, C2, rs2, uimm6);
2355 void Assembler::c_fsdsp(FPURegister rs2, uint16_t uimm9) {
2358 GenInstrCSS(0b101, C2, rs2, uimm6);
2390 void Assembler::c_sw(Register rs2, Register rs1, uint16_t uimm7) {
2391 DCHECK(((rs2.code() & 0b11000) == 0b01000) &&
2396 GenInstrCS(0b110, C0, rs2, rs1, uimm5);
2399 void Assembler::c_sd(Register rs2, Register rs1, uint16_t uimm8) {
2400 DCHECK(((rs2.code() & 0b11000) == 0b01000) &&
2404 GenInstrCS(0b111, C0, rs2, rs1, uimm5);
2407 void Assembler::c_fsd(FPURegister rs2, Register rs1, uint16_t uimm8) {
2408 DCHECK(((rs2.code() & 0b11000) == 0b01000) &&
2412 GenInstrCS(0b101, C0, rs2, rs1, uimm5);
2888 void Assembler::vsetvl(Register rd, Register rs1, Register rs2) {
2891 ((rs2.code() & 0x1F) << kRvvRs2Shift) | 0x40 << 25;
2919 void Assembler::vls(VRegister vd, Register rs1, Register rs2, VSew vsew,
2922 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b000);
2935 void Assembler::vss(VRegister vs3, Register rs1, Register rs2, VSew vsew,
2938 GenInstrV(STORE_FP, width, vs3, rs1, rs2, mask, 0b10, 0, 0b000);
3029 void Assembler::vlsseg2(VRegister vd, Register rs1, Register rs2, VSew vsew,
3032 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b001);
3034 void Assembler::vlsseg3(VRegister vd, Register rs1, Register rs2, VSew vsew,
3037 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b010);
3039 void Assembler::vlsseg4(VRegister vd, Register rs1, Register rs2, VSew vsew,
3042 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b011);
3044 void Assembler::vlsseg5(VRegister vd, Register rs1, Register rs2, VSew vsew,
3047 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b100);
3049 void Assembler::vlsseg6(VRegister vd, Register rs1, Register rs2, VSew vsew,
3052 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b101);
3054 void Assembler::vlsseg7(VRegister vd, Register rs1, Register rs2, VSew vsew,
3057 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b110);
3059 void Assembler::vlsseg8(VRegister vd, Register rs1, Register rs2, VSew vsew,
3062 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b111);
3064 void Assembler::vssseg2(VRegister vd, Register rs1, Register rs2, VSew vsew,
3067 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b001);
3069 void Assembler::vssseg3(VRegister vd, Register rs1, Register rs2, VSew vsew,
3072 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b010);
3074 void Assembler::vssseg4(VRegister vd, Register rs1, Register rs2, VSew vsew,
3077 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b011);
3079 void Assembler::vssseg5(VRegister vd, Register rs1, Register rs2, VSew vsew,
3082 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b100);
3084 void Assembler::vssseg6(VRegister vd, Register rs1, Register rs2, VSew vsew,
3087 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b101);
3089 void Assembler::vssseg7(VRegister vd, Register rs1, Register rs2, VSew vsew,
3092 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b110);
3094 void Assembler::vssseg8(VRegister vd, Register rs1, Register rs2, VSew vsew,
3097 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b111);
3100 void Assembler::vlxseg2(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3103 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b001);
3105 void Assembler::vlxseg3(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3108 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b010);
3110 void Assembler::vlxseg4(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3113 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b011);
3115 void Assembler::vlxseg5(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3118 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b100);
3120 void Assembler::vlxseg6(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3123 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b101);
3125 void Assembler::vlxseg7(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3128 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b110);
3130 void Assembler::vlxseg8(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3133 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b111);
3135 void Assembler::vsxseg2(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3138 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b001);
3140 void Assembler::vsxseg3(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3143 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b010);
3145 void Assembler::vsxseg4(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3148 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b011);
3150 void Assembler::vsxseg5(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3153 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b100);
3155 void Assembler::vsxseg6(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3158 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b101);
3160 void Assembler::vsxseg7(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3163 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b110);
3165 void Assembler::vsxseg8(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3168 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b111);
3196 void Assembler::sfence_vma(Register rs1, Register rs2) {
3197 GenInstrR(0b0001001, 0b000, SYSTEM, ToRegister(0), rs1, rs2);