Lines Matching defs:rs1
730 // | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode |
818 Register rd, Register rs1, Register rs2) {
820 rs1.is_valid() && rs2.is_valid());
822 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
828 FPURegister rd, FPURegister rs1, FPURegister rs2) {
830 rs1.is_valid() && rs2.is_valid());
832 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
838 Register rd, FPURegister rs1, Register rs2) {
840 rs1.is_valid() && rs2.is_valid());
842 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
848 FPURegister rd, Register rs1, Register rs2) {
850 rs1.is_valid() && rs2.is_valid());
852 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
858 FPURegister rd, FPURegister rs1, Register rs2) {
860 rs1.is_valid() && rs2.is_valid());
862 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
868 Register rd, FPURegister rs1, FPURegister rs2) {
870 rs1.is_valid() && rs2.is_valid());
872 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
878 Register rs1, Register rs2, Register rs3,
880 DCHECK(is_uint2(funct2) && rd.is_valid() && rs1.is_valid() &&
883 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
889 FPURegister rs1, FPURegister rs2, FPURegister rs3,
891 DCHECK(is_uint2(funct2) && rd.is_valid() && rs1.is_valid() &&
894 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
900 uint8_t funct3, Register rd, Register rs1,
903 rs1.is_valid() && rs2.is_valid());
905 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
911 Register rs1, Register rs2, RoundingMode frm) {
912 DCHECK(rd.is_valid() && rs1.is_valid() && rs2.is_valid() && is_uint3(frm));
914 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
920 Register rs1, int16_t imm12) {
921 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
924 (rs1.code() << kRs1Shift) | (imm12 << kImm12Shift);
929 Register rs1, int16_t imm12) {
930 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
933 (rs1.code() << kRs1Shift) | (imm12 << kImm12Shift);
938 Register rd, Register rs1, uint8_t shamt) {
939 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
942 (rs1.code() << kRs1Shift) | (shamt << kShamtShift) |
948 Register rd, Register rs1, uint8_t shamt) {
949 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
952 (rs1.code() << kRs1Shift) | (shamt << kShamtWShift) |
957 void Assembler::GenInstrS(uint8_t funct3, Opcode opcode, Register rs1,
959 DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() &&
962 (funct3 << kFunct3Shift) | (rs1.code() << kRs1Shift) |
968 void Assembler::GenInstrS(uint8_t funct3, Opcode opcode, Register rs1,
970 DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() &&
973 (funct3 << kFunct3Shift) | (rs1.code() << kRs1Shift) |
979 void Assembler::GenInstrB(uint8_t funct3, Opcode opcode, Register rs1,
981 DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() &&
985 (funct3 << kFunct3Shift) | (rs1.code() << kRs1Shift) |
1079 Register rs1, uint8_t uimm5) {
1080 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
1085 ((rs1.code() & 0x7) << kRvcRs1sShift);
1090 Register rs1, uint8_t uimm5) {
1091 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
1096 ((rs1.code() & 0x7) << kRvcRs1sShift);
1106 Register rs1, uint8_t uimm5) {
1107 DCHECK(is_uint3(funct3) && rs2.is_valid() && rs1.is_valid() &&
1112 ((rs1.code() & 0x7) << kRvcRs1sShift);
1117 Register rs1, uint8_t uimm5) {
1118 DCHECK(is_uint3(funct3) && rs2.is_valid() && rs1.is_valid() &&
1123 ((rs1.code() & 0x7) << kRvcRs1sShift);
1127 void Assembler::GenInstrCB(uint8_t funct3, Opcode opcode, Register rs1,
1131 ((rs1.code() & 0x7) << kRvcRs1sShift) |
1137 Register rs1, int8_t imm6) {
1140 ((rs1.code() & 0x7) << kRvcRs1sShift) |
1189 Register rs1, VRegister vs2, MaskType mask) {
1193 ((rs1.code() & 0x1F) << kRvvRs1Shift) |
1210 void Assembler::GenInstrV(uint8_t funct6, Register rd, Register rs1,
1214 ((rs1.code() & 0x1F) << kRvvRs1Shift) |
1231 Register rs1, uint8_t umop, MaskType mask,
1236 ((rs1.code() << kRvvRs1Shift) & kRvvRs1Mask) |
1245 Register rs1, Register rs2, MaskType mask,
1250 ((rs1.code() << kRvvRs1Shift) & kRvvRs1Mask) |
1260 Register rs1, VRegister vs2, MaskType mask,
1265 ((rs1.code() << kRvvRs1Shift) & kRvvRs1Mask) |
1285 void Assembler::GenInstrBranchCC_rri(uint8_t funct3, Register rs1, Register rs2,
1287 GenInstrB(funct3, BRANCH, rs1, rs2, imm13);
1290 void Assembler::GenInstrLoad_ri(uint8_t funct3, Register rd, Register rs1,
1292 GenInstrI(funct3, LOAD, rd, rs1, imm12);
1295 void Assembler::GenInstrStore_rri(uint8_t funct3, Register rs1, Register rs2,
1297 GenInstrS(funct3, STORE, rs1, rs2, imm12);
1300 void Assembler::GenInstrALU_ri(uint8_t funct3, Register rd, Register rs1,
1302 GenInstrI(funct3, OP_IMM, rd, rs1, imm12);
1306 Register rs1, uint8_t shamt) {
1308 GenInstrI(funct3, OP_IMM, rd, rs1, (arithshift << 10) | shamt);
1312 Register rs1, Register rs2) {
1313 GenInstrR(funct7, funct3, OP, rd, rs1, rs2);
1317 ControlStatusReg csr, Register rs1) {
1318 GenInstrI(funct3, SYSTEM, rd, rs1, csr);
1327 Register rs1, uint8_t shamt) {
1328 GenInstrIShiftW(arithshift, funct3, OP_IMM_32, rd, rs1, shamt);
1332 Register rs1, Register rs2) {
1333 GenInstrR(funct7, funct3, OP_32, rd, rs1, rs2);
1336 void Assembler::GenInstrPriv(uint8_t funct7, Register rs1, Register rs2) {
1337 GenInstrR(funct7, 0b000, SYSTEM, ToRegister(0), rs1, rs2);
1340 void Assembler::GenInstrLoadFP_ri(uint8_t funct3, FPURegister rd, Register rs1,
1342 GenInstrI(funct3, LOAD_FP, rd, rs1, imm12);
1345 void Assembler::GenInstrStoreFP_rri(uint8_t funct3, Register rs1,
1347 GenInstrS(funct3, STORE_FP, rs1, rs2, imm12);
1351 FPURegister rs1, FPURegister rs2) {
1352 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1356 Register rs1, Register rs2) {
1357 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1361 FPURegister rs1, Register rs2) {
1362 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1366 FPURegister rs1, Register rs2) {
1367 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1371 FPURegister rs1, FPURegister rs2) {
1372 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1528 void Assembler::jalr(Register rd, Register rs1, int16_t imm12) {
1529 GenInstrI(0b000, JALR, rd, rs1, imm12);
1535 void Assembler::beq(Register rs1, Register rs2, int16_t imm13) {
1536 GenInstrBranchCC_rri(0b000, rs1, rs2, imm13);
1539 void Assembler::bne(Register rs1, Register rs2, int16_t imm13) {
1540 GenInstrBranchCC_rri(0b001, rs1, rs2, imm13);
1543 void Assembler::blt(Register rs1, Register rs2, int16_t imm13) {
1544 GenInstrBranchCC_rri(0b100, rs1, rs2, imm13);
1547 void Assembler::bge(Register rs1, Register rs2, int16_t imm13) {
1548 GenInstrBranchCC_rri(0b101, rs1, rs2, imm13);
1551 void Assembler::bltu(Register rs1, Register rs2, int16_t imm13) {
1552 GenInstrBranchCC_rri(0b110, rs1, rs2, imm13);
1555 void Assembler::bgeu(Register rs1, Register rs2, int16_t imm13) {
1556 GenInstrBranchCC_rri(0b111, rs1, rs2, imm13);
1561 void Assembler::lb(Register rd, Register rs1, int16_t imm12) {
1562 GenInstrLoad_ri(0b000, rd, rs1, imm12);
1565 void Assembler::lh(Register rd, Register rs1, int16_t imm12) {
1566 GenInstrLoad_ri(0b001, rd, rs1, imm12);
1569 void Assembler::lw(Register rd, Register rs1, int16_t imm12) {
1570 GenInstrLoad_ri(0b010, rd, rs1, imm12);
1573 void Assembler::lbu(Register rd, Register rs1, int16_t imm12) {
1574 GenInstrLoad_ri(0b100, rd, rs1, imm12);
1577 void Assembler::lhu(Register rd, Register rs1, int16_t imm12) {
1578 GenInstrLoad_ri(0b101, rd, rs1, imm12);
1597 void Assembler::addi(Register rd, Register rs1, int16_t imm12) {
1598 GenInstrALU_ri(0b000, rd, rs1, imm12);
1601 void Assembler::slti(Register rd, Register rs1, int16_t imm12) {
1602 GenInstrALU_ri(0b010, rd, rs1, imm12);
1605 void Assembler::sltiu(Register rd, Register rs1, int16_t imm12) {
1606 GenInstrALU_ri(0b011, rd, rs1, imm12);
1609 void Assembler::xori(Register rd, Register rs1, int16_t imm12) {
1610 GenInstrALU_ri(0b100, rd, rs1, imm12);
1613 void Assembler::ori(Register rd, Register rs1, int16_t imm12) {
1614 GenInstrALU_ri(0b110, rd, rs1, imm12);
1617 void Assembler::andi(Register rd, Register rs1, int16_t imm12) {
1618 GenInstrALU_ri(0b111, rd, rs1, imm12);
1621 void Assembler::slli(Register rd, Register rs1, uint8_t shamt) {
1622 GenInstrShift_ri(0, 0b001, rd, rs1, shamt & 0x3f);
1625 void Assembler::srli(Register rd, Register rs1, uint8_t shamt) {
1626 GenInstrShift_ri(0, 0b101, rd, rs1, shamt & 0x3f);
1629 void Assembler::srai(Register rd, Register rs1, uint8_t shamt) {
1630 GenInstrShift_ri(1, 0b101, rd, rs1, shamt & 0x3f);
1635 void Assembler::add(Register rd, Register rs1, Register rs2) {
1636 GenInstrALU_rr(0b0000000, 0b000, rd, rs1, rs2);
1639 void Assembler::sub(Register rd, Register rs1, Register rs2) {
1640 GenInstrALU_rr(0b0100000, 0b000, rd, rs1, rs2);
1643 void Assembler::sll(Register rd, Register rs1, Register rs2) {
1644 GenInstrALU_rr(0b0000000, 0b001, rd, rs1, rs2);
1647 void Assembler::slt(Register rd, Register rs1, Register rs2) {
1648 GenInstrALU_rr(0b0000000, 0b010, rd, rs1, rs2);
1651 void Assembler::sltu(Register rd, Register rs1, Register rs2) {
1652 GenInstrALU_rr(0b0000000, 0b011, rd, rs1, rs2);
1655 void Assembler::xor_(Register rd, Register rs1, Register rs2) {
1656 GenInstrALU_rr(0b0000000, 0b100, rd, rs1, rs2);
1659 void Assembler::srl(Register rd, Register rs1, Register rs2) {
1660 GenInstrALU_rr(0b0000000, 0b101, rd, rs1, rs2);
1663 void Assembler::sra(Register rd, Register rs1, Register rs2) {
1664 GenInstrALU_rr(0b0100000, 0b101, rd, rs1, rs2);
1667 void Assembler::or_(Register rd, Register rs1, Register rs2) {
1668 GenInstrALU_rr(0b0000000, 0b110, rd, rs1, rs2);
1671 void Assembler::and_(Register rd, Register rs1, Register rs2) {
1672 GenInstrALU_rr(0b0000000, 0b111, rd, rs1, rs2);
1707 void Assembler::csrrw(Register rd, ControlStatusReg csr, Register rs1) {
1708 GenInstrCSR_ir(0b001, rd, csr, rs1);
1711 void Assembler::csrrs(Register rd, ControlStatusReg csr, Register rs1) {
1712 GenInstrCSR_ir(0b010, rd, csr, rs1);
1715 void Assembler::csrrc(Register rd, ControlStatusReg csr, Register rs1) {
1716 GenInstrCSR_ir(0b011, rd, csr, rs1);
1733 void Assembler::lwu(Register rd, Register rs1, int16_t imm12) {
1734 GenInstrLoad_ri(0b110, rd, rs1, imm12);
1737 void Assembler::ld(Register rd, Register rs1, int16_t imm12) {
1738 GenInstrLoad_ri(0b011, rd, rs1, imm12);
1745 void Assembler::addiw(Register rd, Register rs1, int16_t imm12) {
1746 GenInstrI(0b000, OP_IMM_32, rd, rs1, imm12);
1749 void Assembler::slliw(Register rd, Register rs1, uint8_t shamt) {
1750 GenInstrShiftW_ri(0, 0b001, rd, rs1, shamt & 0x1f);
1753 void Assembler::srliw(Register rd, Register rs1, uint8_t shamt) {
1754 GenInstrShiftW_ri(0, 0b101, rd, rs1, shamt & 0x1f);
1757 void Assembler::sraiw(Register rd, Register rs1, uint8_t shamt) {
1758 GenInstrShiftW_ri(1, 0b101, rd, rs1, shamt & 0x1f);
1761 void Assembler::addw(Register rd, Register rs1, Register rs2) {
1762 GenInstrALUW_rr(0b0000000, 0b000, rd, rs1, rs2);
1765 void Assembler::subw(Register rd, Register rs1, Register rs2) {
1766 GenInstrALUW_rr(0b0100000, 0b000, rd, rs1, rs2);
1769 void Assembler::sllw(Register rd, Register rs1, Register rs2) {
1770 GenInstrALUW_rr(0b0000000, 0b001, rd, rs1, rs2);
1773 void Assembler::srlw(Register rd, Register rs1, Register rs2) {
1774 GenInstrALUW_rr(0b0000000, 0b101, rd, rs1, rs2);
1777 void Assembler::sraw(Register rd, Register rs1, Register rs2) {
1778 GenInstrALUW_rr(0b0100000, 0b101, rd, rs1, rs2);
1783 void Assembler::mul(Register rd, Register rs1, Register rs2) {
1784 GenInstrALU_rr(0b0000001, 0b000, rd, rs1, rs2);
1787 void Assembler::mulh(Register rd, Register rs1, Register rs2) {
1788 GenInstrALU_rr(0b0000001, 0b001, rd, rs1, rs2);
1791 void Assembler::mulhsu(Register rd, Register rs1, Register rs2) {
1792 GenInstrALU_rr(0b0000001, 0b010, rd, rs1, rs2);
1795 void Assembler::mulhu(Register rd, Register rs1, Register rs2) {
1796 GenInstrALU_rr(0b0000001, 0b011, rd, rs1, rs2);
1799 void Assembler::div(Register rd, Register rs1, Register rs2) {
1800 GenInstrALU_rr(0b0000001, 0b100, rd, rs1, rs2);
1803 void Assembler::divu(Register rd, Register rs1, Register rs2) {
1804 GenInstrALU_rr(0b0000001, 0b101, rd, rs1, rs2);
1807 void Assembler::rem(Register rd, Register rs1, Register rs2) {
1808 GenInstrALU_rr(0b0000001, 0b110, rd, rs1, rs2);
1811 void Assembler::remu(Register rd, Register rs1, Register rs2) {
1812 GenInstrALU_rr(0b0000001, 0b111, rd, rs1, rs2);
1817 void Assembler::mulw(Register rd, Register rs1, Register rs2) {
1818 GenInstrALUW_rr(0b0000001, 0b000, rd, rs1, rs2);
1821 void Assembler::divw(Register rd, Register rs1, Register rs2) {
1822 GenInstrALUW_rr(0b0000001, 0b100, rd, rs1, rs2);
1825 void Assembler::divuw(Register rd, Register rs1, Register rs2) {
1826 GenInstrALUW_rr(0b0000001, 0b101, rd, rs1, rs2);
1829 void Assembler::remw(Register rd, Register rs1, Register rs2) {
1830 GenInstrALUW_rr(0b0000001, 0b110, rd, rs1, rs2);
1833 void Assembler::remuw(Register rd, Register rs1, Register rs2) {
1834 GenInstrALUW_rr(0b0000001, 0b111, rd, rs1, rs2);
1839 void Assembler::lr_w(bool aq, bool rl, Register rd, Register rs1) {
1840 GenInstrRAtomic(0b00010, aq, rl, 0b010, rd, rs1, zero_reg);
1843 void Assembler::sc_w(bool aq, bool rl, Register rd, Register rs1,
1845 GenInstrRAtomic(0b00011, aq, rl, 0b010, rd, rs1, rs2);
1848 void Assembler::amoswap_w(bool aq, bool rl, Register rd, Register rs1,
1850 GenInstrRAtomic(0b00001, aq, rl, 0b010, rd, rs1, rs2);
1853 void Assembler::amoadd_w(bool aq, bool rl, Register rd, Register rs1,
1855 GenInstrRAtomic(0b00000, aq, rl, 0b010, rd, rs1, rs2);
1858 void Assembler::amoxor_w(bool aq, bool rl, Register rd, Register rs1,
1860 GenInstrRAtomic(0b00100, aq, rl, 0b010, rd, rs1, rs2);
1863 void Assembler::amoand_w(bool aq, bool rl, Register rd, Register rs1,
1865 GenInstrRAtomic(0b01100, aq, rl, 0b010, rd, rs1, rs2);
1868 void Assembler::amoor_w(bool aq, bool rl, Register rd, Register rs1,
1870 GenInstrRAtomic(0b01000, aq, rl, 0b010, rd, rs1, rs2);
1873 void Assembler::amomin_w(bool aq, bool rl, Register rd, Register rs1,
1875 GenInstrRAtomic(0b10000, aq, rl, 0b010, rd, rs1, rs2);
1878 void Assembler::amomax_w(bool aq, bool rl, Register rd, Register rs1,
1880 GenInstrRAtomic(0b10100, aq, rl, 0b010, rd, rs1, rs2);
1883 void Assembler::amominu_w(bool aq, bool rl, Register rd, Register rs1,
1885 GenInstrRAtomic(0b11000, aq, rl, 0b010, rd, rs1, rs2);
1888 void Assembler::amomaxu_w(bool aq, bool rl, Register rd, Register rs1,
1890 GenInstrRAtomic(0b11100, aq, rl, 0b010, rd, rs1, rs2);
1895 void Assembler::lr_d(bool aq, bool rl, Register rd, Register rs1) {
1896 GenInstrRAtomic(0b00010, aq, rl, 0b011, rd, rs1, zero_reg);
1899 void Assembler::sc_d(bool aq, bool rl, Register rd, Register rs1,
1901 GenInstrRAtomic(0b00011, aq, rl, 0b011, rd, rs1, rs2);
1904 void Assembler::amoswap_d(bool aq, bool rl, Register rd, Register rs1,
1906 GenInstrRAtomic(0b00001, aq, rl, 0b011, rd, rs1, rs2);
1909 void Assembler::amoadd_d(bool aq, bool rl, Register rd, Register rs1,
1911 GenInstrRAtomic(0b00000, aq, rl, 0b011, rd, rs1, rs2);
1914 void Assembler::amoxor_d(bool aq, bool rl, Register rd, Register rs1,
1916 GenInstrRAtomic(0b00100, aq, rl, 0b011, rd, rs1, rs2);
1919 void Assembler::amoand_d(bool aq, bool rl, Register rd, Register rs1,
1921 GenInstrRAtomic(0b01100, aq, rl, 0b011, rd, rs1, rs2);
1924 void Assembler::amoor_d(bool aq, bool rl, Register rd, Register rs1,
1926 GenInstrRAtomic(0b01000, aq, rl, 0b011, rd, rs1, rs2);
1929 void Assembler::amomin_d(bool aq, bool rl, Register rd, Register rs1,
1931 GenInstrRAtomic(0b10000, aq, rl, 0b011, rd, rs1, rs2);
1934 void Assembler::amomax_d(bool aq, bool rl, Register rd, Register rs1,
1936 GenInstrRAtomic(0b10100, aq, rl, 0b011, rd, rs1, rs2);
1939 void Assembler::amominu_d(bool aq, bool rl, Register rd, Register rs1,
1941 GenInstrRAtomic(0b11000, aq, rl, 0b011, rd, rs1, rs2);
1944 void Assembler::amomaxu_d(bool aq, bool rl, Register rd, Register rs1,
1946 GenInstrRAtomic(0b11100, aq, rl, 0b011, rd, rs1, rs2);
1951 void Assembler::flw(FPURegister rd, Register rs1, int16_t imm12) {
1952 GenInstrLoadFP_ri(0b010, rd, rs1, imm12);
1959 void Assembler::fmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1961 GenInstrR4(0b00, MADD, rd, rs1, rs2, rs3, frm);
1964 void Assembler::fmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1966 GenInstrR4(0b00, MSUB, rd, rs1, rs2, rs3, frm);
1969 void Assembler::fnmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1971 GenInstrR4(0b00, NMSUB, rd, rs1, rs2, rs3, frm);
1974 void Assembler::fnmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1976 GenInstrR4(0b00, NMADD, rd, rs1, rs2, rs3, frm);
1979 void Assembler::fadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1981 GenInstrALUFP_rr(0b0000000, frm, rd, rs1, rs2);
1984 void Assembler::fsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1986 GenInstrALUFP_rr(0b0000100, frm, rd, rs1, rs2);
1989 void Assembler::fmul_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1991 GenInstrALUFP_rr(0b0001000, frm, rd, rs1, rs2);
1994 void Assembler::fdiv_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
1996 GenInstrALUFP_rr(0b0001100, frm, rd, rs1, rs2);
1999 void Assembler::fsqrt_s(FPURegister rd, FPURegister rs1, RoundingMode frm) {
2000 GenInstrALUFP_rr(0b0101100, frm, rd, rs1, zero_reg);
2003 void Assembler::fsgnj_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2004 GenInstrALUFP_rr(0b0010000, 0b000, rd, rs1, rs2);
2007 void Assembler::fsgnjn_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2008 GenInstrALUFP_rr(0b0010000, 0b001, rd, rs1, rs2);
2011 void Assembler::fsgnjx_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2012 GenInstrALUFP_rr(0b0010000, 0b010, rd, rs1, rs2);
2015 void Assembler::fmin_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2016 GenInstrALUFP_rr(0b0010100, 0b000, rd, rs1, rs2);
2019 void Assembler::fmax_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2020 GenInstrALUFP_rr(0b0010100, 0b001, rd, rs1, rs2);
2023 void Assembler::fcvt_w_s(Register rd, FPURegister rs1, RoundingMode frm) {
2024 GenInstrALUFP_rr(0b1100000, frm, rd, rs1, zero_reg);
2027 void Assembler::fcvt_wu_s(Register rd, FPURegister rs1, RoundingMode frm) {
2028 GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(1));
2031 void Assembler::fmv_x_w(Register rd, FPURegister rs1) {
2032 GenInstrALUFP_rr(0b1110000, 0b000, rd, rs1, zero_reg);
2035 void Assembler::feq_s(Register rd, FPURegister rs1, FPURegister rs2) {
2036 GenInstrALUFP_rr(0b1010000, 0b010, rd, rs1, rs2);
2039 void Assembler::flt_s(Register rd, FPURegister rs1, FPURegister rs2) {
2040 GenInstrALUFP_rr(0b1010000, 0b001, rd, rs1, rs2);
2043 void Assembler::fle_s(Register rd, FPURegister rs1, FPURegister rs2) {
2044 GenInstrALUFP_rr(0b1010000, 0b000, rd, rs1, rs2);
2047 void Assembler::fclass_s(Register rd, FPURegister rs1) {
2048 GenInstrALUFP_rr(0b1110000, 0b001, rd, rs1, zero_reg);
2051 void Assembler::fcvt_s_w(FPURegister rd, Register rs1, RoundingMode frm) {
2052 GenInstrALUFP_rr(0b1101000, frm, rd, rs1, zero_reg);
2055 void Assembler::fcvt_s_wu(FPURegister rd, Register rs1, RoundingMode frm) {
2056 GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(1));
2059 void Assembler::fmv_w_x(FPURegister rd, Register rs1) {
2060 GenInstrALUFP_rr(0b1111000, 0b000, rd, rs1, zero_reg);
2065 void Assembler::fcvt_l_s(Register rd, FPURegister rs1, RoundingMode frm) {
2066 GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(2));
2069 void Assembler::fcvt_lu_s(Register rd, FPURegister rs1, RoundingMode frm) {
2070 GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(3));
2073 void Assembler::fcvt_s_l(FPURegister rd, Register rs1, RoundingMode frm) {
2074 GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(2));
2077 void Assembler::fcvt_s_lu(FPURegister rd, Register rs1, RoundingMode frm) {
2078 GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(3));
2083 void Assembler::fld(FPURegister rd, Register rs1, int16_t imm12) {
2084 GenInstrLoadFP_ri(0b011, rd, rs1, imm12);
2091 void Assembler::fmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2093 GenInstrR4(0b01, MADD, rd, rs1, rs2, rs3, frm);
2096 void Assembler::fmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2098 GenInstrR4(0b01, MSUB, rd, rs1, rs2, rs3, frm);
2101 void Assembler::fnmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2103 GenInstrR4(0b01, NMSUB, rd, rs1, rs2, rs3, frm);
2106 void Assembler::fnmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2108 GenInstrR4(0b01, NMADD, rd, rs1, rs2, rs3, frm);
2111 void Assembler::fadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2113 GenInstrALUFP_rr(0b0000001, frm, rd, rs1, rs2);
2116 void Assembler::fsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2118 GenInstrALUFP_rr(0b0000101, frm, rd, rs1, rs2);
2121 void Assembler::fmul_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2123 GenInstrALUFP_rr(0b0001001, frm, rd, rs1, rs2);
2126 void Assembler::fdiv_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
2128 GenInstrALUFP_rr(0b0001101, frm, rd, rs1, rs2);
2131 void Assembler::fsqrt_d(FPURegister rd, FPURegister rs1, RoundingMode frm) {
2132 GenInstrALUFP_rr(0b0101101, frm, rd, rs1, zero_reg);
2135 void Assembler::fsgnj_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2136 GenInstrALUFP_rr(0b0010001, 0b000, rd, rs1, rs2);
2139 void Assembler::fsgnjn_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2140 GenInstrALUFP_rr(0b0010001, 0b001, rd, rs1, rs2);
2143 void Assembler::fsgnjx_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2144 GenInstrALUFP_rr(0b0010001, 0b010, rd, rs1, rs2);
2147 void Assembler::fmin_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2148 GenInstrALUFP_rr(0b0010101, 0b000, rd, rs1, rs2);
2151 void Assembler::fmax_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
2152 GenInstrALUFP_rr(0b0010101, 0b001, rd, rs1, rs2);
2155 void Assembler::fcvt_s_d(FPURegister rd, FPURegister rs1, RoundingMode frm) {
2156 GenInstrALUFP_rr(0b0100000, frm, rd, rs1, ToRegister(1));
2159 void Assembler::fcvt_d_s(FPURegister rd, FPURegister rs1, RoundingMode frm) {
2160 GenInstrALUFP_rr(0b0100001, frm, rd, rs1, zero_reg);
2163 void Assembler::feq_d(Register rd, FPURegister rs1, FPURegister rs2) {
2164 GenInstrALUFP_rr(0b1010001, 0b010, rd, rs1, rs2);
2167 void Assembler::flt_d(Register rd, FPURegister rs1, FPURegister rs2) {
2168 GenInstrALUFP_rr(0b1010001, 0b001, rd, rs1, rs2);
2171 void Assembler::fle_d(Register rd, FPURegister rs1, FPURegister rs2) {
2172 GenInstrALUFP_rr(0b1010001, 0b000, rd, rs1, rs2);
2175 void Assembler::fclass_d(Register rd, FPURegister rs1) {
2176 GenInstrALUFP_rr(0b1110001, 0b001, rd, rs1, zero_reg);
2179 void Assembler::fcvt_w_d(Register rd, FPURegister rs1, RoundingMode frm) {
2180 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, zero_reg);
2183 void Assembler::fcvt_wu_d(Register rd, FPURegister rs1, RoundingMode frm) {
2184 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(1));
2187 void Assembler::fcvt_d_w(FPURegister rd, Register rs1, RoundingMode frm) {
2188 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, zero_reg);
2191 void Assembler::fcvt_d_wu(FPURegister rd, Register rs1, RoundingMode frm) {
2192 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(1));
2197 void Assembler::fcvt_l_d(Register rd, FPURegister rs1, RoundingMode frm) {
2198 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(2));
2201 void Assembler::fcvt_lu_d(Register rd, FPURegister rs1, RoundingMode frm) {
2202 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(3));
2205 void Assembler::fmv_x_d(Register rd, FPURegister rs1) {
2206 GenInstrALUFP_rr(0b1110001, 0b000, rd, rs1, zero_reg);
2209 void Assembler::fcvt_d_l(FPURegister rd, Register rs1, RoundingMode frm) {
2210 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(2));
2213 void Assembler::fcvt_d_lu(FPURegister rd, Register rs1, RoundingMode frm) {
2214 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(3));
2217 void Assembler::fmv_d_x(FPURegister rd, Register rs1) {
2218 GenInstrALUFP_rr(0b1111001, 0b000, rd, rs1, zero_reg);
2282 void Assembler::c_jr(Register rs1) {
2283 DCHECK(rs1 != zero_reg);
2284 GenInstrCR(0b1000, C2, rs1, zero_reg);
2295 void Assembler::c_jalr(Register rs1) {
2296 DCHECK(rs1 != zero_reg);
2297 GenInstrCR(0b1001, C2, rs1, zero_reg);
2363 void Assembler::c_lw(Register rd, Register rs1, uint16_t uimm7) {
2365 ((rs1.code() & 0b11000) == 0b01000) && is_uint7(uimm7) &&
2369 GenInstrCL(0b010, C0, rd, rs1, uimm5);
2372 void Assembler::c_ld(Register rd, Register rs1, uint16_t uimm8) {
2374 ((rs1.code() & 0b11000) == 0b01000) && is_uint8(uimm8) &&
2377 GenInstrCL(0b011, C0, rd, rs1, uimm5);
2380 void Assembler::c_fld(FPURegister rd, Register rs1, uint16_t uimm8) {
2382 ((rs1.code() & 0b11000) == 0b01000) && is_uint8(uimm8) &&
2385 GenInstrCL(0b001, C0, rd, rs1, uimm5);
2390 void Assembler::c_sw(Register rs2, Register rs1, uint16_t uimm7) {
2392 ((rs1.code() & 0b11000) == 0b01000) && is_uint7(uimm7) &&
2396 GenInstrCS(0b110, C0, rs2, rs1, uimm5);
2399 void Assembler::c_sd(Register rs2, Register rs1, uint16_t uimm8) {
2401 ((rs1.code() & 0b11000) == 0b01000) && is_uint8(uimm8) &&
2404 GenInstrCS(0b111, C0, rs2, rs1, uimm5);
2407 void Assembler::c_fsd(FPURegister rs2, Register rs1, uint16_t uimm8) {
2409 ((rs1.code() & 0b11000) == 0b01000) && is_uint8(uimm8) &&
2412 GenInstrCS(0b101, C0, rs2, rs1, uimm5);
2429 void Assembler::c_bnez(Register rs1, int16_t imm9) {
2430 DCHECK(((rs1.code() & 0b11000) == 0b01000) && is_int9(imm9));
2433 GenInstrCB(0b111, C1, rs1, uimm8);
2436 void Assembler::c_beqz(Register rs1, int16_t imm9) {
2437 DCHECK(((rs1.code() & 0b11000) == 0b01000) && is_int9(imm9));
2440 GenInstrCB(0b110, C1, rs1, uimm8);
2443 void Assembler::c_srli(Register rs1, int8_t shamt6) {
2444 DCHECK(((rs1.code() & 0b11000) == 0b01000) && is_int6(shamt6));
2445 GenInstrCBA(0b100, 0b00, C1, rs1, shamt6);
2448 void Assembler::c_srai(Register rs1, int8_t shamt6) {
2449 DCHECK(((rs1.code() & 0b11000) == 0b01000) && is_int6(shamt6));
2450 GenInstrCBA(0b100, 0b01, C1, rs1, shamt6);
2453 void Assembler::c_andi(Register rs1, int8_t imm6) {
2454 DCHECK(((rs1.code() & 0b11000) == 0b01000) && is_int6(imm6));
2455 GenInstrCBA(0b100, 0b10, C1, rs1, imm6);
2500 void Assembler::vmv_vx(VRegister vd, Register rs1) {
2501 GenInstrV(VMV_FUNCT6, OP_IVX, vd, rs1, v0, NoMask);
2512 void Assembler::vmv_sx(VRegister vd, Register rs1) {
2513 GenInstrV(VRXUNARY0_FUNCT6, OP_MVX, vd, rs1, v0, NoMask);
2520 void Assembler::vmerge_vx(VRegister vd, Register rs1, VRegister vs2) {
2521 GenInstrV(VMV_FUNCT6, OP_IVX, vd, rs1, vs2, Mask);
2532 void Assembler::vadc_vx(VRegister vd, Register rs1, VRegister vs2) {
2533 GenInstrV(VADC_FUNCT6, OP_IVX, vd, rs1, vs2, Mask);
2544 void Assembler::vmadc_vx(VRegister vd, Register rs1, VRegister vs2) {
2545 GenInstrV(VMADC_FUNCT6, OP_IVX, vd, rs1, vs2, Mask);
2565 void Assembler::vrgather_vx(VRegister vd, VRegister vs2, Register rs1,
2568 GenInstrV(VRGATHER_FUNCT6, OP_IVX, vd, rs1, vs2, mask);
2571 void Assembler::vwaddu_wx(VRegister vd, VRegister vs2, Register rs1,
2573 GenInstrV(VWADDUW_FUNCT6, OP_MVX, vd, rs1, vs2, mask);
2605 void Assembler::name##_vx(VRegister vd, VRegister vs2, Register rs1, \
2607 GenInstrV(funct6, OP_IVX, vd, rs1, vs2, mask); \
2622 // void GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, Register rs1,
2625 void Assembler::name##_vx(VRegister vd, VRegister vs2, Register rs1, \
2627 GenInstrV(funct6, OP_MVX, vd, rs1, vs2, mask); \
2869 void Assembler::vsetvli(Register rd, Register rs1, VSew vsew, Vlmul vlmul,
2873 ((rs1.code() & 0x1F) << kRvvRs1Shift) |
2888 void Assembler::vsetvl(Register rd, Register rs1, Register rs2) {
2890 ((rs1.code() & 0x1F) << kRvvRs1Shift) |
2914 void Assembler::vl(VRegister vd, Register rs1, uint8_t lumop, VSew vsew,
2917 GenInstrV(LOAD_FP, width, vd, rs1, lumop, mask, 0b00, 0, 0b000);
2919 void Assembler::vls(VRegister vd, Register rs1, Register rs2, VSew vsew,
2922 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b000);
2924 void Assembler::vlx(VRegister vd, Register rs1, VRegister vs2, VSew vsew,
2927 GenInstrV(LOAD_FP, width, vd, rs1, vs2, mask, 0b11, 0, 0);
2930 void Assembler::vs(VRegister vd, Register rs1, uint8_t sumop, VSew vsew,
2933 GenInstrV(STORE_FP, width, vd, rs1, sumop, mask, 0b00, 0, 0b000);
2935 void Assembler::vss(VRegister vs3, Register rs1, Register rs2, VSew vsew,
2938 GenInstrV(STORE_FP, width, vs3, rs1, rs2, mask, 0b10, 0, 0b000);
2941 void Assembler::vsx(VRegister vd, Register rs1, VRegister vs2, VSew vsew,
2944 GenInstrV(STORE_FP, width, vd, rs1, vs2, mask, 0b11, 0, 0b000);
2946 void Assembler::vsu(VRegister vd, Register rs1, VRegister vs2, VSew vsew,
2949 GenInstrV(STORE_FP, width, vd, rs1, vs2, mask, 0b01, 0, 0b000);
2952 void Assembler::vlseg2(VRegister vd, Register rs1, uint8_t lumop, VSew vsew,
2955 GenInstrV(LOAD_FP, width, vd, rs1, lumop, mask, 0b00, 0, 0b001);
2958 void Assembler::vlseg3(VRegister vd, Register rs1, uint8_t lumop, VSew vsew,
2961 GenInstrV(LOAD_FP, width, vd, rs1, lumop, mask, 0b00, 0, 0b010);
2964 void Assembler::vlseg4(VRegister vd, Register rs1, uint8_t lumop, VSew vsew,
2967 GenInstrV(LOAD_FP, width, vd, rs1, lumop, mask, 0b00, 0, 0b011);
2970 void Assembler::vlseg5(VRegister vd, Register rs1, uint8_t lumop, VSew vsew,
2973 GenInstrV(LOAD_FP, width, vd, rs1, lumop, mask, 0b00, 0, 0b100);
2976 void Assembler::vlseg6(VRegister vd, Register rs1, uint8_t lumop, VSew vsew,
2979 GenInstrV(LOAD_FP, width, vd, rs1, lumop, mask, 0b00, 0, 0b101);
2982 void Assembler::vlseg7(VRegister vd, Register rs1, uint8_t lumop, VSew vsew,
2985 GenInstrV(LOAD_FP, width, vd, rs1, lumop, mask, 0b00, 0, 0b110);
2988 void Assembler::vlseg8(VRegister vd, Register rs1, uint8_t lumop, VSew vsew,
2991 GenInstrV(LOAD_FP, width, vd, rs1, lumop, mask, 0b00, 0, 0b111);
2993 void Assembler::vsseg2(VRegister vd, Register rs1, uint8_t sumop, VSew vsew,
2996 GenInstrV(STORE_FP, width, vd, rs1, sumop, mask, 0b00, 0, 0b001);
2998 void Assembler::vsseg3(VRegister vd, Register rs1, uint8_t sumop, VSew vsew,
3001 GenInstrV(STORE_FP, width, vd, rs1, sumop, mask, 0b00, 0, 0b010);
3003 void Assembler::vsseg4(VRegister vd, Register rs1, uint8_t sumop, VSew vsew,
3006 GenInstrV(STORE_FP, width, vd, rs1, sumop, mask, 0b00, 0, 0b011);
3008 void Assembler::vsseg5(VRegister vd, Register rs1, uint8_t sumop, VSew vsew,
3011 GenInstrV(STORE_FP, width, vd, rs1, sumop, mask, 0b00, 0, 0b100);
3013 void Assembler::vsseg6(VRegister vd, Register rs1, uint8_t sumop, VSew vsew,
3016 GenInstrV(STORE_FP, width, vd, rs1, sumop, mask, 0b00, 0, 0b101);
3018 void Assembler::vsseg7(VRegister vd, Register rs1, uint8_t sumop, VSew vsew,
3021 GenInstrV(STORE_FP, width, vd, rs1, sumop, mask, 0b00, 0, 0b110);
3023 void Assembler::vsseg8(VRegister vd, Register rs1, uint8_t sumop, VSew vsew,
3026 GenInstrV(STORE_FP, width, vd, rs1, sumop, mask, 0b00, 0, 0b111);
3029 void Assembler::vlsseg2(VRegister vd, Register rs1, Register rs2, VSew vsew,
3032 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b001);
3034 void Assembler::vlsseg3(VRegister vd, Register rs1, Register rs2, VSew vsew,
3037 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b010);
3039 void Assembler::vlsseg4(VRegister vd, Register rs1, Register rs2, VSew vsew,
3042 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b011);
3044 void Assembler::vlsseg5(VRegister vd, Register rs1, Register rs2, VSew vsew,
3047 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b100);
3049 void Assembler::vlsseg6(VRegister vd, Register rs1, Register rs2, VSew vsew,
3052 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b101);
3054 void Assembler::vlsseg7(VRegister vd, Register rs1, Register rs2, VSew vsew,
3057 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b110);
3059 void Assembler::vlsseg8(VRegister vd, Register rs1, Register rs2, VSew vsew,
3062 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b111);
3064 void Assembler::vssseg2(VRegister vd, Register rs1, Register rs2, VSew vsew,
3067 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b001);
3069 void Assembler::vssseg3(VRegister vd, Register rs1, Register rs2, VSew vsew,
3072 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b010);
3074 void Assembler::vssseg4(VRegister vd, Register rs1, Register rs2, VSew vsew,
3077 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b011);
3079 void Assembler::vssseg5(VRegister vd, Register rs1, Register rs2, VSew vsew,
3082 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b100);
3084 void Assembler::vssseg6(VRegister vd, Register rs1, Register rs2, VSew vsew,
3087 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b101);
3089 void Assembler::vssseg7(VRegister vd, Register rs1, Register rs2, VSew vsew,
3092 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b110);
3094 void Assembler::vssseg8(VRegister vd, Register rs1, Register rs2, VSew vsew,
3097 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b10, 0, 0b111);
3100 void Assembler::vlxseg2(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3103 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b001);
3105 void Assembler::vlxseg3(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3108 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b010);
3110 void Assembler::vlxseg4(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3113 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b011);
3115 void Assembler::vlxseg5(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3118 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b100);
3120 void Assembler::vlxseg6(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3123 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b101);
3125 void Assembler::vlxseg7(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3128 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b110);
3130 void Assembler::vlxseg8(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3133 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b111);
3135 void Assembler::vsxseg2(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3138 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b001);
3140 void Assembler::vsxseg3(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3143 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b010);
3145 void Assembler::vsxseg4(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3148 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b011);
3150 void Assembler::vsxseg5(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3153 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b100);
3155 void Assembler::vsxseg6(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3158 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b101);
3160 void Assembler::vsxseg7(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3163 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b110);
3165 void Assembler::vsxseg8(VRegister vd, Register rs1, VRegister rs2, VSew vsew,
3168 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b111);
3196 void Assembler::sfence_vma(Register rs1, Register rs2) {
3197 GenInstrR(0b0001001, 0b000, SYSTEM, ToRegister(0), rs1, rs2);