Lines Matching defs:opcode
730 // | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode |
817 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
821 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
827 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
831 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
837 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
841 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
847 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
851 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
857 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
861 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
867 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
871 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
877 void Assembler::GenInstrR4(uint8_t funct2, Opcode opcode, Register rd,
882 Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) |
888 void Assembler::GenInstrR4(uint8_t funct2, Opcode opcode, FPURegister rd,
893 Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) |
910 void Assembler::GenInstrRFrm(uint8_t funct7, Opcode opcode, Register rd,
913 Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) |
919 void Assembler::GenInstrI(uint8_t funct3, Opcode opcode, Register rd,
923 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
928 void Assembler::GenInstrI(uint8_t funct3, Opcode opcode, FPURegister rd,
932 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
937 void Assembler::GenInstrIShift(bool arithshift, uint8_t funct3, Opcode opcode,
941 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
947 void Assembler::GenInstrIShiftW(bool arithshift, uint8_t funct3, Opcode opcode,
951 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
957 void Assembler::GenInstrS(uint8_t funct3, Opcode opcode, Register rs1,
961 Instr instr = opcode | ((imm12 & 0x1f) << 7) | // bits 4-0
968 void Assembler::GenInstrS(uint8_t funct3, Opcode opcode, Register rs1,
972 Instr instr = opcode | ((imm12 & 0x1f) << 7) | // bits 4-0
979 void Assembler::GenInstrB(uint8_t funct3, Opcode opcode, Register rs1,
983 Instr instr = opcode | ((imm13 & 0x800) >> 4) | // bit 11
992 void Assembler::GenInstrU(Opcode opcode, Register rd, int32_t imm20) {
994 Instr instr = opcode | (rd.code() << kRdShift) | (imm20 << kImm20Shift);
998 void Assembler::GenInstrJ(Opcode opcode, Register rd, int32_t imm21) {
1000 Instr instr = opcode | (rd.code() << kRdShift) |
1008 void Assembler::GenInstrCR(uint8_t funct4, Opcode opcode, Register rd,
1011 ShortInstr instr = opcode | (rs2.code() << kRvcRs2Shift) |
1016 void Assembler::GenInstrCA(uint8_t funct6, Opcode opcode, Register rd,
1020 ShortInstr instr = opcode | ((rs2.code() & 0x7) << kRvcRs2sShift) |
1026 void Assembler::GenInstrCI(uint8_t funct3, Opcode opcode, Register rd,
1029 ShortInstr instr = opcode | ((imm6 & 0x1f) << 2) |
1035 void Assembler::GenInstrCIU(uint8_t funct3, Opcode opcode, Register rd,
1038 ShortInstr instr = opcode | ((uimm6 & 0x1f) << 2) |
1044 void Assembler::GenInstrCIU(uint8_t funct3, Opcode opcode, FPURegister rd,
1047 ShortInstr instr = opcode | ((uimm6 & 0x1f) << 2) |
1053 void Assembler::GenInstrCIW(uint8_t funct3, Opcode opcode, Register rd,
1056 ShortInstr instr = opcode | ((uimm8) << 5) |
1062 void Assembler::GenInstrCSS(uint8_t funct3, Opcode opcode, Register rs2,
1065 ShortInstr instr = opcode | (uimm6 << 7) | (rs2.code() << kRvcRs2Shift) |
1070 void Assembler::GenInstrCSS(uint8_t funct3, Opcode opcode, FPURegister rs2,
1073 ShortInstr instr = opcode | (uimm6 << 7) | (rs2.code() << kRvcRs2Shift) |
1078 void Assembler::GenInstrCL(uint8_t funct3, Opcode opcode, Register rd,
1082 ShortInstr instr = opcode | ((uimm5 & 0x3) << 5) |
1089 void Assembler::GenInstrCL(uint8_t funct3, Opcode opcode, FPURegister rd,
1093 ShortInstr instr = opcode | ((uimm5 & 0x3) << 5) |
1099 void Assembler::GenInstrCJ(uint8_t funct3, Opcode opcode, uint16_t uint11) {
1101 ShortInstr instr = opcode | (funct3 << kRvcFunct3Shift) | (uint11 << 2);
1105 void Assembler::GenInstrCS(uint8_t funct3, Opcode opcode, Register rs2,
1109 ShortInstr instr = opcode | ((uimm5 & 0x3) << 5) |
1116 void Assembler::GenInstrCS(uint8_t funct3, Opcode opcode, FPURegister rs2,
1120 ShortInstr instr = opcode | ((uimm5 & 0x3) << 5) |
1127 void Assembler::GenInstrCB(uint8_t funct3, Opcode opcode, Register rs1,
1130 ShortInstr instr = opcode | ((uimm8 & 0x1f) << 2) | ((uimm8 & 0xe0) << 5) |
1136 void Assembler::GenInstrCBA(uint8_t funct3, uint8_t funct2, Opcode opcode,
1139 ShortInstr instr = opcode | ((imm6 & 0x1f) << 2) | ((imm6 & 0x20) << 7) |
1146 void Assembler::GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd,
1148 DCHECK(opcode == OP_MVV || opcode == OP_FVV || opcode == OP_IVV);
1149 Instr instr = (funct6 << kRvvFunct6Shift) | opcode | (mask << kRvvVmShift) |
1156 void Assembler::GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd,
1158 DCHECK(opcode == OP_MVV || opcode == OP_FVV || opcode == OP_IVV);
1159 Instr instr = (funct6 << kRvvFunct6Shift) | opcode | (mask << kRvvVmShift) |
1166 void Assembler::GenInstrV(uint8_t funct6, Opcode opcode, Register rd,
1168 DCHECK(opcode == OP_MVV || opcode == OP_FVV);
1169 Instr instr = (funct6 << kRvvFunct6Shift) | opcode | (mask << kRvvVmShift) |
1177 void Assembler::GenInstrV(uint8_t funct6, Opcode opcode, FPURegister fd,
1179 DCHECK(opcode == OP_FVV);
1180 Instr instr = (funct6 << kRvvFunct6Shift) | opcode | (mask << kRvvVmShift) |
1188 void Assembler::GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd,
1190 DCHECK(opcode == OP_IVX || opcode == OP_MVX);
1191 Instr instr = (funct6 << kRvvFunct6Shift) | opcode | (mask << kRvvVmShift) |
1199 void Assembler::GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd,
1201 DCHECK(opcode == OP_FVF);
1202 Instr instr = (funct6 << kRvvFunct6Shift) | opcode | (mask << kRvvVmShift) |
1230 void Assembler::GenInstrV(Opcode opcode, uint8_t width, VRegister vd,
1233 DCHECK(opcode == LOAD_FP || opcode == STORE_FP);
1234 Instr instr = opcode | ((vd.code() << kRvvVdShift) & kRvvVdMask) |
1244 void Assembler::GenInstrV(Opcode opcode, uint8_t width, VRegister vd,
1247 DCHECK(opcode == LOAD_FP || opcode == STORE_FP);
1248 Instr instr = opcode | ((vd.code() << kRvvVdShift) & kRvvVdMask) |
1259 void Assembler::GenInstrV(Opcode opcode, uint8_t width, VRegister vd,
1262 DCHECK(opcode == LOAD_FP || opcode == STORE_FP || opcode == AMO);
1263 Instr instr = opcode | ((vd.code() << kRvvVdShift) & kRvvVdMask) |
1274 void Assembler::GenInstrV(uint8_t funct6, Opcode opcode, Register rd,
1276 DCHECK(opcode == OP_MVV);
1277 Instr instr = (funct6 << kRvvFunct6Shift) | opcode | (mask << kRvvVmShift) |
2622 // void GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, Register rs1,