Lines Matching defs:imm12
397 int32_t imm12 = instr >> 20;
398 if (imm12 == kEndOfJumpChain) {
402 return pos + imm12;
457 int32_t imm12 = ((imm & 0x800) >> 4) | // bit 11
462 return instr | (imm12 & kBImm12Mask);
469 int32_t imm12 = offset << kImm12Shift;
470 return instr | (imm12 & kImm12Mask);
484 int32_t imm12 = offset << kImm12Shift;
485 DCHECK(Assembler::IsJalr(instr | (imm12 & kImm12Mask)));
486 DCHECK_EQ(Assembler::JalrOffset(instr | (imm12 & kImm12Mask)), offset);
487 return instr | (imm12 & kImm12Mask);
746 int32_t imm12 = ((instr & 0x4) << 3) | ((instr & 0x38) >> 2) |
750 imm12 = imm12 << 20 >> 20;
751 return imm12;
761 int32_t imm12 = static_cast<int32_t>(instr_I & kImm12Mask) >> 20;
762 int32_t offset = imm12 + imm_auipc;
782 int32_t imm12 = static_cast<int32_t>(instr & kImm12Mask) >> 20;
783 return imm12;
788 int32_t imm12 = static_cast<int32_t>(instr & kImm12Mask) >> 20;
789 return imm12;
920 Register rs1, int16_t imm12) {
922 (is_uint12(imm12) || is_int12(imm12)));
924 (rs1.code() << kRs1Shift) | (imm12 << kImm12Shift);
929 Register rs1, int16_t imm12) {
931 (is_uint12(imm12) || is_int12(imm12)));
933 (rs1.code() << kRs1Shift) | (imm12 << kImm12Shift);
958 Register rs2, int16_t imm12) {
960 is_int12(imm12));
961 Instr instr = opcode | ((imm12 & 0x1f) << 7) | // bits 4-0
964 ((imm12 & 0xfe0) << 20); // bits 11-5
969 FPURegister rs2, int16_t imm12) {
971 is_int12(imm12));
972 Instr instr = opcode | ((imm12 & 0x1f) << 7) | // bits 4-0
975 ((imm12 & 0xfe0) << 20); // bits 11-5
1291 int16_t imm12) {
1292 GenInstrI(funct3, LOAD, rd, rs1, imm12);
1296 int16_t imm12) {
1297 GenInstrS(funct3, STORE, rs1, rs2, imm12);
1301 int16_t imm12) {
1302 GenInstrI(funct3, OP_IMM, rd, rs1, imm12);
1341 int16_t imm12) {
1342 GenInstrI(funct3, LOAD_FP, rd, rs1, imm12);
1346 FPURegister rs2, int16_t imm12) {
1347 GenInstrS(funct3, STORE_FP, rs1, rs2, imm12);
1528 void Assembler::jalr(Register rd, Register rs1, int16_t imm12) {
1529 GenInstrI(0b000, JALR, rd, rs1, imm12);
1561 void Assembler::lb(Register rd, Register rs1, int16_t imm12) {
1562 GenInstrLoad_ri(0b000, rd, rs1, imm12);
1565 void Assembler::lh(Register rd, Register rs1, int16_t imm12) {
1566 GenInstrLoad_ri(0b001, rd, rs1, imm12);
1569 void Assembler::lw(Register rd, Register rs1, int16_t imm12) {
1570 GenInstrLoad_ri(0b010, rd, rs1, imm12);
1573 void Assembler::lbu(Register rd, Register rs1, int16_t imm12) {
1574 GenInstrLoad_ri(0b100, rd, rs1, imm12);
1577 void Assembler::lhu(Register rd, Register rs1, int16_t imm12) {
1578 GenInstrLoad_ri(0b101, rd, rs1, imm12);
1583 void Assembler::sb(Register source, Register base, int16_t imm12) {
1584 GenInstrStore_rri(0b000, base, source, imm12);
1587 void Assembler::sh(Register source, Register base, int16_t imm12) {
1588 GenInstrStore_rri(0b001, base, source, imm12);
1591 void Assembler::sw(Register source, Register base, int16_t imm12) {
1592 GenInstrStore_rri(0b010, base, source, imm12);
1597 void Assembler::addi(Register rd, Register rs1, int16_t imm12) {
1598 GenInstrALU_ri(0b000, rd, rs1, imm12);
1601 void Assembler::slti(Register rd, Register rs1, int16_t imm12) {
1602 GenInstrALU_ri(0b010, rd, rs1, imm12);
1605 void Assembler::sltiu(Register rd, Register rs1, int16_t imm12) {
1606 GenInstrALU_ri(0b011, rd, rs1, imm12);
1609 void Assembler::xori(Register rd, Register rs1, int16_t imm12) {
1610 GenInstrALU_ri(0b100, rd, rs1, imm12);
1613 void Assembler::ori(Register rd, Register rs1, int16_t imm12) {
1614 GenInstrALU_ri(0b110, rd, rs1, imm12);
1617 void Assembler::andi(Register rd, Register rs1, int16_t imm12) {
1618 GenInstrALU_ri(0b111, rd, rs1, imm12);
1679 uint16_t imm12 = succ | (pred << 4) | (0b0000 << 8);
1680 GenInstrI(0b000, MISC_MEM, ToRegister(0), ToRegister(0), imm12);
1684 uint16_t imm12 = (0b0011) | (0b0011 << 4) | (0b1000 << 8);
1685 GenInstrI(0b000, MISC_MEM, ToRegister(0), ToRegister(0), imm12);
1733 void Assembler::lwu(Register rd, Register rs1, int16_t imm12) {
1734 GenInstrLoad_ri(0b110, rd, rs1, imm12);
1737 void Assembler::ld(Register rd, Register rs1, int16_t imm12) {
1738 GenInstrLoad_ri(0b011, rd, rs1, imm12);
1741 void Assembler::sd(Register source, Register base, int16_t imm12) {
1742 GenInstrStore_rri(0b011, base, source, imm12);
1745 void Assembler::addiw(Register rd, Register rs1, int16_t imm12) {
1746 GenInstrI(0b000, OP_IMM_32, rd, rs1, imm12);
1951 void Assembler::flw(FPURegister rd, Register rs1, int16_t imm12) {
1952 GenInstrLoadFP_ri(0b010, rd, rs1, imm12);
1955 void Assembler::fsw(FPURegister source, Register base, int16_t imm12) {
1956 GenInstrStoreFP_rri(0b010, base, source, imm12);
2083 void Assembler::fld(FPURegister rd, Register rs1, int16_t imm12) {
2084 GenInstrLoadFP_ri(0b011, rd, rs1, imm12);
2087 void Assembler::fsd(FPURegister source, Register base, int16_t imm12) {
2088 GenInstrStoreFP_rri(0b011, base, source, imm12);
2417 void Assembler::c_j(int16_t imm12) {
2418 DCHECK(is_int12(imm12));
2419 int16_t uimm11 = ((imm12 & 0x800) >> 1) | ((imm12 & 0x400) >> 4) |
2420 ((imm12 & 0x300) >> 1) | ((imm12 & 0x80) >> 3) |
2421 ((imm12 & 0x40) >> 1) | ((imm12 & 0x20) >> 5) |
2422 ((imm12 & 0x10) << 5) | (imm12 & 0xe);