Lines Matching defs:imm
409 uint64_t imm = reinterpret_cast<uint64_t>(pc);
410 if (imm == kEndOfJumpChain) {
413 DCHECK(instr_address - imm < INT_MAX);
414 int32_t delta = static_cast<int32_t>(instr_address - imm);
452 int32_t imm = target_pos - pos;
453 DCHECK_EQ(imm & 1, 0);
454 DCHECK(is_intn(imm, Assembler::kBranchOffsetBits));
457 int32_t imm12 = ((imm & 0x800) >> 4) | // bit 11
458 ((imm & 0x1e) << 7) | // bits 4-1
459 ((imm & 0x7e0) << 20) | // bits 10-5
460 ((imm & 0x1000) << 19); // bit 12
492 int32_t imm = target_pos - pos;
493 DCHECK_EQ(imm & 1, 0);
494 DCHECK(is_intn(imm, Assembler::kJumpOffsetBits));
497 int32_t imm20 = (imm & 0xff000) | // bits 19-12
498 ((imm & 0x800) << 9) | // bit 11
499 ((imm & 0x7fe) << 20) | // bits 10-1
500 ((imm & 0x100000) << 11); // bit 20
508 int32_t imm = target_pos - pos;
509 DCHECK_EQ(imm & 1, 0);
510 DCHECK(is_intn(imm, Assembler::kCJalOffsetBits));
512 int16_t imm11 = ((imm & 0x800) >> 1) | ((imm & 0x400) >> 4) |
513 ((imm & 0x300) >> 1) | ((imm & 0x80) >> 3) |
514 ((imm & 0x40) >> 1) | ((imm & 0x20) >> 5) |
515 ((imm & 0x10) << 5) | (imm & 0xe);
523 int32_t imm = target_pos - pos;
524 DCHECK_EQ(imm & 1, 0);
525 DCHECK(is_intn(imm, Assembler::kCBranchOffsetBits));
528 int32_t imm8 = ((imm & 0x20) >> 5) | ((imm & 0x6)) | ((imm & 0xc0) >> 3) |
529 ((imm & 0x18) << 2) | ((imm & 0x100) >> 1);
539 uint64_t imm = reinterpret_cast<uint64_t>(buffer_start_) + target_pos;
540 *reinterpret_cast<uint64_t*>(buffer_start_ + pos) = imm;
730 // | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode |
1412 uint64_t imm = reinterpret_cast<uint64_t>(buffer_start_) + target_pos;
1414 DCHECK_EQ(imm & 1, 0);
1416 DCHECK_EQ(imm & 3, 0);
1418 return imm;
3204 void Assembler::RV_li(Register rd, int64_t imm) {
3205 // 64-bit imm is put in the register rd.
3206 // In most cases the imm is 32 bit and 2 instructions are generated. If a
3209 // available the maximum will be 8 instructions. If imm is more than 32 bits
3210 // and a temp register is available, imm is divided into two 32-bit parts,
3218 if (is_int32(imm + 0x800)) {
3220 int64_t high_20 = ((imm + 0x800) >> 12);
3221 int64_t low_12 = imm << 52 >> 52;
3232 // 64-bit case: divide imm into two 32-bit parts, upper and lower
3233 int64_t up_32 = imm >> 32;
3234 int64_t low_32 = imm & 0xffffffffull;
3303 // No temp register. Build imm in rd.
3356 int Assembler::li_estimate(int64_t imm, bool is_get_temp_reg) {
3359 if (is_int32(imm + 0x800)) {
3361 int64_t high_20 = ((imm + 0x800) >> 12);
3362 int64_t low_12 = imm << 52 >> 52;
3373 // 64-bit case: divide imm into two 32-bit parts, upper and lower
3374 int64_t up_32 = imm >> 32;
3375 int64_t low_32 = imm & 0xffffffffull;
3431 // No temp register. Build imm in rd.
3479 void Assembler::li_ptr(Register rd, int64_t imm) {
3483 DCHECK_EQ((imm & 0xfff0000000000000ll), 0);
3484 int64_t a6 = imm & 0x3f; // bits 0:5. 6 bits
3485 int64_t b11 = (imm >> 6) & 0x7ff; // bits 6:11. 11 bits
3486 int64_t high_31 = (imm >> 17) & 0x7fffffff; // 31 bits
3497 void Assembler::li_constant(Register rd, int64_t imm) {
3498 DEBUG_PRINTF("li_constant(%d, %lx <%ld>)\n", ToNumber(rd), imm, imm);
3499 lui(rd, (imm + (1LL << 47) + (1LL << 35) + (1LL << 23) + (1LL << 11)) >>
3502 (imm + (1LL << 35) + (1LL << 23) + (1LL << 11)) << 16 >>
3505 addi(rd, rd, (imm + (1LL << 23) + (1LL << 11)) << 28 >> 52); // Bits 35:24
3507 addi(rd, rd, (imm + (1LL << 11)) << 40 >> 52); // Bits 23:12
3509 addi(rd, rd, imm << 52 >> 52); // Bits 11:0
3617 int32_t imm;
3618 imm = BrachlongOffset(instr, instr1);
3619 imm -= pc_delta;
3620 PatchBranchlongOffset(pc, instr, instr1, imm);
3810 int64_t imm = (int64_t)target - (int64_t)pc;
3813 DCHECK(is_int32(imm + 0x800));
3814 int num = PatchBranchlongOffset(pc, instr, instr1, (int32_t)imm);