Lines Matching defs:funct3
730 // | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode |
817 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
819 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
821 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
827 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
829 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
831 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
837 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
839 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
841 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
847 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
849 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
851 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
857 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
859 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
861 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
867 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
869 DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() &&
871 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
900 uint8_t funct3, Register rd, Register rs1,
902 DCHECK(is_uint5(funct5) && is_uint3(funct3) && rd.is_valid() &&
904 Instr instr = AMO | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
919 void Assembler::GenInstrI(uint8_t funct3, Opcode opcode, Register rd,
921 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
923 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
928 void Assembler::GenInstrI(uint8_t funct3, Opcode opcode, FPURegister rd,
930 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
932 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
937 void Assembler::GenInstrIShift(bool arithshift, uint8_t funct3, Opcode opcode,
939 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
941 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
947 void Assembler::GenInstrIShiftW(bool arithshift, uint8_t funct3, Opcode opcode,
949 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
951 Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) |
957 void Assembler::GenInstrS(uint8_t funct3, Opcode opcode, Register rs1,
959 DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() &&
962 (funct3 << kFunct3Shift) | (rs1.code() << kRs1Shift) |
968 void Assembler::GenInstrS(uint8_t funct3, Opcode opcode, Register rs1,
970 DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() &&
973 (funct3 << kFunct3Shift) | (rs1.code() << kRs1Shift) |
979 void Assembler::GenInstrB(uint8_t funct3, Opcode opcode, Register rs1,
981 DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() &&
985 (funct3 << kFunct3Shift) | (rs1.code() << kRs1Shift) |
1026 void Assembler::GenInstrCI(uint8_t funct3, Opcode opcode, Register rd,
1028 DCHECK(is_uint3(funct3) && rd.is_valid() && is_int6(imm6));
1031 (funct3 << kRvcFunct3Shift);
1035 void Assembler::GenInstrCIU(uint8_t funct3, Opcode opcode, Register rd,
1037 DCHECK(is_uint3(funct3) && rd.is_valid() && is_uint6(uimm6));
1040 (funct3 << kRvcFunct3Shift);
1044 void Assembler::GenInstrCIU(uint8_t funct3, Opcode opcode, FPURegister rd,
1046 DCHECK(is_uint3(funct3) && rd.is_valid() && is_uint6(uimm6));
1049 (funct3 << kRvcFunct3Shift);
1053 void Assembler::GenInstrCIW(uint8_t funct3, Opcode opcode, Register rd,
1055 DCHECK(is_uint3(funct3) && rd.is_valid() && is_uint8(uimm8));
1058 (funct3 << kRvcFunct3Shift);
1062 void Assembler::GenInstrCSS(uint8_t funct3, Opcode opcode, Register rs2,
1064 DCHECK(is_uint3(funct3) && rs2.is_valid() && is_uint6(uimm6));
1066 (funct3 << kRvcFunct3Shift);
1070 void Assembler::GenInstrCSS(uint8_t funct3, Opcode opcode, FPURegister rs2,
1072 DCHECK(is_uint3(funct3) && rs2.is_valid() && is_uint6(uimm6));
1074 (funct3 << kRvcFunct3Shift);
1078 void Assembler::GenInstrCL(uint8_t funct3, Opcode opcode, Register rd,
1080 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
1084 ((uimm5 & 0x1c) << 8) | (funct3 << kRvcFunct3Shift) |
1089 void Assembler::GenInstrCL(uint8_t funct3, Opcode opcode, FPURegister rd,
1091 DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() &&
1095 ((uimm5 & 0x1c) << 8) | (funct3 << kRvcFunct3Shift) |
1099 void Assembler::GenInstrCJ(uint8_t funct3, Opcode opcode, uint16_t uint11) {
1101 ShortInstr instr = opcode | (funct3 << kRvcFunct3Shift) | (uint11 << 2);
1105 void Assembler::GenInstrCS(uint8_t funct3, Opcode opcode, Register rs2,
1107 DCHECK(is_uint3(funct3) && rs2.is_valid() && rs1.is_valid() &&
1111 ((uimm5 & 0x1c) << 8) | (funct3 << kRvcFunct3Shift) |
1116 void Assembler::GenInstrCS(uint8_t funct3, Opcode opcode, FPURegister rs2,
1118 DCHECK(is_uint3(funct3) && rs2.is_valid() && rs1.is_valid() &&
1122 ((uimm5 & 0x1c) << 8) | (funct3 << kRvcFunct3Shift) |
1127 void Assembler::GenInstrCB(uint8_t funct3, Opcode opcode, Register rs1,
1129 DCHECK(is_uint3(funct3) && is_uint8(uimm8));
1132 (funct3 << kRvcFunct3Shift);
1136 void Assembler::GenInstrCBA(uint8_t funct3, uint8_t funct2, Opcode opcode,
1138 DCHECK(is_uint3(funct3) && is_uint2(funct2) && is_int6(imm6));
1141 (funct3 << kRvcFunct3Shift) | (funct2 << 10);
1285 void Assembler::GenInstrBranchCC_rri(uint8_t funct3, Register rs1, Register rs2,
1287 GenInstrB(funct3, BRANCH, rs1, rs2, imm13);
1290 void Assembler::GenInstrLoad_ri(uint8_t funct3, Register rd, Register rs1,
1292 GenInstrI(funct3, LOAD, rd, rs1, imm12);
1295 void Assembler::GenInstrStore_rri(uint8_t funct3, Register rs1, Register rs2,
1297 GenInstrS(funct3, STORE, rs1, rs2, imm12);
1300 void Assembler::GenInstrALU_ri(uint8_t funct3, Register rd, Register rs1,
1302 GenInstrI(funct3, OP_IMM, rd, rs1, imm12);
1305 void Assembler::GenInstrShift_ri(bool arithshift, uint8_t funct3, Register rd,
1308 GenInstrI(funct3, OP_IMM, rd, rs1, (arithshift << 10) | shamt);
1311 void Assembler::GenInstrALU_rr(uint8_t funct7, uint8_t funct3, Register rd,
1313 GenInstrR(funct7, funct3, OP, rd, rs1, rs2);
1316 void Assembler::GenInstrCSR_ir(uint8_t funct3, Register rd,
1318 GenInstrI(funct3, SYSTEM, rd, rs1, csr);
1321 void Assembler::GenInstrCSR_ii(uint8_t funct3, Register rd,
1323 GenInstrI(funct3, SYSTEM, rd, ToRegister(imm5), csr);
1326 void Assembler::GenInstrShiftW_ri(bool arithshift, uint8_t funct3, Register rd,
1328 GenInstrIShiftW(arithshift, funct3, OP_IMM_32, rd, rs1, shamt);
1331 void Assembler::GenInstrALUW_rr(uint8_t funct7, uint8_t funct3, Register rd,
1333 GenInstrR(funct7, funct3, OP_32, rd, rs1, rs2);
1340 void Assembler::GenInstrLoadFP_ri(uint8_t funct3, FPURegister rd, Register rs1,
1342 GenInstrI(funct3, LOAD_FP, rd, rs1, imm12);
1345 void Assembler::GenInstrStoreFP_rri(uint8_t funct3, Register rs1,
1347 GenInstrS(funct3, STORE_FP, rs1, rs2, imm12);
1350 void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd,
1352 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1355 void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd,
1357 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1360 void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd,
1362 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1365 void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd,
1367 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);
1370 void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd,
1372 GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2);