Lines Matching defs:bits
283 DCHECK(m >= 4 && base::bits::IsPowerOfTwo(m));
458 ((imm & 0x1e) << 7) | // bits 4-1
459 ((imm & 0x7e0) << 20) | // bits 10-5
497 int32_t imm20 = (imm & 0xff000) | // bits 19-12
499 ((imm & 0x7fe) << 20) | // bits 10-1
719 bool Assembler::is_near(Label* L, OffsetSize bits) {
721 return is_intn((pc_offset() - L->pos()), bits);
798 // if they can be encoded in RISC-V's 12 bits of immediate-offset instruction
961 Instr instr = opcode | ((imm12 & 0x1f) << 7) | // bits 4-0
964 ((imm12 & 0xfe0) << 20); // bits 11-5
972 Instr instr = opcode | ((imm12 & 0x1f) << 7) | // bits 4-0
975 ((imm12 & 0xfe0) << 20); // bits 11-5
984 ((imm13 & 0x1e) << 7) | // bits 4-1
987 ((imm13 & 0x7e0) << 20) | // bits 10-5
1001 (imm21 & 0xff000) | // bits 19-12
1003 ((imm21 & 0x7fe) << 20) | // bits 10-1
1452 int32_t Assembler::branch_offset_helper(Label* L, OffsetSize bits) {
1478 DCHECK(is_intn(offset, bits));
3209 // available the maximum will be 8 instructions. If imm is more than 32 bits
3212 // built before up_32. If low_32 is negative (upper 32 bits are 1), 0xffffffff
3214 // bits of 1's in the lower when the two registers are added. If no temp is
3215 // available, the upper 32 bit is built in rd, and the lower 32 bits are
3216 // devided to 3 parts (11, 11, and 10 bits). The parts are shifted and added
3252 // Adjust to 20 bits for the case of overflow
3287 // Adjust to 20 bits for the case of overflow
3304 // Build upper 32 bits first in rd. Divide lower 32 bits parts and add
3310 // Adjust to 20 bits for the case of overflow
3320 // bits, and always starts with a 1. rd is shifted by the size of the part
3339 // Pick 11 bits
3385 // Adjust to 20 bits for the case of overflow
3415 // Adjust to 20 bits for the case of overflow
3432 // Build upper 32 bits first in rd. Divide lower 32 bits parts and add
3438 // Adjust to 20 bits for the case of overflow
3448 // bits, and always starts with a 1. rd is shifted by the size of the part
3464 // Pick 11 bits
3481 // Pointers are 48 bits
3484 int64_t a6 = imm & 0x3f; // bits 0:5. 6 bits
3485 int64_t b11 = (imm >> 6) & 0x7ff; // bits 6:11. 11 bits
3486 int64_t high_31 = (imm >> 17) & 0x7fffffff; // 31 bits
3487 int64_t high_20 = ((high_31 + 0x800) >> 12); // 19 bits
3488 int64_t low_12 = high_31 & 0xfff; // 12 bits
3490 addi(rd, rd, low_12); // 31 bits in rd.
3492 ori(rd, rd, b11); // 11 bits are put in. 42 bit in rd
3493 slli(rd, rd, 6); // Space for next 6 bits
3494 ori(rd, rd, a6); // 6 bits are put in. 48 bis in rd
3874 // lui(reg, (int32_t)high_20); // 19 high bits
3875 // addi(reg, reg, low_12); // 12 following bits. total is 31 high bits in reg.
3876 // slli(reg, reg, 11); // Space for next 11 bits
3877 // ori(reg, reg, b11); // 11 bits are put in. 42 bit in reg
3878 // slli(reg, reg, 6); // Space for next 6 bits
3879 // ori(reg, reg, a6); // 6 bits are put in. all 48 bis in reg
3899 int64_t a6 = target & 0x3f; // bits 0:6. 6 bits
3900 int64_t b11 = (target >> 6) & 0x7ff; // bits 6:11. 11 bits
3901 int64_t high_31 = (target >> 17) & 0x7fffffff; // 31 bits
3902 int64_t high_20 = ((high_31 + 0x800) >> 12); // 19 bits
3903 int64_t low_12 = high_31 & 0xfff; // 12 bits
3933 static_cast<int>(base::bits::CountTrailingZeros32(available_->bits()));
3985 // Recorded constant pool size is expressed in number of 32-bits words,