Lines Matching defs:b11
2328 GenInstrCA(0b100011, C1, rd, 0b11, rs2);
2927 GenInstrV(LOAD_FP, width, vd, rs1, vs2, mask, 0b11, 0, 0);
2944 GenInstrV(STORE_FP, width, vd, rs1, vs2, mask, 0b11, 0, 0b000);
3103 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b001);
3108 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b010);
3113 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b011);
3118 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b100);
3123 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b101);
3128 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b110);
3133 GenInstrV(LOAD_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b111);
3138 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b001);
3143 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b010);
3148 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b011);
3153 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b100);
3158 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b101);
3163 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b110);
3168 GenInstrV(STORE_FP, width, vd, rs1, rs2, mask, 0b11, 0, 0b111);
3485 int64_t b11 = (imm >> 6) & 0x7ff; // bits 6:11. 11 bits
3492 ori(rd, rd, b11); // 11 bits are put in. 42 bit in rd
3877 // ori(reg, reg, b11); // 11 bits are put in. 42 bit in reg
3900 int64_t b11 = (target >> 6) & 0x7ff; // bits 6:11. 11 bits
3911 *(p + 3) = *(p + 3) | ((int32_t)b11 << 20);