Lines Matching defs:addi
142 // specially coded on RISC-V means that it is a lui/addi instruction, and that
1597 void Assembler::addi(Register rd, Register rs1, int16_t imm12) {
3202 void Assembler::nop() { addi(ToRegister(0), ToRegister(0), 0); }
3225 addi(rd, rd, low_12);
3228 addi(rd, zero_reg, low_12);
3258 addi(rd, rd, low_12);
3291 addi(temp_reg, temp_reg, low_12);
3314 addi(rd, rd, low_12);
3490 addi(rd, rd, low_12); // 31 bits in rd.
3505 addi(rd, rd, (imm + (1LL << 23) + (1LL << 11)) << 28 >> 52); // Bits 35:24
3507 addi(rd, rd, (imm + (1LL << 11)) << 40 >> 52); // Bits 23:12
3509 addi(rd, rd, imm << 52 >> 52); // Bits 11:0
3571 addi(scratch, src->rm(), kMinOffsetForSimpleAdjustment);
3575 addi(scratch, src->rm(), -kMinOffsetForSimpleAdjustment);
3875 // addi(reg, reg, low_12); // 12 following bits. total is 31 high bits in reg.