Lines Matching defs:src
37 #include "src/codegen/ppc/assembler-ppc.h"
41 #include "src/base/bits.h"
42 #include "src/base/cpu.h"
43 #include "src/codegen/macro-assembler.h"
44 #include "src/codegen/ppc/assembler-ppc-inl.h"
45 #include "src/codegen/string-constants.h"
46 #include "src/deoptimizer/deoptimizer.h"
726 void Assembler::xori(Register dst, Register src, const Operand& imm) {
727 d_form(XORI, src, dst, imm.immediate(), false);
760 void Assembler::slwi(Register dst, Register src, const Operand& val, RCBit rc) {
762 rlwinm(dst, src, val.immediate(), 0, 31 - val.immediate(), rc);
765 void Assembler::srwi(Register dst, Register src, const Operand& val, RCBit rc) {
767 rlwinm(dst, src, 32 - val.immediate(), val.immediate(), 31, rc);
770 void Assembler::clrrwi(Register dst, Register src, const Operand& val,
773 rlwinm(dst, src, 0, 0, 31 - val.immediate(), rc);
776 void Assembler::clrlwi(Register dst, Register src, const Operand& val,
779 rlwinm(dst, src, 0, val.immediate(), 31, rc);
794 void Assembler::subi(Register dst, Register src, const Operand& imm) {
795 addi(dst, src, Operand(-(imm.immediate())));
828 void Assembler::subfic(Register dst, Register src, const Operand& imm) {
829 d_form(SUBFIC, dst, src, imm.immediate(), true);
843 void Assembler::mulli(Register dst, Register src, const Operand& imm) {
844 d_form(MULLI, dst, src, imm.immediate(), true);
869 void Assembler::addi(Register dst, Register src, const Operand& imm) {
870 DCHECK(src != r0); // use li instead to show intent
871 d_form(ADDI, dst, src, imm.immediate(), true);
874 void Assembler::addis(Register dst, Register src, const Operand& imm) {
875 DCHECK(src != r0); // use lis instead to show intent
876 d_form(ADDIS, dst, src, imm.immediate(), true);
879 void Assembler::addic(Register dst, Register src, const Operand& imm) {
880 d_form(ADDIC, dst, src, imm.immediate(), true);
895 void Assembler::oris(Register dst, Register src, const Operand& imm) {
896 d_form(ORIS, src, dst, imm.immediate(), false);
966 void Assembler::mr(Register dst, Register src) {
967 // actually or(dst, src, src)
968 orx(dst, src, src);
971 void Assembler::lbz(Register dst, const MemOperand& src) {
972 DCHECK(src.ra_ != r0);
973 d_form(LBZ, dst, src.ra(), src.offset(), true);
976 void Assembler::lhz(Register dst, const MemOperand& src) {
977 DCHECK(src.ra_ != r0);
978 d_form(LHZ, dst, src.ra(), src.offset(), true);
981 void Assembler::lwz(Register dst, const MemOperand& src) {
982 DCHECK(src.ra_ != r0);
983 d_form(LWZ, dst, src.ra(), src.offset(), true);
986 void Assembler::lwzu(Register dst, const MemOperand& src) {
987 DCHECK(src.ra_ != r0);
988 d_form(LWZU, dst, src.ra(), src.offset(), true);
991 void Assembler::lha(Register dst, const MemOperand& src) {
992 DCHECK(src.ra_ != r0);
993 d_form(LHA, dst, src.ra(), src.offset(), true);
996 void Assembler::lwa(Register dst, const MemOperand& src) {
998 int offset = src.offset();
999 DCHECK(src.ra_ != r0);
1002 emit(LD | dst.code() * B21 | src.ra().code() * B16 | offset | 2);
1004 lwz(dst, src);
1008 void Assembler::stb(Register dst, const MemOperand& src) {
1009 DCHECK(src.ra_ != r0);
1010 d_form(STB, dst, src.ra(), src.offset(), true);
1013 void Assembler::sth(Register dst, const MemOperand& src) {
1014 DCHECK(src.ra_ != r0);
1015 d_form(STH, dst, src.ra(), src.offset(), true);
1018 void Assembler::stw(Register dst, const MemOperand& src) {
1019 DCHECK(src.ra_ != r0);
1020 d_form(STW, dst, src.ra(), src.offset(), true);
1023 void Assembler::stwu(Register dst, const MemOperand& src) {
1024 DCHECK(src.ra_ != r0);
1025 d_form(STWU, dst, src.ra(), src.offset(), true);
1034 void Assembler::ld(Register rd, const MemOperand& src) {
1035 int offset = src.offset();
1036 DCHECK(src.ra_ != r0);
1039 emit(LD | rd.code() * B21 | src.ra().code() * B16 | offset);
1042 void Assembler::ldu(Register rd, const MemOperand& src) {
1043 int offset = src.offset();
1044 DCHECK(src.ra_ != r0);
1047 emit(LD | rd.code() * B21 | src.ra().code() * B16 | offset | 1);
1050 void Assembler::std(Register rs, const MemOperand& src) {
1051 int offset = src.offset();
1052 DCHECK(src.ra_ != r0);
1055 emit(STD | rs.code() * B21 | src.ra().code() * B16 | offset);
1058 void Assembler::stdu(Register rs, const MemOperand& src) {
1059 int offset = src.offset();
1060 DCHECK(src.ra_ != r0);
1063 emit(STD | rs.code() * B21 | src.ra().code() * B16 | offset | 1);
1082 void Assembler::sldi(Register dst, Register src, const Operand& val, RCBit rc) {
1084 rldicr(dst, src, val.immediate(), 63 - val.immediate(), rc);
1087 void Assembler::srdi(Register dst, Register src, const Operand& val, RCBit rc) {
1089 rldicl(dst, src, 64 - val.immediate(), val.immediate(), rc);
1092 void Assembler::clrrdi(Register dst, Register src, const Operand& val,
1095 rldicr(dst, src, 0, 63 - val.immediate(), rc);
1098 void Assembler::clrldi(Register dst, Register src, const Operand& val,
1101 rldicl(dst, src, 0, val.immediate(), rc);
1152 void Assembler::paddi(Register dst, Register src, const Operand& imm) {
1154 DCHECK(src != r0); // use pli instead to show intent.
1159 addi(dst, src, Operand(lo));
1171 void Assembler::psubi(Register dst, Register src, const Operand& imm) {
1172 paddi(dst, src, Operand(-(imm.immediate())));
1175 void Assembler::plbz(Register dst, const MemOperand& src) {
1176 DCHECK(src.ra_ != r0);
1177 int64_t offset = src.offset();
1181 lbz(dst, MemOperand(src.ra(), lo));
1184 void Assembler::plhz(Register dst, const MemOperand& src) {
1185 DCHECK(src.ra_ != r0);
1186 int64_t offset = src.offset();
1190 lhz(dst, MemOperand(src.ra(), lo));
1193 void Assembler::plha(Register dst, const MemOperand& src) {
1194 DCHECK(src.ra_ != r0);
1195 int64_t offset = src.offset();
1199 lha(dst, MemOperand(src.ra(), lo));
1202 void Assembler::plwz(Register dst, const MemOperand& src) {
1203 DCHECK(src.ra_ != r0);
1204 int64_t offset = src.offset();
1208 lwz(dst, MemOperand(src.ra(), lo));
1211 void Assembler::plwa(Register dst, const MemOperand& src) {
1212 DCHECK(src.ra_ != r0);
1213 int64_t offset = src.offset();
1217 emit(PPLWA | dst.code() * B21 | src.ra().code() * B16 | (lo & kImm16Mask));
1220 void Assembler::pld(Register dst, const MemOperand& src) {
1221 DCHECK(src.ra_ != r0);
1222 int64_t offset = src.offset();
1226 emit(PPLD | dst.code() * B21 | src.ra().code() * B16 | (lo & kImm16Mask));
1229 void Assembler::plfs(DoubleRegister dst, const MemOperand& src) {
1230 DCHECK(src.ra_ != r0);
1231 int64_t offset = src.offset();
1235 lfs(dst, MemOperand(src.ra(), lo));
1238 void Assembler::plfd(DoubleRegister dst, const MemOperand& src) {
1239 DCHECK(src.ra_ != r0);
1240 int64_t offset = src.offset();
1244 lfd(dst, MemOperand(src.ra(), lo));
1249 const Operand& src) const {
1251 !(src.must_output_reloc_info(this) || is_trampoline_pool_blocked());
1252 if (use_constant_pool_for_mov(dst, src, canOptimize)) {
1262 bool Assembler::use_constant_pool_for_mov(Register dst, const Operand& src,
1269 intptr_t value = src.immediate();
1312 void Assembler::mov(Register dst, const Operand& src) {
1314 if (src.IsHeapObjectRequest()) {
1315 RequestHeapObject(src.heap_object_request());
1318 value = src.immediate();
1320 bool relocatable = src.must_output_reloc_info(this);
1329 if (!src.IsHeapObjectRequest() &&
1330 use_constant_pool_for_mov(dst, src, canOptimize)) {
1333 RecordRelocInfo(src.rmode_);
1335 ConstantPoolEntry::Access access = ConstantPoolAddEntry(src.rmode_, value);
1393 RecordRelocInfo(src.rmode_);
1428 void Assembler::bitwise_add32(Register dst, Register src, int32_t value) {
1431 addi(dst, src, Operand(value));
1437 addis(dst, src, Operand(SIGN_EXT_IMM16(hi_word)));
1574 void Assembler::mtlr(Register src) {
1575 emit(EXT2 | MTSPR | src.code() * B21 | 256 << 11); // Ignore RC bit
1578 void Assembler::mtctr(Register src) {
1579 emit(EXT2 | MTSPR | src.code() * B21 | 288 << 11); // Ignore RC bit
1582 void Assembler::mtxer(Register src) {
1583 emit(EXT2 | MTSPR | src.code() * B21 | 32 << 11);
1595 void Assembler::mtcrf(Register src, uint8_t FXM) {
1596 emit(MTCRF | src.code() * B21 | FXM * B12);
1599 void Assembler::mffprd(Register dst, DoubleRegister src) {
1600 emit(EXT2 | MFVSRD | src.code() * B21 | dst.code() * B16);
1603 void Assembler::mffprwz(Register dst, DoubleRegister src) {
1604 emit(EXT2 | MFVSRWZ | src.code() * B21 | dst.code() * B16);
1607 void Assembler::mtfprd(DoubleRegister dst, Register src) {
1608 emit(EXT2 | MTVSRD | dst.code() * B21 | src.code() * B16);
1611 void Assembler::mtfprwz(DoubleRegister dst, Register src) {
1612 emit(EXT2 | MTVSRWZ | dst.code() * B21 | src.code() * B16);
1615 void Assembler::mtfprwa(DoubleRegister dst, Register src) {
1616 emit(EXT2 | MTVSRWA | dst.code() * B21 | src.code() * B16);
1652 void Assembler::lfd(const DoubleRegister frt, const MemOperand& src) {
1653 int offset = src.offset();
1654 Register ra = src.ra();
1662 void Assembler::lfdu(const DoubleRegister frt, const MemOperand& src) {
1663 int offset = src.offset();
1664 Register ra = src.ra();
1672 void Assembler::lfs(const DoubleRegister frt, const MemOperand& src) {
1673 int offset = src.offset();
1674 Register ra = src.ra();
1682 void Assembler::lfsu(const DoubleRegister frt, const MemOperand& src) {
1683 int offset = src.offset();
1684 Register ra = src.ra();
1692 void Assembler::stfd(const DoubleRegister frs, const MemOperand& src) {
1693 int offset = src.offset();
1694 Register ra = src.ra();
1702 void Assembler::stfdu(const DoubleRegister frs, const MemOperand& src) {
1703 int offset = src.offset();
1704 Register ra = src.ra();
1712 void Assembler::stfs(const DoubleRegister frs, const MemOperand& src) {
1713 int offset = src.offset();
1714 Register ra = src.ra();
1722 void Assembler::stfsu(const DoubleRegister frs, const MemOperand& src) {
1723 int offset = src.offset();
1724 Register ra = src.ra();
1930 void Assembler::lxvd(const Simd128Register rt, const MemOperand& src) {
1931 CHECK(src.rb().is_valid());
1933 emit(LXVD | rt.code() * B21 | src.ra().code() * B16 | src.rb().code() * B11 |
1937 void Assembler::lxvx(const Simd128Register rt, const MemOperand& src) {
1938 CHECK(src.rb().is_valid());
1940 emit(LXVX | rt.code() * B21 | src.ra().code() * B16 | src.rb().code() * B11 |
1944 void Assembler::lxsdx(const Simd128Register rt, const MemOperand& src) {
1945 CHECK(src.rb().is_valid());
1947 emit(LXSDX | rt.code() * B21 | src.ra().code() * B16 | src.rb().code() * B11 |
1951 void Assembler::lxsibzx(const Simd128Register rt, const MemOperand& src) {
1952 CHECK(src.rb().is_valid());
1954 emit(LXSIBZX | rt.code() * B21 | src.ra().code() * B16 |
1955 src.rb().code() * B11 | TX);
1958 void Assembler::lxsihzx(const Simd128Register rt, const MemOperand& src) {
1959 CHECK(src.rb().is_valid());
1961 emit(LXSIHZX | rt.code() * B21 | src.ra().code() * B16 |
1962 src.rb().code() * B11 | TX);
1965 void Assembler::lxsiwzx(const Simd128Register rt, const MemOperand& src) {
1966 CHECK(src.rb().is_valid());
1968 emit(LXSIWZX | rt.code() * B21 | src.ra().code() * B16 |
1969 src.rb().code() * B11 | TX);