Lines Matching refs:rt
41 static inline bool IsZero(const Operand& rt) {
42 if (rt.is_reg()) {
43 return rt.rm() == zero_reg;
45 return rt.immediate() == 0;
338 void TurboAssembler::Addu(Register rd, Register rs, const Operand& rt) {
339 if (rt.is_reg()) {
340 addu(rd, rs, rt.rm());
342 if (is_int16(rt.immediate()) && !MustUseReg(rt.rmode())) {
343 addiu(rd, rs, static_cast<int32_t>(rt.immediate()));
349 li(scratch, rt);
355 void TurboAssembler::Daddu(Register rd, Register rs, const Operand& rt) {
356 if (rt.is_reg()) {
357 daddu(rd, rs, rt.rm());
359 if (is_int16(rt.immediate()) && !MustUseReg(rt.rmode())) {
360 daddiu(rd, rs, static_cast<int32_t>(rt.immediate()));
366 li(scratch, rt);
372 void TurboAssembler::Subu(Register rd, Register rs, const Operand& rt) {
373 if (rt.is_reg()) {
374 subu(rd, rs, rt.rm());
376 DCHECK(is_int32(rt.immediate()));
377 if (is_int16(-rt.immediate()) && !MustUseReg(rt.rmode())) {
380 -rt.immediate())); // No subiu instr, use addiu(x, y, -imm).
385 if (-rt.immediate() >> 16 == 0 && !MustUseReg(rt.rmode())) {
387 li(scratch, -rt.immediate());
391 li(scratch, rt);
398 void TurboAssembler::Dsubu(Register rd, Register rs, const Operand& rt) {
399 if (rt.is_reg()) {
400 dsubu(rd, rs, rt.rm());
401 } else if (is_int16(-rt.immediate()) && !MustUseReg(rt.rmode())) {
404 -rt.immediate())); // No dsubiu instr, use daddiu(x, y, -imm).
407 int li_count = InstrCountForLi64Bit(rt.immediate());
408 int li_neg_count = InstrCountForLi64Bit(-rt.immediate());
409 if (li_neg_count < li_count && !MustUseReg(rt.rmode())) {
411 DCHECK(rt.immediate() != std::numeric_limits<int32_t>::min());
414 li(scratch, Operand(-rt.immediate()));
420 li(scratch, rt);
426 void TurboAssembler::Mul(Register rd, Register rs, const Operand& rt) {
427 if (rt.is_reg()) {
428 mul(rd, rs, rt.rm());
434 li(scratch, rt);
439 void TurboAssembler::Mulh(Register rd, Register rs, const Operand& rt) {
440 if (rt.is_reg()) {
442 mult(rs, rt.rm());
445 muh(rd, rs, rt.rm());
452 li(scratch, rt);
462 void TurboAssembler::Mulhu(Register rd, Register rs, const Operand& rt) {
463 if (rt.is_reg()) {
465 multu(rs, rt.rm());
468 muhu(rd, rs, rt.rm());
475 li(scratch, rt);
485 void TurboAssembler::Dmul(Register rd, Register rs, const Operand& rt) {
486 if (rt.is_reg()) {
488 dmul(rd, rs, rt.rm());
490 dmult(rs, rt.rm());
498 li(scratch, rt);
508 void TurboAssembler::Dmulh(Register rd, Register rs, const Operand& rt) {
509 if (rt.is_reg()) {
511 dmuh(rd, rs, rt.rm());
513 dmult(rs, rt.rm());
521 li(scratch, rt);
531 void TurboAssembler::Mult(Register rs, const Operand& rt) {
532 if (rt.is_reg()) {
533 mult(rs, rt.rm());
539 li(scratch, rt);
544 void TurboAssembler::Dmult(Register rs, const Operand& rt) {
545 if (rt.is_reg()) {
546 dmult(rs, rt.rm());
552 li(scratch, rt);
557 void TurboAssembler::Multu(Register rs, const Operand& rt) {
558 if (rt.is_reg()) {
559 multu(rs, rt.rm());
565 li(scratch, rt);
570 void TurboAssembler::Dmultu(Register rs, const Operand& rt) {
571 if (rt.is_reg()) {
572 dmultu(rs, rt.rm());
578 li(scratch, rt);
583 void TurboAssembler::Div(Register rs, const Operand& rt) {
584 if (rt.is_reg()) {
585 div(rs, rt.rm());
591 li(scratch, rt);
596 void TurboAssembler::Div(Register res, Register rs, const Operand& rt) {
597 if (rt.is_reg()) {
599 div(rs, rt.rm());
602 div(res, rs, rt.rm());
609 li(scratch, rt);
619 void TurboAssembler::Mod(Register rd, Register rs, const Operand& rt) {
620 if (rt.is_reg()) {
622 div(rs, rt.rm());
625 mod(rd, rs, rt.rm());
632 li(scratch, rt);
642 void TurboAssembler::Modu(Register rd, Register rs, const Operand& rt) {
643 if (rt.is_reg()) {
645 divu(rs, rt.rm());
648 modu(rd, rs, rt.rm());
655 li(scratch, rt);
665 void TurboAssembler::Ddiv(Register rs, const Operand& rt) {
666 if (rt.is_reg()) {
667 ddiv(rs, rt.rm());
673 li(scratch, rt);
678 void TurboAssembler::Ddiv(Register rd, Register rs, const Operand& rt) {
680 if (rt.is_reg()) {
681 ddiv(rs, rt.rm());
688 li(scratch, rt);
693 if (rt.is_reg()) {
694 ddiv(rd, rs, rt.rm());
700 li(scratch, rt);
706 void TurboAssembler::Divu(Register rs, const Operand& rt) {
707 if (rt.is_reg()) {
708 divu(rs, rt.rm());
714 li(scratch, rt);
719 void TurboAssembler::Divu(Register res, Register rs, const Operand& rt) {
720 if (rt.is_reg()) {
722 divu(rs, rt.rm());
725 divu(res, rs, rt.rm());
732 li(scratch, rt);
742 void TurboAssembler::Ddivu(Register rs, const Operand& rt) {
743 if (rt.is_reg()) {
744 ddivu(rs, rt.rm());
750 li(scratch, rt);
755 void TurboAssembler::Ddivu(Register res, Register rs, const Operand& rt) {
756 if (rt.is_reg()) {
758 ddivu(rs, rt.rm());
761 ddivu(res, rs, rt.rm());
768 li(scratch, rt);
778 void TurboAssembler::Dmod(Register rd, Register rs, const Operand& rt) {
780 if (rt.is_reg()) {
781 ddiv(rs, rt.rm());
788 li(scratch, rt);
793 if (rt.is_reg()) {
794 dmod(rd, rs, rt.rm());
800 li(scratch, rt);
806 void TurboAssembler::Dmodu(Register rd, Register rs, const Operand& rt) {
808 if (rt.is_reg()) {
809 ddivu(rs, rt.rm());
816 li(scratch, rt);
821 if (rt.is_reg()) {
822 dmodu(rd, rs, rt.rm());
828 li(scratch, rt);
834 void TurboAssembler::And(Register rd, Register rs, const Operand& rt) {
835 if (rt.is_reg()) {
836 and_(rd, rs, rt.rm());
838 if (is_uint16(rt.immediate()) && !MustUseReg(rt.rmode())) {
839 andi(rd, rs, static_cast<int32_t>(rt.immediate()));
845 li(scratch, rt);
851 void TurboAssembler::Or(Register rd, Register rs, const Operand& rt) {
852 if (rt.is_reg()) {
853 or_(rd, rs, rt.rm());
855 if (is_uint16(rt.immediate()) && !MustUseReg(rt.rmode())) {
856 ori(rd, rs, static_cast<int32_t>(rt.immediate()));
862 li(scratch, rt);
868 void TurboAssembler::Xor(Register rd, Register rs, const Operand& rt) {
869 if (rt.is_reg()) {
870 xor_(rd, rs, rt.rm());
872 if (is_uint16(rt.immediate()) && !MustUseReg(rt.rmode())) {
873 xori(rd, rs, static_cast<int32_t>(rt.immediate()));
879 li(scratch, rt);
885 void TurboAssembler::Nor(Register rd, Register rs, const Operand& rt) {
886 if (rt.is_reg()) {
887 nor(rd, rs, rt.rm());
893 li(scratch, rt);
898 void TurboAssembler::Neg(Register rs, const Operand& rt) {
899 dsubu(rs, zero_reg, rt.rm());
902 void TurboAssembler::Slt(Register rd, Register rs, const Operand& rt) {
903 if (rt.is_reg()) {
904 slt(rd, rs, rt.rm());
906 if (is_int16(rt.immediate()) && !MustUseReg(rt.rmode())) {
907 slti(rd, rs, static_cast<int32_t>(rt.immediate()));
914 li(scratch, rt);
920 void TurboAssembler::Sltu(Register rd, Register rs, const Operand& rt) {
921 if (rt.is_reg()) {
922 sltu(rd, rs, rt.rm());
925 if (is_uint15(rt.immediate()) && !MustUseReg(rt.rmode())) {
927 sltiu(rd, rs, static_cast<int32_t>(rt.immediate()));
928 } else if (is_uint15(rt.immediate() - int16_min) &&
929 !MustUseReg(rt.rmode())) {
931 sltiu(rd, rs, static_cast<uint16_t>(rt.immediate()));
938 li(scratch, rt);
944 void TurboAssembler::Sle(Register rd, Register rs, const Operand& rt) {
945 if (rt.is_reg()) {
946 slt(rd, rt.rm(), rs);
953 li(scratch, rt);
959 void TurboAssembler::Sleu(Register rd, Register rs, const Operand& rt) {
960 if (rt.is_reg()) {
961 sltu(rd, rt.rm(), rs);
968 li(scratch, rt);
974 void TurboAssembler::Sge(Register rd, Register rs, const Operand& rt) {
975 Slt(rd, rs, rt);
979 void TurboAssembler::Sgeu(Register rd, Register rs, const Operand& rt) {
980 Sltu(rd, rs, rt);
984 void TurboAssembler::Sgt(Register rd, Register rs, const Operand& rt) {
985 if (rt.is_reg()) {
986 slt(rd, rt.rm(), rs);
993 li(scratch, rt);
998 void TurboAssembler::Sgtu(Register rd, Register rs, const Operand& rt) {
999 if (rt.is_reg()) {
1000 sltu(rd, rt.rm(), rs);
1007 li(scratch, rt);
1012 void TurboAssembler::Ror(Register rd, Register rs, const Operand& rt) {
1013 if (rt.is_reg()) {
1014 rotrv(rd, rs, rt.rm());
1016 int64_t ror_value = rt.immediate() % 32;
1024 void TurboAssembler::Dror(Register rd, Register rs, const Operand& rt) {
1025 if (rt.is_reg()) {
1026 drotrv(rd, rs, rt.rm());
1028 int64_t dror_value = rt.immediate() % 64;
1042 void TurboAssembler::Lsa(Register rd, Register rt, Register rs, uint8_t sa,
1046 lsa(rd, rt, rs, sa - 1);
1048 Register tmp = rd == rt ? scratch : rd;
1049 DCHECK(tmp != rt);
1051 Addu(rd, rt, tmp);
1055 void TurboAssembler::Dlsa(Register rd, Register rt, Register rs, uint8_t sa,
1059 dlsa(rd, rt, rs, sa - 1);
1061 Register tmp = rd == rt ? scratch : rd;
1062 DCHECK(tmp != rt);
1067 Daddu(rd, rt, tmp);
1071 void TurboAssembler::Bovc(Register rs, Register rt, Label* L) {
1074 bnvc(rs, rt, &skip);
1078 bovc(rs, rt, L);
1082 void TurboAssembler::Bnvc(Register rs, Register rt, Label* L) {
1085 bovc(rs, rt, &skip);
1089 bnvc(rs, rt, L);
1994 void TurboAssembler::Ext(Register rt, Register rs, uint16_t pos,
1998 ext_(rt, rs, pos, size);
2001 void TurboAssembler::Dext(Register rt, Register rs, uint16_t pos,
2006 dextm_(rt, rs, pos, size);
2008 dextu_(rt, rs, pos, size);
2010 dext_(rt, rs, pos, size);
2014 void TurboAssembler::Ins(Register rt, Register rs, uint16_t pos,
2019 ins_(rt, rs, pos, size);
2022 void TurboAssembler::Dins(Register rt, Register rs, uint16_t pos,
2027 dins_(rt, rs, pos, size);
2029 dinsm_(rt, rs, pos, size);
2031 dinsu_(rt, rs, pos, size);
3010 void TurboAssembler::Movz(Register rd, Register rs, Register rt) {
3013 Branch(&done, ne, rt, Operand(zero_reg));
3017 movz(rd, rs, rt);
3021 void TurboAssembler::Movn(Register rd, Register rs, Register rt) {
3024 Branch(&done, eq, rt, Operand(zero_reg));
3028 movn(rd, rs, rt);
3033 const Operand& rt, Condition cond) {
3041 if (rt.is_reg()) {
3042 LoadZeroIfConditionZero(rd, rt.rm());
3044 if (rt.immediate() == 0) {
3050 } else if (IsZero(rt)) {
3053 Dsubu(t9, rs, rt);
3059 if (rt.is_reg()) {
3060 LoadZeroIfConditionNotZero(rd, rt.rm());
3062 if (rt.immediate() != 0) {
3068 } else if (IsZero(rt)) {
3071 Dsubu(t9, rs, rt);
3078 Sgt(t9, rs, rt);
3082 Sge(t9, rs, rt);
3084 // rs >= rt
3087 Slt(t9, rs, rt);
3089 // rs < rt
3092 Sle(t9, rs, rt);
3094 // rs <= rt
3099 Sgtu(t9, rs, rt);
3101 // rs > rt
3105 Sgeu(t9, rs, rt);
3107 // rs >= rt
3110 Sltu(t9, rs, rt);
3112 // rs < rt
3115 Sleu(t9, rs, rt);
3117 // rs <= rt
3360 #define BRANCH_ARGS_CHECK(cond, rs, rt) \
3361 DCHECK((cond == cc_always && rs == zero_reg && rt.rm() == zero_reg) || \
3362 (cond != cc_always && (rs != zero_reg || rt.rm() != zero_reg)))
3370 const Operand& rt, BranchDelaySlot bdslot) {
3371 bool is_near = BranchShortCheck(offset, nullptr, cond, rs, rt, bdslot);
3393 const Operand& rt, BranchDelaySlot bdslot) {
3395 if (!BranchShortCheck(0, L, cond, rs, rt, bdslot)) {
3399 BranchShort(&skip, neg_cond, rs, rt);
3411 BranchShort(&skip, neg_cond, rs, rt);
3418 BranchShort(L, cond, rs, rt, bdslot);
3474 Register TurboAssembler::GetRtAsRegisterHelper(const Operand& rt,
3477 if (rt.is_reg()) {
3478 r2 = rt.rm();
3481 li(r2, rt);
3495 Register* scratch, const Operand& rt) {
3497 *scratch = GetRtAsRegisterHelper(rt, *scratch);
3504 const Operand& rt) {
3521 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3524 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3528 } else if (IsZero(rt)) {
3533 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3539 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3542 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3546 } else if (IsZero(rt)) {
3551 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3559 // rs > rt
3560 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3563 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3566 } else if (IsZero(rt)) {
3570 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3577 // rs >= rt
3578 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3582 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3585 } else if (IsZero(rt)) {
3589 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3596 // rs < rt
3597 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3600 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3603 } else if (IsZero(rt)) {
3607 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3614 // rs <= rt
3615 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3619 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3622 } else if (IsZero(rt)) {
3626 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3635 // rs > rt
3636 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3639 if (!CalculateOffset(L, &offset, OffsetSize::kOffset21, &scratch, rt))
3642 } else if (IsZero(rt)) {
3646 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3653 // rs >= rt
3654 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3658 if (!CalculateOffset(L, &offset, OffsetSize::kOffset21, &scratch, rt))
3661 } else if (IsZero(rt)) {
3665 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3672 // rs < rt
3673 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3676 if (!CalculateOffset(L, &offset, OffsetSize::kOffset21, &scratch, rt))
3679 } else if (IsZero(rt)) {
3682 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3689 // rs <= rt
3690 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3694 if (!CalculateOffset(L, &offset, OffsetSize::kOffset26, &scratch, rt))
3697 } else if (IsZero(rt)) {
3701 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3716 Register rs, const Operand& rt,
3737 if (IsZero(rt)) {
3742 scratch = GetRtAsRegisterHelper(rt, scratch);
3748 if (IsZero(rt)) {
3753 scratch = GetRtAsRegisterHelper(rt, scratch);
3761 if (IsZero(rt)) {
3765 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3771 if (IsZero(rt)) {
3775 Slt(scratch, rs, rt);
3781 if (IsZero(rt)) {
3785 Slt(scratch, rs, rt);
3791 if (IsZero(rt)) {
3795 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3803 if (IsZero(rt)) {
3807 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3813 if (IsZero(rt)) {
3817 Sltu(scratch, rs, rt);
3823 if (IsZero(rt)) {
3826 Sltu(scratch, rs, rt);
3832 if (IsZero(rt)) {
3836 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3853 Register rs, const Operand& rt,
3855 BRANCH_ARGS_CHECK(cond, rs, rt);
3860 return BranchShortHelperR6(offset, nullptr, cond, rs, rt);
3863 return BranchShortHelper(offset, nullptr, cond, rs, rt, bdslot);
3868 return BranchShortHelperR6(0, L, cond, rs, rt);
3870 return BranchShortHelper(0, L, cond, rs, rt, bdslot);
3876 const Operand& rt, BranchDelaySlot bdslot) {
3877 BranchShortCheck(offset, nullptr, cond, rs, rt, bdslot);
3881 const Operand& rt, BranchDelaySlot bdslot) {
3882 BranchShortCheck(0, L, cond, rs, rt, bdslot);
3890 const Operand& rt, BranchDelaySlot bdslot) {
3891 bool is_near = BranchAndLinkShortCheck(offset, nullptr, cond, rs, rt, bdslot);
3913 const Operand& rt, BranchDelaySlot bdslot) {
3915 if (!BranchAndLinkShortCheck(0, L, cond, rs, rt, bdslot)) {
3918 BranchShort(&skip, neg_cond, rs, rt);
3926 BranchShort(&skip, neg_cond, rs, rt);
3930 BranchAndLinkShortCheck(0, L, cond, rs, rt, bdslot);
3972 const Operand& rt) {
3987 Subu(scratch, rs, rt);
3993 Subu(scratch, rs, rt);
4000 // rs > rt
4001 if (rs.code() == rt.rm().code()) {
4004 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
4007 } else if (IsZero(rt)) {
4012 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
4018 // rs >= rt
4019 if (rs.code() == rt.rm().code()) {
4023 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
4026 } else if (IsZero(rt)) {
4031 Slt(scratch, rs, rt);
4037 // rs < rt
4038 if (rs.code() == rt.rm().code()) {
4041 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
4044 } else if (IsZero(rt)) {
4049 Slt(scratch, rs, rt);
4056 if (rs.code() == rt.rm().code()) {
4060 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
4063 } else if (IsZero(rt)) {
4068 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
4078 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
4085 Sltu(scratch, rs, rt);
4092 Sltu(scratch, rs, rt);
4099 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
4114 const Operand& rt,
4128 bne(rs, GetRtAsRegisterHelper(rt, scratch), 2);
4134 beq(rs, GetRtAsRegisterHelper(rt, scratch), 2);
4142 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
4148 Slt(scratch, rs, rt);
4154 Slt(scratch, rs, rt);
4160 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
4168 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
4174 Sltu(scratch, rs, rt);
4180 Sltu(scratch, rs, rt);
4186 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
4204 const Operand& rt,
4206 BRANCH_ARGS_CHECK(cond, rs, rt);
4211 return BranchAndLinkShortHelperR6(offset, nullptr, cond, rs, rt);
4214 return BranchAndLinkShortHelper(offset, nullptr, cond, rs, rt, bdslot);
4219 return BranchAndLinkShortHelperR6(0, L, cond, rs, rt);
4221 return BranchAndLinkShortHelper(0, L, cond, rs, rt, bdslot);
4250 const Operand& rt, BranchDelaySlot bd) {
4256 BRANCH_ARGS_CHECK(cond, rs, rt);
4257 Branch(2, NegateCondition(cond), rs, rt);
4264 BRANCH_ARGS_CHECK(cond, rs, rt);
4265 Branch(2, NegateCondition(cond), rs, rt);
4274 Condition cond, Register rs, const Operand& rt,
4278 Branch(USE_DELAY_SLOT, &skip, NegateCondition(cond), rs, rt);
4291 Register rs, const Operand& rt, BranchDelaySlot bd) {
4293 Jump(static_cast<intptr_t>(target), rmode, cond, rs, rt, bd);
4297 Condition cond, Register rs, const Operand& rt,
4305 Jump(t9, cond, rs, rt, bd);
4314 Jump(t9, cond, rs, rt, bd);
4320 Jump(static_cast<intptr_t>(code.address()), rmode, cond, rs, rt, bd);
4330 const Operand& rt, BranchDelaySlot bd) {
4336 BRANCH_ARGS_CHECK(cond, rs, rt);
4337 Branch(2, NegateCondition(cond), rs, rt);
4344 BRANCH_ARGS_CHECK(cond, rs, rt);
4345 Branch(2, NegateCondition(cond), rs, rt);
4369 Register rs, const Operand& rt, BranchDelaySlot bd) {
4372 Call(t9, cond, rs, rt, bd);
4376 Condition cond, Register rs, const Operand& rt,
4383 Call(t9, cond, rs, rt, bd);
4392 Call(t9, cond, rs, rt, bd);
4400 Call(code.address(), rmode, cond, rs, rt, bd);
4498 void TurboAssembler::Ret(Condition cond, Register rs, const Operand& rt,
4500 Jump(ra, cond, rs, rt, bd);
5260 Operand rt) {
5261 if (FLAG_debug_code) Check(cc, reason, rs, rt);
5265 Operand rt) {
5267 Branch(&L, cc, rs, rt);