Lines Matching defs:const
41 static inline bool IsZero(const Operand& rt) {
52 Register exclusion3) const {
105 const Operand& src2) {
338 void TurboAssembler::Addu(Register rd, Register rs, const Operand& rt) {
355 void TurboAssembler::Daddu(Register rd, Register rs, const Operand& rt) {
372 void TurboAssembler::Subu(Register rd, Register rs, const Operand& rt) {
398 void TurboAssembler::Dsubu(Register rd, Register rs, const Operand& rt) {
426 void TurboAssembler::Mul(Register rd, Register rs, const Operand& rt) {
439 void TurboAssembler::Mulh(Register rd, Register rs, const Operand& rt) {
462 void TurboAssembler::Mulhu(Register rd, Register rs, const Operand& rt) {
485 void TurboAssembler::Dmul(Register rd, Register rs, const Operand& rt) {
508 void TurboAssembler::Dmulh(Register rd, Register rs, const Operand& rt) {
531 void TurboAssembler::Mult(Register rs, const Operand& rt) {
544 void TurboAssembler::Dmult(Register rs, const Operand& rt) {
557 void TurboAssembler::Multu(Register rs, const Operand& rt) {
570 void TurboAssembler::Dmultu(Register rs, const Operand& rt) {
583 void TurboAssembler::Div(Register rs, const Operand& rt) {
596 void TurboAssembler::Div(Register res, Register rs, const Operand& rt) {
619 void TurboAssembler::Mod(Register rd, Register rs, const Operand& rt) {
642 void TurboAssembler::Modu(Register rd, Register rs, const Operand& rt) {
665 void TurboAssembler::Ddiv(Register rs, const Operand& rt) {
678 void TurboAssembler::Ddiv(Register rd, Register rs, const Operand& rt) {
706 void TurboAssembler::Divu(Register rs, const Operand& rt) {
719 void TurboAssembler::Divu(Register res, Register rs, const Operand& rt) {
742 void TurboAssembler::Ddivu(Register rs, const Operand& rt) {
755 void TurboAssembler::Ddivu(Register res, Register rs, const Operand& rt) {
778 void TurboAssembler::Dmod(Register rd, Register rs, const Operand& rt) {
806 void TurboAssembler::Dmodu(Register rd, Register rs, const Operand& rt) {
834 void TurboAssembler::And(Register rd, Register rs, const Operand& rt) {
851 void TurboAssembler::Or(Register rd, Register rs, const Operand& rt) {
868 void TurboAssembler::Xor(Register rd, Register rs, const Operand& rt) {
885 void TurboAssembler::Nor(Register rd, Register rs, const Operand& rt) {
898 void TurboAssembler::Neg(Register rs, const Operand& rt) {
902 void TurboAssembler::Slt(Register rd, Register rs, const Operand& rt) {
920 void TurboAssembler::Sltu(Register rd, Register rs, const Operand& rt) {
924 const uint64_t int16_min = std::numeric_limits<int16_t>::min();
944 void TurboAssembler::Sle(Register rd, Register rs, const Operand& rt) {
959 void TurboAssembler::Sleu(Register rd, Register rs, const Operand& rt) {
974 void TurboAssembler::Sge(Register rd, Register rs, const Operand& rt) {
979 void TurboAssembler::Sgeu(Register rd, Register rs, const Operand& rt) {
984 void TurboAssembler::Sgt(Register rd, Register rs, const Operand& rt) {
998 void TurboAssembler::Sgtu(Register rd, Register rs, const Operand& rt) {
1012 void TurboAssembler::Ror(Register rd, Register rs, const Operand& rt) {
1024 void TurboAssembler::Dror(Register rd, Register rs, const Operand& rt) {
1038 void MacroAssembler::Pref(int32_t hint, const MemOperand& rs) {
1125 void TurboAssembler::Ulw(Register rd, const MemOperand& rs) {
1149 void TurboAssembler::Ulwu(Register rd, const MemOperand& rs) {
1159 void TurboAssembler::Usw(Register rd, const MemOperand& rs) {
1176 void TurboAssembler::Ulh(Register rd, const MemOperand& rs) {
1210 void TurboAssembler::Ulhu(Register rd, const MemOperand& rs) {
1244 void TurboAssembler::Ush(Register rd, const MemOperand& rs, Register scratch) {
1273 void TurboAssembler::Uld(Register rd, const MemOperand& rs) {
1300 void MacroAssembler::LoadWordPair(Register rd, const MemOperand& rs,
1308 void TurboAssembler::Usd(Register rd, const MemOperand& rs) {
1325 void MacroAssembler::StoreWordPair(Register rd, const MemOperand& rs,
1332 void TurboAssembler::Ulwc1(FPURegister fd, const MemOperand& rs,
1343 void TurboAssembler::Uswc1(FPURegister fd, const MemOperand& rs,
1354 void TurboAssembler::Uldc1(FPURegister fd, const MemOperand& rs,
1366 void TurboAssembler::Usdc1(FPURegister fd, const MemOperand& rs,
1378 void TurboAssembler::Lb(Register rd, const MemOperand& rs) {
1384 void TurboAssembler::Lbu(Register rd, const MemOperand& rs) {
1390 void TurboAssembler::Sb(Register rd, const MemOperand& rs) {
1396 void TurboAssembler::Lh(Register rd, const MemOperand& rs) {
1402 void TurboAssembler::Lhu(Register rd, const MemOperand& rs) {
1408 void TurboAssembler::Sh(Register rd, const MemOperand& rs) {
1414 void TurboAssembler::Lw(Register rd, const MemOperand& rs) {
1420 void TurboAssembler::Lwu(Register rd, const MemOperand& rs) {
1426 void TurboAssembler::Sw(Register rd, const MemOperand& rs) {
1432 void TurboAssembler::Ld(Register rd, const MemOperand& rs) {
1438 void TurboAssembler::Sd(Register rd, const MemOperand& rs) {
1444 void TurboAssembler::Lwc1(FPURegister fd, const MemOperand& src) {
1450 void TurboAssembler::Swc1(FPURegister fs, const MemOperand& src) {
1456 void TurboAssembler::Ldc1(FPURegister fd, const MemOperand& src) {
1462 void TurboAssembler::Sdc1(FPURegister fs, const MemOperand& src) {
1468 void TurboAssembler::Ll(Register rd, const MemOperand& rs) {
1482 void TurboAssembler::Lld(Register rd, const MemOperand& rs) {
1496 void TurboAssembler::Sc(Register rd, const MemOperand& rs) {
1510 void TurboAssembler::Scd(Register rd, const MemOperand& rs) {
1546 void TurboAssembler::li(Register dst, const StringConstantBase* string,
3033 const Operand& rt, Condition cond) {
3370 const Operand& rt, BranchDelaySlot bdslot) {
3393 const Operand& rt, BranchDelaySlot bdslot) {
3474 Register TurboAssembler::GetRtAsRegisterHelper(const Operand& rt,
3495 Register* scratch, const Operand& rt) {
3504 const Operand& rt) {
3716 Register rs, const Operand& rt,
3853 Register rs, const Operand& rt,
3876 const Operand& rt, BranchDelaySlot bdslot) {
3881 const Operand& rt, BranchDelaySlot bdslot) {
3890 const Operand& rt, BranchDelaySlot bdslot) {
3913 const Operand& rt, BranchDelaySlot bdslot) {
3972 const Operand& rt) {
4114 const Operand& rt,
4204 const Operand& rt,
4250 const Operand& rt, BranchDelaySlot bd) {
4274 Condition cond, Register rs, const Operand& rt,
4291 Register rs, const Operand& rt, BranchDelaySlot bd) {
4297 Condition cond, Register rs, const Operand& rt,
4323 void TurboAssembler::Jump(const ExternalReference& reference) {
4330 const Operand& rt, BranchDelaySlot bd) {
4369 Register rs, const Operand& rt, BranchDelaySlot bd) {
4376 Condition cond, Register rs, const Operand& rt,
4498 void TurboAssembler::Ret(Condition cond, Register rs, const Operand& rt,
4623 const Operand& r2) {
4639 const Operand& op) {
4750 void TurboAssembler::FPUCanonicalizeNaN(const DoubleRegister dst,
4751 const DoubleRegister src) {
4755 void TurboAssembler::MovFromFloatResult(const DoubleRegister dst) {
4767 void TurboAssembler::MovFromFloatParameter(const DoubleRegister dst) {
4806 const DoubleRegister fparg2 = f13;
5078 const Operand& right, Register overflow) {
5109 const Operand& right, Register overflow) {
5140 const Operand& right, Register overflow) {
5169 void MacroAssembler::CallRuntime(const Runtime::Function* f, int num_arguments,
5192 const Runtime::Function* function = Runtime::FunctionForId(fid);
5200 void MacroAssembler::JumpToExternalReference(const ExternalReference& builtin,
5277 const char* msg = GetAbortReason(reason);
5315 static const int kExpectedAbortInstructions = 10;
5413 const int frame_alignment = MacroAssembler::ActivationFrameAlignment();
5518 const int frame_alignment = ActivationFrameAlignment();
5519 const int frame_alignment_mask = frame_alignment - 1;
5537 void TurboAssembler::SmiUntag(Register dst, const MemOperand& src) {
5896 static const int kRegisterPassedArguments = 8;
6078 const RegisterConfiguration* config = RegisterConfiguration::Default();