Lines Matching defs:opcode
442 uint32_t opcode = GetOpcodeField(instr);
444 if (opcode == COP1) {
466 uint32_t opcode = GetOpcodeField(instr);
471 opcode == BEQ || opcode == BNE || opcode == BLEZ || opcode == BGTZ ||
472 opcode == BEQL || opcode == BNEL || opcode == BLEZL || opcode == BGTZL ||
473 (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ ||
475 (opcode == COP1 && rs_field == BC1) || // Coprocessor branch.
476 (opcode == COP1 && rs_field == BC1EQZ) ||
477 (opcode == COP1 && rs_field == BC1NEZ) || IsMsaBranch(instr);
481 isBranch |= opcode == POP10 || opcode == POP30 || opcode == BC ||
482 opcode == BALC ||
483 (opcode == POP66 && rs_field != 0) || // BEQZC
484 (opcode == POP76 && rs_field != 0); // BNEZC
490 uint32_t opcode = GetOpcodeField(instr);
492 return opcode == BC || opcode == BALC;
496 uint32_t opcode = GetOpcodeField(instr);
499 return opcode == REGIMM && rt_field == BLTZAL && rs_field == 0;
503 uint32_t opcode = GetOpcodeField(instr);
505 return (opcode == POP66 && GetRsField(instr) != 0) ||
506 (opcode == POP76 && GetRsField(instr) != 0);
519 uint32_t opcode = GetOpcodeField(instr);
520 return opcode == POP66 && GetRsField(instr) != 0;
524 uint32_t opcode = GetOpcodeField(instr);
525 return opcode == POP76 && GetRsField(instr) != 0;
529 uint32_t opcode = GetOpcodeField(instr);
532 return opcode == POP10 && rs != 0 && rs < rt; // && rt != 0
536 uint32_t opcode = GetOpcodeField(instr);
539 return opcode == POP30 && rs != 0 && rs < rt; // && rt != 0
543 uint32_t opcode = GetOpcodeField(instr);
551 bool res = opcode == SPECIAL && function_field == OR && rd_field == rd_reg &&
557 uint32_t opcode = GetOpcodeField(instr);
562 return opcode == J || opcode == JAL ||
563 (opcode == SPECIAL && rt_field == 0 &&
569 uint32_t opcode = GetOpcodeField(instr);
571 return opcode == J;
585 uint32_t opcode = GetOpcodeField(instr);
587 return opcode == LUI;
591 uint32_t opcode = GetOpcodeField(instr);
593 return opcode == ORI;
599 uint32_t opcode = GetOpcodeField(instr);
611 bool ret = (opcode == SPECIAL && function == SLL &&
1038 uint32_t opcode = GetOpcodeField(instr);
1039 switch (opcode) {
1067 void Assembler::GenInstrRegister(Opcode opcode, Register rs, Register rt,
1071 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1076 void Assembler::GenInstrRegister(Opcode opcode, Register rs, Register rt,
1080 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1085 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt,
1089 Instr instr = opcode | fmt | (ft.code() << kFtShift) |
1094 void Assembler::GenInstrRegister(Opcode opcode, FPURegister fr, FPURegister ft,
1098 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) |
1103 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt,
1107 Instr instr = opcode | fmt | (rt.code() << kRtShift) |
1112 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt,
1116 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func;
1122 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, Register rt,
1126 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1131 void Assembler::GenInstrImmediate(Opcode opcode, Register base, Register rt,
1136 Instr instr = opcode | (base.code() << kBaseShift) | (rt.code() << kRtShift) |
1142 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, SecondaryField SF,
1146 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
1150 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, FPURegister ft,
1154 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) |
1159 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, int32_t offset21,
1162 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1166 void Assembler::GenInstrImmediate(Opcode opcode, Register rs,
1169 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1173 void Assembler::GenInstrImmediate(Opcode opcode, int32_t offset26,
1176 Instr instr = opcode | (offset26 & kImm26Mask);
1180 void Assembler::GenInstrJump(Opcode opcode, uint32_t address) {
1183 Instr instr = opcode | address;
2254 // This instruction uses same opcode as 'lui'. The difference in encoding is
3169 #define MSA_BRANCH(name, opcode) \
3171 GenInstrMsaBranch(opcode, wt, offset); \
3188 #define MSA_LD_ST(name, opcode, b) \
3194 GenInstrMsaMI10(opcode, source.offset() / b, source.rm(), wd); \
3200 GenInstrMsaMI10(opcode, 0, scratch, wd); \
3235 #define MSA_I5_FORMAT(name, opcode, format) \
3238 GenInstrMsaI5(opcode, I5_DF_##format, imm5, ws, wd); \
3241 #define MSA_I5(name, opcode) \
3242 MSA_I5_FORMAT(name, opcode, b) \
3243 MSA_I5_FORMAT(name, opcode, h) \
3244 MSA_I5_FORMAT(name, opcode, w) \
3245 MSA_I5_FORMAT(name, opcode, d)
3264 #define MSA_I8(name, opcode) \
3266 GenInstrMsaI8(opcode, imm8, ws, wd); \
3282 #define MSA_VEC(name, opcode) \
3284 GenInstrMsaVec(opcode, wt, ws, wd); \
3296 #define MSA_2R_FORMAT(name, opcode, format) \
3298 GenInstrMsa2R(opcode, MSA_2R_DF_##format, ws, wd); \
3301 #define MSA_2R(name, opcode) \
3302 MSA_2R_FORMAT(name, opcode, b) \
3303 MSA_2R_FORMAT(name, opcode, h) \
3304 MSA_2R_FORMAT(name, opcode, w) \
3305 MSA_2R_FORMAT(name, opcode, d)
3346 #define MSA_2RF_FORMAT(name, opcode, format) \
3348 GenInstrMsa2RF(opcode, MSA_2RF_DF_##format, ws, wd); \
3351 #define MSA_2RF(name, opcode) \
3352 MSA_2RF_FORMAT(name, opcode, w) \
3353 MSA_2RF_FORMAT(name, opcode, d)
3423 #define MSA_3R_FORMAT(name, opcode, format) \
3426 GenInstrMsa3R<MSARegister>(opcode, MSA_3R_DF_##format, wt, ws, wd); \
3429 #define MSA_3R_FORMAT_SLD_SPLAT(name, opcode, format) \
3432 GenInstrMsa3R<Register>(opcode, MSA_3R_DF_##format, rt, ws, wd); \
3435 #define MSA_3R(name, opcode) \
3436 MSA_3R_FORMAT(name, opcode, b) \
3437 MSA_3R_FORMAT(name, opcode, h) \
3438 MSA_3R_FORMAT(name, opcode, w) \
3439 MSA_3R_FORMAT(name, opcode, d)
3441 #define MSA_3R_SLD_SPLAT(name, opcode) \
3442 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, b) \
3443 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, h) \
3444 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, w) \
3445 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, d)
3502 #define MSA_3RF_FORMAT(name, opcode, df, df_c) \
3505 GenInstrMsa3RF(opcode, df_c, wt, ws, wd); \
3508 #define MSA_3RF_1(name, opcode) \
3509 MSA_3RF_FORMAT(name, opcode, w, 0) \
3510 MSA_3RF_FORMAT(name, opcode, d, 1)
3512 #define MSA_3RF_2(name, opcode) \
3513 MSA_3RF_FORMAT(name, opcode, h, 0) \
3514 MSA_3RF_FORMAT(name, opcode, w, 1)
3654 #define MSA_BIT_FORMAT(name, opcode, format) \
3657 GenInstrMsaBit(opcode, BIT_DF_##format, m, ws, wd); \
3660 #define MSA_BIT(name, opcode) \
3661 MSA_BIT_FORMAT(name, opcode, b) \
3662 MSA_BIT_FORMAT(name, opcode, h) \
3663 MSA_BIT_FORMAT(name, opcode, w) \
3664 MSA_BIT_FORMAT(name, opcode, d)