Lines Matching defs:code
8 // - Redistributions of source code must retain the above copyright notice,
31 // The original source code covered by the above license above has been
60 // If the compiler is allowed to use FPU then we can use FPU too in our code
79 // code generation.
143 return kNumbers[reg.code()];
164 // always the case inside code objects.
236 const Instr kPopInstruction = DADDIU | (sp.code() << kRsShift) |
237 (sp.code() << kRtShift) |
240 const Instr kPushInstruction = DADDIU | (sp.code() << kRsShift) |
241 (sp.code() << kRtShift) |
244 const Instr kPushRegPattern = SD | (sp.code() << kRsShift) | (0 & kImm16Mask);
246 const Instr kPopRegPattern = LD | (sp.code() << kRsShift) | (0 & kImm16Mask);
249 LW | (fp.code() << kRsShift) | (0 & kImm16Mask);
252 SW | (fp.code() << kRsShift) | (0 & kImm16Mask);
255 LW | (fp.code() << kRsShift) | (kNegOffset & kImm16Mask);
258 SW | (fp.code() << kRsShift) | (kNegOffset & kImm16Mask);
298 // metadata table builders (safepoint, handler, constant pool, code
310 // Set up code descriptor.
422 // Labels refer to positions in the (to be) generated code.
426 // generated code. pos() is the position the label refers to.
428 // Linked labels refer to unknown positions in the code
435 // code is conv to an 18-bit value addressing bytes, hence the -4 value.
547 uint32_t rd_reg = static_cast<uint32_t>(rd.code());
548 uint32_t rs_reg = static_cast<uint32_t>(rs.code());
837 Instr instr_a = DADDIU | ra.code() << kRsShift | ra.code() << kRtShift |
914 // When code is committed it will be resolved to j/jal.
924 // When code is committed it will be resolved to j/jal.
1071 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1072 (rd.code() << kRdShift) | (sa << kSaShift) | func;
1080 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1089 Instr instr = opcode | fmt | (ft.code() << kFtShift) |
1090 (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
1098 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) |
1099 (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
1107 Instr instr = opcode | fmt | (rt.code() << kRtShift) |
1108 (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
1116 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func;
1126 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1136 Instr instr = opcode | (base.code() << kBaseShift) | (rt.code() << kRtShift) |
1146 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
1154 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) |
1162 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1169 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1194 (ws.code() << kWsShift) | (wd.code() << kWdShift);
1208 (ws.code() << kWsShift) | (wd.code() << kWdShift);
1217 (ws.code() << kWsShift) | (wd.code() << kWdShift);
1226 (wd.code() << kWdShift);
1235 Instr instr = MSA | operation | df | (t.code() << kWtShift) |
1236 (ws.code() << kWsShift) | (wd.code() << kWdShift);
1246 (src.code() << kWsShift) | (dst.code() << kWdShift) |
1256 Instr instr = MSA | operation | (df << 21) | (wt.code() << kWtShift) |
1257 (ws.code() << kWsShift) | (wd.code() << kWdShift);
1265 Instr instr = MSA | operation | (wt.code() << kWtShift) |
1266 (ws.code() << kWsShift) | (wd.code() << kWdShift) |
1276 (rs.code() << kWsShift) | (wd.code() << kWdShift);
1284 Instr instr = MSA | MSA_2R_FORMAT | operation | df | (ws.code() << kWsShift) |
1285 (wd.code() << kWdShift) | MSA_VEC_2R_2RF_MINOR;
1294 (ws.code() << kWsShift) | (wd.code() << kWdShift) |
1305 COP1 | operation | (wt.code() << kWtShift) | (offset16 & kImm16Mask);
1475 DCHECK(rs.code() != rt.code());
1483 DCHECK(rs.code() != rt.code());
1531 DCHECK(rs.code() != rt.code());
1539 DCHECK(rs.code() != rt.code());
1565 if (rs.code() >= rt.code()) {
1574 if (rs.code() >= rt.code()) {
1638 DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0);
1639 if (rs.code() < rt.code()) {
1654 DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0);
1655 if (rs.code() < rt.code()) {
1699 DCHECK(rs.code() != rd.code());
1927 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) |
1928 (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
1936 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1937 (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
1959 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) |
1960 (rd.code() << kRdShift) | (sa << kSaShift) | DSRL;
1966 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) |
1967 (rd.code() << kRdShift) | (sa << kSaShift) | DSRL32;
1973 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1974 (rd.code() << kRdShift) | (1 << kSaShift) | DSRLV;
2002 Instr instr = SPECIAL | rs.code() << kRsShift | rt.code() << kRtShift |
2003 rd.code() << kRdShift | sa << kSaShift | LSA;
2011 Instr instr = SPECIAL | rs.code() << kRsShift | rt.code() << kRtShift |
2012 rd.code() << kRdShift | sa << kSaShift | DLSA;
2355 void Assembler::break_(uint32_t code, bool break_as_stop) {
2356 DCHECK_EQ(code & ~0xFFFFF, 0);
2361 (break_as_stop && code <= kMaxStopCode && code > kMaxWatchpointCode) ||
2362 (!break_as_stop && (code > kMaxStopCode || code <= kMaxWatchpointCode)));
2363 Instr break_instr = SPECIAL | BREAK | (code << 6);
2367 void Assembler::stop(uint32_t code) {
2368 DCHECK_GT(code, kMaxWatchpointCode);
2369 DCHECK_LE(code, kMaxStopCode);
2373 break_(code, true);
2377 void Assembler::tge(Register rs, Register rt, uint16_t code) {
2378 DCHECK(is_uint10(code));
2380 SPECIAL | TGE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2384 void Assembler::tgeu(Register rs, Register rt, uint16_t code) {
2385 DCHECK(is_uint10(code));
2386 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift | rt.code() << kRtShift |
2387 code << 6;
2391 void Assembler::tlt(Register rs, Register rt, uint16_t code) {
2392 DCHECK(is_uint10(code));
2394 SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2398 void Assembler::tltu(Register rs, Register rt, uint16_t code) {
2399 DCHECK(is_uint10(code));
2400 Instr instr = SPECIAL | TLTU | rs.code() << kRsShift | rt.code() << kRtShift |
2401 code << 6;
2405 void Assembler::teq(Register rs, Register rt, uint16_t code) {
2406 DCHECK(is_uint10(code));
2408 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2412 void Assembler::tne(Register rs, Register rt, uint16_t code) {
2413 DCHECK(is_uint10(code));
2415 SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2616 PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift) | (rs.offset_);
3080 Instr instr = COP1 | fmt | ft.code() << kFtShift | fs.code() << kFsShift |
3081 fd.code() << kFdShift | (0 << 5) | cond;
3098 Instr instr = COP1 | BC1EQZ | ft.code() << kFtShift | (offset & kImm16Mask);
3106 Instr instr = COP1 | BC1NEZ | ft.code() << kFtShift | (offset & kImm16Mask);
3118 Instr instr = COP1 | fmt | ft.code() << kFtShift | fs.code() << kFsShift |
3317 (rs.code() << kWsShift) | (wd.code() << kWdShift) | \
3619 Instr instr = MSA | MOVE_V | (ws.code() << kWsShift) |
3620 (wd.code() << kWdShift) | MSA_ELM_MINOR;
3627 Instr instr = MSA | CTCMSA | (rs.code() << kWsShift) |
3628 (cd.code() << kWdShift) | MSA_ELM_MINOR;
3635 Instr instr = MSA | CFCMSA | (cs.code() << kWsShift) |
3636 (rd.code() << kWdShift) | MSA_ELM_MINOR;
3952 // in code on MIP64 because only 48-bits of address is effectively used.
3968 // Must use 4 instructions to insure patchable code.