Lines Matching refs:rt
41 static inline bool IsZero(const Operand& rt) {
42 if (rt.is_reg()) {
43 return rt.rm() == zero_reg;
45 return rt.immediate() == 0;
343 void TurboAssembler::Addu(Register rd, Register rs, const Operand& rt) {
344 if (rt.is_reg()) {
345 addu(rd, rs, rt.rm());
347 if (is_int16(rt.immediate()) && !MustUseReg(rt.rmode())) {
348 addiu(rd, rs, rt.immediate());
354 li(scratch, rt);
360 void TurboAssembler::Subu(Register rd, Register rs, const Operand& rt) {
361 if (rt.is_reg()) {
362 subu(rd, rs, rt.rm());
364 if (is_int16(-rt.immediate()) && !MustUseReg(rt.rmode())) {
365 addiu(rd, rs, -rt.immediate()); // No subiu instr, use addiu(x, y, -imm).
366 } else if (!(-rt.immediate() & kHiMask) &&
367 !MustUseReg(rt.rmode())) { // Use load
372 li(scratch, -rt.immediate());
379 li(scratch, rt);
385 void TurboAssembler::Mul(Register rd, Register rs, const Operand& rt) {
386 if (rt.is_reg()) {
388 mult(rs, rt.rm());
391 mul(rd, rs, rt.rm());
398 li(scratch, rt);
409 const Operand& rt) {
410 if (rt.is_reg()) {
412 mult(rs, rt.rm());
418 DCHECK(rd_hi != rt.rm() && rd_lo != rt.rm());
419 muh(rd_hi, rs, rt.rm());
420 mul(rd_lo, rs, rt.rm());
422 DCHECK(rd_hi != rt.rm() && rd_lo != rt.rm());
423 mul(rd_lo, rs, rt.rm());
424 muh(rd_hi, rs, rt.rm());
432 li(scratch, rt);
453 const Operand& rt) {
457 if (rt.is_reg()) {
458 reg = rt.rm();
462 li(reg, rt);
483 void TurboAssembler::Mulh(Register rd, Register rs, const Operand& rt) {
484 if (rt.is_reg()) {
486 mult(rs, rt.rm());
489 muh(rd, rs, rt.rm());
496 li(scratch, rt);
506 void TurboAssembler::Mult(Register rs, const Operand& rt) {
507 if (rt.is_reg()) {
508 mult(rs, rt.rm());
514 li(scratch, rt);
519 void TurboAssembler::Mulhu(Register rd, Register rs, const Operand& rt) {
520 if (rt.is_reg()) {
522 multu(rs, rt.rm());
525 muhu(rd, rs, rt.rm());
532 li(scratch, rt);
542 void TurboAssembler::Multu(Register rs, const Operand& rt) {
543 if (rt.is_reg()) {
544 multu(rs, rt.rm());
550 li(scratch, rt);
555 void TurboAssembler::Div(Register rs, const Operand& rt) {
556 if (rt.is_reg()) {
557 div(rs, rt.rm());
563 li(scratch, rt);
569 const Operand& rt) {
570 if (rt.is_reg()) {
572 div(rs, rt.rm());
576 div(res, rs, rt.rm());
577 mod(rem, rs, rt.rm());
584 li(scratch, rt);
596 void TurboAssembler::Div(Register res, Register rs, const Operand& rt) {
597 if (rt.is_reg()) {
599 div(rs, rt.rm());
602 div(res, rs, rt.rm());
609 li(scratch, rt);
619 void TurboAssembler::Mod(Register rd, Register rs, const Operand& rt) {
620 if (rt.is_reg()) {
622 div(rs, rt.rm());
625 mod(rd, rs, rt.rm());
632 li(scratch, rt);
642 void TurboAssembler::Modu(Register rd, Register rs, const Operand& rt) {
643 if (rt.is_reg()) {
645 divu(rs, rt.rm());
648 modu(rd, rs, rt.rm());
655 li(scratch, rt);
665 void TurboAssembler::Divu(Register rs, const Operand& rt) {
666 if (rt.is_reg()) {
667 divu(rs, rt.rm());
673 li(scratch, rt);
678 void TurboAssembler::Divu(Register res, Register rs, const Operand& rt) {
679 if (rt.is_reg()) {
681 divu(rs, rt.rm());
684 divu(res, rs, rt.rm());
691 li(scratch, rt);
701 void TurboAssembler::And(Register rd, Register rs, const Operand& rt) {
702 if (rt.is_reg()) {
703 and_(rd, rs, rt.rm());
705 if (is_uint16(rt.immediate()) && !MustUseReg(rt.rmode())) {
706 andi(rd, rs, rt.immediate());
712 li(scratch, rt);
718 void TurboAssembler::Or(Register rd, Register rs, const Operand& rt) {
719 if (rt.is_reg()) {
720 or_(rd, rs, rt.rm());
722 if (is_uint16(rt.immediate()) && !MustUseReg(rt.rmode())) {
723 ori(rd, rs, rt.immediate());
729 li(scratch, rt);
735 void TurboAssembler::Xor(Register rd, Register rs, const Operand& rt) {
736 if (rt.is_reg()) {
737 xor_(rd, rs, rt.rm());
739 if (is_uint16(rt.immediate()) && !MustUseReg(rt.rmode())) {
740 xori(rd, rs, rt.immediate());
746 li(scratch, rt);
752 void TurboAssembler::Nor(Register rd, Register rs, const Operand& rt) {
753 if (rt.is_reg()) {
754 nor(rd, rs, rt.rm());
760 li(scratch, rt);
765 void TurboAssembler::Neg(Register rs, const Operand& rt) {
766 subu(rs, zero_reg, rt.rm());
769 void TurboAssembler::Slt(Register rd, Register rs, const Operand& rt) {
770 if (rt.is_reg()) {
771 slt(rd, rs, rt.rm());
773 if (is_int16(rt.immediate()) && !MustUseReg(rt.rmode())) {
774 slti(rd, rs, rt.immediate());
781 li(scratch, rt);
787 void TurboAssembler::Sltu(Register rd, Register rs, const Operand& rt) {
788 if (rt.is_reg()) {
789 sltu(rd, rs, rt.rm());
792 if (is_uint15(rt.immediate()) && !MustUseReg(rt.rmode())) {
794 sltiu(rd, rs, rt.immediate());
795 } else if (is_uint15(rt.immediate() - int16_min) &&
796 !MustUseReg(rt.rmode())) {
798 sltiu(rd, rs, static_cast<uint16_t>(rt.immediate()));
805 li(scratch, rt);
811 void TurboAssembler::Sle(Register rd, Register rs, const Operand& rt) {
812 if (rt.is_reg()) {
813 slt(rd, rt.rm(), rs);
820 li(scratch, rt);
826 void TurboAssembler::Sleu(Register rd, Register rs, const Operand& rt) {
827 if (rt.is_reg()) {
828 sltu(rd, rt.rm(), rs);
835 li(scratch, rt);
841 void TurboAssembler::Sge(Register rd, Register rs, const Operand& rt) {
842 Slt(rd, rs, rt);
846 void TurboAssembler::Sgeu(Register rd, Register rs, const Operand& rt) {
847 Sltu(rd, rs, rt);
851 void TurboAssembler::Sgt(Register rd, Register rs, const Operand& rt) {
852 if (rt.is_reg()) {
853 slt(rd, rt.rm(), rs);
860 li(scratch, rt);
865 void TurboAssembler::Sgtu(Register rd, Register rs, const Operand& rt) {
866 if (rt.is_reg()) {
867 sltu(rd, rt.rm(), rs);
874 li(scratch, rt);
879 void TurboAssembler::Ror(Register rd, Register rs, const Operand& rt) {
881 if (rt.is_reg()) {
882 rotrv(rd, rs, rt.rm());
884 rotr(rd, rs, rt.immediate() & 0x1F);
887 if (rt.is_reg()) {
891 subu(scratch, zero_reg, rt.rm());
893 srlv(rd, rs, rt.rm());
896 if (rt.immediate() == 0) {
901 srl(scratch, rs, rt.immediate() & 0x1F);
902 sll(rd, rs, (0x20 - (rt.immediate() & 0x1F)) & 0x1F);
917 void TurboAssembler::Lsa(Register rd, Register rt, Register rs, uint8_t sa,
921 lsa(rd, rt, rs, sa - 1);
923 Register tmp = rd == rt ? scratch : rd;
924 DCHECK(tmp != rt);
926 Addu(rd, rt, tmp);
930 void TurboAssembler::Bovc(Register rs, Register rt, Label* L) {
933 bnvc(rs, rt, &skip);
937 bovc(rs, rt, L);
941 void TurboAssembler::Bnvc(Register rs, Register rt, Label* L) {
944 bovc(rs, rt, &skip);
948 bnvc(rs, rt, L);
1666 void TurboAssembler::Ext(Register rt, Register rs, uint16_t pos,
1672 ext_(rt, rs, pos, size);
1674 // Move rs to rt and shift it left then right to get the
1677 sll(rt, rs, shift_left); // Acts as a move if shift_left == 0.
1681 srl(rt, rt, shift_right);
1686 void TurboAssembler::Ins(Register rt, Register rs, uint16_t pos,
1693 ins_(rt, rs, pos, size);
1695 DCHECK(rt != t8 && rs != t8);
1705 and_(scratch, rt, scratch);
1706 or_(rt, t8, scratch);
1739 void TurboAssembler::Seb(Register rd, Register rt) {
1741 seb(rd, rt);
1744 sll(rd, rt, 24);
1749 void TurboAssembler::Seh(Register rd, Register rt) {
1751 seh(rd, rt);
1754 sll(rd, rt, 16);
2103 void TurboAssembler::Mthc1(Register rt, FPURegister fs) {
2105 mtc1(rt, fs.high());
2109 mthc1(rt, fs);
2113 void TurboAssembler::Mfhc1(Register rt, FPURegister fs) {
2115 mfc1(rt, fs.high());
2119 mfhc1(rt, fs);
2364 const Operand& rt, Condition cond) {
2372 if (rt.is_reg()) {
2373 LoadZeroIfConditionZero(rd, rt.rm());
2375 if (rt.immediate() == 0) {
2381 } else if (IsZero(rt)) {
2384 Subu(t9, rs, rt);
2390 if (rt.is_reg()) {
2391 LoadZeroIfConditionNotZero(rd, rt.rm());
2393 if (rt.immediate() != 0) {
2399 } else if (IsZero(rt)) {
2402 Subu(t9, rs, rt);
2409 Sgt(t9, rs, rt);
2413 Sge(t9, rs, rt);
2415 // rs >= rt
2418 Slt(t9, rs, rt);
2420 // rs < rt
2423 Sle(t9, rs, rt);
2425 // rs <= rt
2430 Sgtu(t9, rs, rt);
2432 // rs > rt
2436 Sgeu(t9, rs, rt);
2438 // rs >= rt
2441 Sltu(t9, rs, rt);
2443 // rs < rt
2446 Sleu(t9, rs, rt);
2448 // rs <= rt
2491 void TurboAssembler::Movz(Register rd, Register rs, Register rt) {
2494 Branch(&done, ne, rt, Operand(zero_reg));
2498 movz(rd, rs, rt);
2502 void TurboAssembler::Movn(Register rd, Register rs, Register rt) {
2505 Branch(&done, eq, rt, Operand(zero_reg));
2509 movn(rd, rs, rt);
2721 #define BRANCH_ARGS_CHECK(cond, rs, rt) \
2722 DCHECK((cond == cc_always && rs == zero_reg && rt.rm() == zero_reg) || \
2723 (cond != cc_always && (rs != zero_reg || rt.rm() != zero_reg)))
2731 const Operand& rt, BranchDelaySlot bdslot) {
2732 bool is_near = BranchShortCheck(offset, nullptr, cond, rs, rt, bdslot);
2754 const Operand& rt, BranchDelaySlot bdslot) {
2756 if (!BranchShortCheck(0, L, cond, rs, rt, bdslot)) {
2760 BranchShort(&skip, neg_cond, rs, rt);
2772 BranchShort(&skip, neg_cond, rs, rt);
2779 BranchShort(L, cond, rs, rt, bdslot);
2835 Register TurboAssembler::GetRtAsRegisterHelper(const Operand& rt,
2838 if (rt.is_reg()) {
2839 r2 = rt.rm();
2842 li(r2, rt);
2856 Register* scratch, const Operand& rt) {
2858 *scratch = GetRtAsRegisterHelper(rt, *scratch);
2865 const Operand& rt) {
2881 if (rt.is_reg() && rs.code() == rt.rm().code()) {
2884 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2888 } else if (IsZero(rt)) {
2893 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2899 if (rt.is_reg() && rs.code() == rt.rm().code()) {
2902 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2906 } else if (IsZero(rt)) {
2911 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2919 // rs > rt
2920 if (rt.is_reg() && rs.code() == rt.rm().code()) {
2923 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2926 } else if (IsZero(rt)) {
2930 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2937 // rs >= rt
2938 if (rt.is_reg() && rs.code() == rt.rm().code()) {
2942 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2945 } else if (IsZero(rt)) {
2949 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2956 // rs < rt
2957 if (rt.is_reg() && rs.code() == rt.rm().code()) {
2960 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2963 } else if (IsZero(rt)) {
2967 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2974 // rs <= rt
2975 if (rt.is_reg() && rs.code() == rt.rm().code()) {
2979 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2982 } else if (IsZero(rt)) {
2986 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
2995 // rs > rt
2996 if (rt.is_reg() && rs.code() == rt.rm().code()) {
2999 if (!CalculateOffset(L, &offset, OffsetSize::kOffset21, &scratch, rt))
3002 } else if (IsZero(rt)) {
3006 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3013 // rs >= rt
3014 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3018 if (!CalculateOffset(L, &offset, OffsetSize::kOffset21, &scratch, rt))
3021 } else if (IsZero(rt)) {
3025 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3032 // rs < rt
3033 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3036 if (!CalculateOffset(L, &offset, OffsetSize::kOffset21, &scratch, rt))
3039 } else if (IsZero(rt)) {
3042 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3049 // rs <= rt
3050 if (rt.is_reg() && rs.code() == rt.rm().code()) {
3054 if (!CalculateOffset(L, &offset, OffsetSize::kOffset26, &scratch, rt))
3057 } else if (IsZero(rt)) {
3061 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3076 Register rs, const Operand& rt,
3096 if (IsZero(rt)) {
3101 scratch = GetRtAsRegisterHelper(rt, scratch);
3107 if (IsZero(rt)) {
3112 scratch = GetRtAsRegisterHelper(rt, scratch);
3120 if (IsZero(rt)) {
3124 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3130 if (IsZero(rt)) {
3134 Slt(scratch, rs, rt);
3140 if (IsZero(rt)) {
3144 Slt(scratch, rs, rt);
3150 if (IsZero(rt)) {
3154 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3162 if (IsZero(rt)) {
3166 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3172 if (IsZero(rt)) {
3176 Sltu(scratch, rs, rt);
3182 if (IsZero(rt)) {
3185 Sltu(scratch, rs, rt);
3191 if (IsZero(rt)) {
3195 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3211 Register rs, const Operand& rt,
3213 BRANCH_ARGS_CHECK(cond, rs, rt);
3217 return BranchShortHelperR6(offset, nullptr, cond, rs, rt);
3220 return BranchShortHelper(offset, nullptr, cond, rs, rt, bdslot);
3225 return BranchShortHelperR6(0, L, cond, rs, rt);
3227 return BranchShortHelper(0, L, cond, rs, rt, bdslot);
3233 const Operand& rt, BranchDelaySlot bdslot) {
3234 BranchShortCheck(offset, nullptr, cond, rs, rt, bdslot);
3238 const Operand& rt, BranchDelaySlot bdslot) {
3239 BranchShortCheck(0, L, cond, rs, rt, bdslot);
3247 const Operand& rt, BranchDelaySlot bdslot) {
3248 bool is_near = BranchAndLinkShortCheck(offset, nullptr, cond, rs, rt, bdslot);
3270 const Operand& rt, BranchDelaySlot bdslot) {
3272 if (!BranchAndLinkShortCheck(0, L, cond, rs, rt, bdslot)) {
3275 BranchShort(&skip, neg_cond, rs, rt);
3283 BranchShort(&skip, neg_cond, rs, rt);
3287 BranchAndLinkShortCheck(0, L, cond, rs, rt, bdslot);
3329 const Operand& rt) {
3344 Subu(scratch, rs, rt);
3350 Subu(scratch, rs, rt);
3357 // rs > rt
3358 if (rs.code() == rt.rm().code()) {
3361 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3364 } else if (IsZero(rt)) {
3369 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3375 // rs >= rt
3376 if (rs.code() == rt.rm().code()) {
3380 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3383 } else if (IsZero(rt)) {
3388 Slt(scratch, rs, rt);
3394 // rs < rt
3395 if (rs.code() == rt.rm().code()) {
3398 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3401 } else if (IsZero(rt)) {
3406 Slt(scratch, rs, rt);
3413 if (rs.code() == rt.rm().code()) {
3417 if (!CalculateOffset(L, &offset, OffsetSize::kOffset16, &scratch, rt))
3420 } else if (IsZero(rt)) {
3425 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3435 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3442 Sltu(scratch, rs, rt);
3449 Sltu(scratch, rs, rt);
3456 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3471 const Operand& rt,
3485 bne(rs, GetRtAsRegisterHelper(rt, scratch), 2);
3491 beq(rs, GetRtAsRegisterHelper(rt, scratch), 2);
3499 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3505 Slt(scratch, rs, rt);
3511 Slt(scratch, rs, rt);
3517 Slt(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3525 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3531 Sltu(scratch, rs, rt);
3537 Sltu(scratch, rs, rt);
3543 Sltu(scratch, GetRtAsRegisterHelper(rt, scratch), rs);
3561 const Operand& rt,
3563 BRANCH_ARGS_CHECK(cond, rs, rt);
3568 return BranchAndLinkShortHelperR6(offset, nullptr, cond, rs, rt);
3571 return BranchAndLinkShortHelper(offset, nullptr, cond, rs, rt, bdslot);
3576 return BranchAndLinkShortHelperR6(0, L, cond, rs, rt);
3578 return BranchAndLinkShortHelper(0, L, cond, rs, rt, bdslot);
3607 Register rs, const Operand& rt, BranchDelaySlot bd) {
3614 BRANCH_ARGS_CHECK(cond, rs, rt);
3615 Branch(2, NegateCondition(cond), rs, rt);
3625 BRANCH_ARGS_CHECK(cond, rs, rt);
3626 Branch(2, NegateCondition(cond), rs, rt);
3635 Condition cond, Register rs, const Operand& rt,
3643 BRANCH_ARGS_CHECK(cond, rs, rt);
3644 Branch(2, NegateCondition(cond), rs, rt);
3656 BRANCH_ARGS_CHECK(cond, rs, rt);
3657 Branch(2, NegateCondition(cond), rs, rt);
3666 Condition cond, Register rs, const Operand& rt,
3679 BRANCH_ARGS_CHECK(cond, rs, rt);
3680 Branch(2, NegateCondition(cond), rs, rt);
3690 BRANCH_ARGS_CHECK(cond, rs, rt);
3691 Branch(2, NegateCondition(cond), rs, rt);
3700 Condition cond, Register rs, const Operand& rt,
3705 Branch(USE_DELAY_SLOT, &skip, NegateCondition(cond), rs, rt);
3725 Register rs, const Operand& rt, BranchDelaySlot bd) {
3727 Jump(static_cast<intptr_t>(target), rmode, cond, rs, rt, bd);
3731 Condition cond, Register rs, const Operand& rt,
3748 Branch(USE_DELAY_SLOT, &skip, NegateCondition(cond), rs, rt);
3756 Jump(t9, Code::kHeaderSize - kHeapObjectTag, cond, rs, rt, bd);
3763 Jump(t9, 0, cond, rs, rt, bd);
3768 Jump(static_cast<intptr_t>(code.address()), rmode, cond, rs, rt, bd);
3792 Register rs, const Operand& rt, BranchDelaySlot bd) {
3799 BRANCH_ARGS_CHECK(cond, rs, rt);
3800 Branch(2, NegateCondition(cond), rs, rt);
3810 BRANCH_ARGS_CHECK(cond, rs, rt);
3811 Branch(2, NegateCondition(cond), rs, rt);
3822 Condition cond, Register rs, const Operand& rt,
3830 BRANCH_ARGS_CHECK(cond, rs, rt);
3831 Branch(2, NegateCondition(cond), rs, rt);
3843 BRANCH_ARGS_CHECK(cond, rs, rt);
3844 Branch(2, NegateCondition(cond), rs, rt);
3854 Register rs, const Operand& rt, BranchDelaySlot bd) {
3865 Call(t9, jialc_offset, cond, rs, rt, bd);
3868 Call(t9, 0, cond, rs, rt, bd);
3873 Condition cond, Register rs, const Operand& rt,
3887 Branch(PROTECT, &skip, NegateCondition(cond), rs, rt);
3895 Call(t9, Code::kHeaderSize - kHeapObjectTag, cond, rs, rt, bd);
3902 Call(t9, 0, cond, rs, rt, bd);
3909 Call(code.address(), rmode, cond, rs, rt, bd);
4004 void TurboAssembler::Ret(Condition cond, Register rs, const Operand& rt,
4006 Jump(ra, 0, cond, rs, rt, bd);
4726 Operand rt) {
4727 if (FLAG_debug_code) Check(cc, reason, rs, rt);
4731 Operand rt) {
4733 Branch(&L, cc, rs, rt);